KR100256240B1 - Method of forming contact plug using selective tungsten growth - Google Patents

Method of forming contact plug using selective tungsten growth Download PDF

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KR100256240B1
KR100256240B1 KR1019920019165A KR920019165A KR100256240B1 KR 100256240 B1 KR100256240 B1 KR 100256240B1 KR 1019920019165 A KR1019920019165 A KR 1019920019165A KR 920019165 A KR920019165 A KR 920019165A KR 100256240 B1 KR100256240 B1 KR 100256240B1
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South Korea
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barrier metal
deposited
contact hole
tungsten
polysilicon film
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KR1019920019165A
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Korean (ko)
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KR940010201A (en
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최경근
김춘환
박흥락
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

PURPOSE: A method for forming a contact plug is to reduce a junction leakage between a silicon substrate and a polysilicon layer by depositing the polysilicon layer in a contact hole after depositing an etching barrier metal. CONSTITUTION: After a contact hole is formed on a silicon substrate(1) and the polysilicon layer(3), an etching barrier metal(5) is deposited on the contact hole. After the second polysilicon layer(6) is deposited on the etching barrier metal, the second polysilicon layer is blanket-etched. Then, a portion of the second polysilicon layer, which is deposited in parallel to the substrate, is removed to expose the etching barrier metal. After an inside of the contact hole is buried with a tungsten plug(7) by selectively depositing a tungsten film in the contact hole, an aluminium alloy(8) is deposited on the substrate. The etching barrier metal is deposited at a thickness of 900 to 1100 angstroms. The second polysilicon layer is deposited at a thickness of 250 to 350 angstroms at a temperature of 550 to 700 deg.C.

Description

식각장벽 금속과 폴리실리콘막 에치백을 이용한 선택 텅스텐의 일방성 성장 유도에 의한 콘택 플러그 형성 방법Method for forming contact plug by inducing unidirectional growth of selective tungsten using etch barrier metal and polysilicon film etchback

제1도는 본 발명에 따른 콘택 플러그 형성 제조 공정도.1 is a process diagram for forming a contact plug according to the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 실리콘 기판 2 : 소자 분리 절연막1 silicon substrate 2 device isolation insulating film

3, 6 : 폴리실리콘막 4 : 산화막3, 6: polysilicon film 4: oxide film

5 : 식각장벽 금속 물질 7 : 텅스텐 플러그5: etching barrier metal material 7: tungsten plug

8 : 알루미늄합금막8: aluminum alloy film

본 발명은 콘택 플러그 형성 방법에 관한 것으로, 특히 식각 장벽 금속과 폴리실리콘막 에치백을 이용한 선택 텅스텐의 일방성 성장 유도에 의한 콘택 플러그 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact plug, and more particularly, to a method for forming a contact plug by inducing unidirectional growth of selective tungsten using an etch barrier metal and a polysilicon film etchback.

일반적인 반도체 플러그 형성에서 선택 텅스텐 화학 기상 증착공정은 반응원 기체로 WF6와 반응기체를 환원 시키기위해 H2와 SiH4를 사용하는데, 이때 수소환원 또는 SiH4환원의 경우 수소가 존재 하여도 아래 나타난 반응이 우선적으로 진행 하게 되어 표면의 규소가 식각되면서 기판이 손상을 입어 회로에 여러 문제점들을 야기 시켜 왔다.Selective tungsten chemical vapor deposition process uses H 2 and SiH 4 to reduce WF 6 and reactants as reactant gases, where hydrogen reduction or SiH 4 reduction is shown below. The reaction proceeds preferentially and the silicon on the surface is etched, which damages the substrate and causes circuit problems.

2WF3+ 3Si → 2W + 3SiF4 2WF 3 + 3Si → 2W + 3SiF 4

따라서 이러한 문제점을 해결 하기 위한 종래의 텅스텐 플러그 형성 과정은 폴리실리콘막을 먼저 증착시킨 후에 텅스텐을 증착하는 것으로(특허 출원 번호 91-16516), 이는 폴리실리콘막 에치백(etch back)시 발생되는 실리콘 기판 표면 어택(attack)으로 인한 접합 누설이 또한 문제가 되었다.Therefore, the conventional tungsten plug forming process to solve this problem is to deposit the polysilicon film first and then deposit the tungsten (Patent Application No. 91-16516), which is a silicon substrate generated during the etch back of the polysilicon film Bond leakage due to surface attack has also been a problem.

상기 문제점을 해결하기 위하여 안출된 본 발명은 식각 장벽 금속 물질을 먼저 증착한 후에 폴리실리콘막을 콘택 홀 내에만 증착하여 실리콘 기판과 접합 누설을 감소 시키는 식각장벽 금속과 폴리실리콘막 에치백을 이용한 선택 텅스텐의 일방성 성장 유도에 의한 콘택 플러그 형성 방법을 제공 하는데 그 목적이 있다.In order to solve the above problems, the present invention provides a selective tungsten using an etch barrier metal and a polysilicon etch back to reduce the leakage of junction with a silicon substrate by first depositing an etch barrier metal material and then depositing a polysilicon layer only in a contact hole. It is an object of the present invention to provide a method for forming a contact plug by inducing unidirectional growth.

상기 목적을 달성 하기 위하여 본 발명은 상기 실리콘 기판과 폴리실리콘막에 콘택홀을 형성한 다음에 상기 콘택홀에 식각장벽 금속 물질을 증착하는 제 1 단계, 상기 제 1 단계 후에 상기 콘택홀에 증착된 식각장벽 금속 물질 상에 제 2 폴리실리콘막을 증착한 후에 제 2 폴리실리콘막을 전면식각(blanket etch)하고 상기 실리콘 기판과 수평으로 증착된 제 2 폴리실리콘막을 제거하여 콘택홀 바닥에 상기 식각장벽 금속 물질이 노출되게 하는 제 2 단계, 상기 제 2 단계 후에 콘택홀내를 텅스텐막으로 선택 증착하여 콘택홀내를 텅스텐 플러그로 완전히 매립 시킨 후에 알루미늄 합금을 증착하는 제 3 단계를 특징으로 한다.In order to achieve the above object, the present invention provides a first step of forming a contact hole in the silicon substrate and the polysilicon layer, and then depositing an etch barrier metal material in the contact hole, which is deposited in the contact hole after the first step. After depositing the second polysilicon film on the etch barrier metal material, the second polysilicon film is etched by a blanket etch, and the second polysilicon film deposited horizontally with the silicon substrate is removed to remove the second polysilicon film on the bottom of the contact hole. And a third step of selectively depositing the contact hole with a tungsten film after the second step of exposing the contact hole to completely fill the contact hole with a tungsten plug and then depositing an aluminum alloy.

이하, 첨부된 도면 제 1 도를 참조 하여 본 발명에 따른 일실시예를 상세히 설명하면, 제 1 도는 본 발명에 따른 콘택 플러그 형성 제조 공정도로서, 도면에서 1은 실리콘 기판, 2는 소자 분리 절연막, 3,6은 폴리실리콘막, 4는 산화막, 5는 식각장벽 금속 물질, 7은 텅스텐 플러그, 8은 알루미늄합금막을 각각 나타낸다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a manufacturing process diagram of a contact plug forming device according to the present invention, in which 1 is a silicon substrate, 2 is a device isolation insulating film, 3 and 6 are polysilicon films, 4 are oxide films, 5 is an etch barrier metal material, 7 is a tungsten plug, and 8 is an aluminum alloy film.

먼저, 실리콘 기판(1)에 소정의 크기로 소자 분리 절연막(2), 층간에 제 1 폴리실리콘막(3)을 포함 하고 있는 산화막(4)을 갖는 반도체 소자에 상기 실리콘 기판(1)과 폴리실리콘막(3)에 콘택홀을 형성한 다음에 상기 콘택홀에 식각장벽 금속 물질(5)(Ti,TiN)을 스퍼터링 방법으로 900 내지 1100Å정도 증착한다(제 1 도 (a)).First, the silicon substrate 1 and the poly in the semiconductor device having the element isolation insulating film 2 in the silicon substrate 1 and the oxide film 4 including the first polysilicon film 3 between the layers. After forming a contact hole in the silicon film 3, an etching barrier metal material 5 (Ti, TiN) is deposited in the contact hole by about 900 to 1100 kPa by the sputtering method (FIG. 1 (a)).

그리고 상기 콘택홀에 증착된 식각장벽 금속 물질(5) 상에 제 2 폴리실리콘막(6)을 LPCVD(low pressure chemical vapor deposition)방법으로 550 내지 700℃에서 250 내지 350Å 정도로 증착한다(제 1 도(b)).The second polysilicon film 6 is deposited on the etch barrier metal material 5 deposited in the contact hole by about 250 to 350 kPa at 550 to 700 ° C. by low pressure chemical vapor deposition (LPCVD). (b)).

이어서, RIE(reactive lon etcher) 반응기에서 상기 제 2 폴리실리콘막(6)을 전면식각(blanket etch)하여 상기 실리콘 기판(1)과 수평으로 증착된 제 2 폴리실리콘막(6)을 제거함으로써 콘택홀 바닥에 상기 식각장벽 금속 물질(5)이 노출되게 한다(제 1 도(c)).Subsequently, the second polysilicon film 6 is blanket etched in a reactive lon etcher (RIE) reactor to remove the second polysilicon film 6 deposited horizontally with the silicon substrate 1. The etch barrier metal material 5 is exposed at the bottom of the hole (FIG. 1 (c)).

끝으로, WF6, SiH4, H2, Ar을 이용한 텅스텐 LPCVD방법으로 콘택홀내를 텅스텐 플러그(7)로 선택 증착하여 콘택홀내를 텅스텐막(7)으로 완전히 매립 시킨 후에 알루미늄합금(8)을 증착한다.(제 1 도(d)).Finally, the tungsten LPCVD method using WF 6 , SiH 4 , H 2 , and Ar is used to selectively deposit the inside of the contact hole with a tungsten plug (7) to completely fill the contact hole with the tungsten film (7). To deposit (FIG. 1 (d)).

이에 따른 본 발명의 작용 상태를 살펴보면 상기 텅스텐 플러그(7)는 폴리실리콘막과 TiN(5)의 잠복기 차이 때문에 콘택 측벽의 제 2 폴리실리콘막(6)에서는 텅스텐이 성장되고 콘택홀 하단부 TiN에서는 거의 어택을 제거하며 동시에 Si소비를 제거 한다. 그리고 TiN과 폴리실리콘막 적층을 이용함으로써 콘택 측벽에서만 텅스텐 성장을 유도하게된다. 또한 산화막 위에 증착된 TiN 박막에서는 TiN 박막의 잠복기 때문에 텅스텐이 성장하지 않는다.According to the operation state of the present invention, the tungsten plug 7 has tungsten grown on the second polysilicon film 6 of the contact sidewall due to the difference in latency between the polysilicon film and the TiN 5, and nearly at the bottom TiN of the contact hole. It removes attack and at the same time removes Si consumption. In addition, by using TiN and polysilicon layer stacking, tungsten growth is induced only at the contact sidewalls. Further, in the TiN thin film deposited on the oxide film, tungsten does not grow because of the latent TiN thin film.

상기와 같이 이루어 지는 본 발명은 콘택 하부에서의 텅스텐 성장을 최대한 억제 하고 콘택 측벽에서 텅스텐 성장을 유도 하기 때문에 기판의 손상을 억제 할 수 있어 소자의 신뢰성과 수율을 향상 시키는 효과가 있다.The present invention made as described above can suppress the damage of the substrate because the tungsten growth is suppressed as much as possible and the tungsten growth in the contact sidewall can be suppressed, thereby improving the reliability and yield of the device.

Claims (3)

실리콘 기판(1)에 소정의 크기로 소자 분리 절연막(2), 층간에 제 1 폴리실리콘막(3)을 포함 하고 있는 산화막(4)을 갖는 반도체 소자의 식각장벽 금속과 폴리실리콘막 에치백을 이용한 선택 텅스텐의 일방성 성장 유도에 의한 콘택 플러그 형성 방법에 있어서, 상기 실리콘 기판(1)과 폴리실리콘막(3)에 콘택홀을 형성한 다음에 상기 콘택홀에서 식각장벽 금속 물질(5)을 증착하는 제 1 단계, 상기 제 1 단계 후에 상기 콘택홀에 증착된 식각장벽 금속 물질(5) 상에 제 2 폴리실리콘막(6)을 증착한 후에 제 2 폴리실리콘막(6)을 전면식각(blanket etch)하고 상기 실리콘 기판(1)과 수평으로 증착된 제 2 폴리실리콘막(6)을 제거하여 콘택홀 바닥에 상기 식각장벽 금속 물질(5)이 노출되게 하는 제 2 단계, 및 상기 제 2 단계 후에 콘택홀내를 텅스텐막(7)으로 선택 증착하여 콘택홀내를 텅스텐 플러그(7)로 완전히 매립 시킨 후에 알루미늄합금(8)을 증착하는 제 3 단계를 포함하여 이루어 지는 것을 특징으로 하는 식각장벽 금속과 폴리실리콘막 에치백을 이용한 선택 텅스턴의 일방성 성장 유도에 의한 콘택 플러그 형성 방법.An etching barrier metal and a polysilicon film etchback of a semiconductor device having an element isolation insulating film 2 and an oxide film 4 including a first polysilicon film 3 between layers in a silicon substrate 1 with a predetermined size. In the method for forming a contact plug by inducing unidirectional growth of selected tungsten, a contact hole is formed in the silicon substrate 1 and the polysilicon film 3, and then an etch barrier metal material 5 is formed in the contact hole. After depositing the second polysilicon layer 6 on the etch barrier metal material 5 deposited in the contact hole after the first step of depositing the first step, the second polysilicon layer 6 is etched. a second step of exposing the etch barrier metal material 5 to the bottom of the contact hole by blanket etching and removing the second polysilicon film 6 deposited horizontally with the silicon substrate 1, and the second After the step, the contact hole is selectively deposited with a tungsten film 7 to Unidirectional of the selected tungsten using an etch barrier metal and a polysilicon film etch back, comprising a third step of depositing the aluminum alloy 8 after the tack hole is completely filled with the tungsten plug 7. Method for forming contact plug by inducing growth. 제1항에 있어서, 제 1 단계의 식각장벽 금속 물질(5)은 스퍼터링 방법으로 900 내지 1100Å 두께로 증착 되어 지는 것을 특징으로 하는 식각장벽 금속과 폴리실리콘막 에치백을 이용한 선택 텅스텐의 일방성 성장 유도에 의한 콘택 플러그 형성 방법.The unidirectional growth of selective tungsten using an etch barrier metal and a polysilicon etch back according to claim 1, wherein the etching barrier metal material 5 of the first step is deposited to a thickness of 900 to 1100 mm by a sputtering method. Method for forming contact plug by induction. 제1항에 있어서, 상기 제 2 단계의 제 2 폴리실리콘막(6)은 PCVD(low pressure chemical vapor deposition)방법으로 550 내지 700℃에서 250 내지 350Å 정도로 증착되어 지는 것을 특징으로 하는 식각장벽 금속과 폴리실리콘막 에치백을 이용한 선택 텅스텐의 일방성 성장 유도에 의한 콘택 플러그 형성 방법.The method of claim 1, wherein the second polysilicon film 6 of the second step is deposited by an etch barrier metal, characterized in that deposited by CVD at low pressure chemical vapor deposition (PCVD) method at about 550 to 700 ℃ 250 ~ 350Å. A method for forming a contact plug by inducing unidirectional growth of selective tungsten using a polysilicon film etchback.
KR1019920019165A 1992-10-19 1992-10-19 Method of forming contact plug using selective tungsten growth KR100256240B1 (en)

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