KR100253389B1 - Peripheral circuit for semiconductor device - Google Patents

Abstract

PURPOSE: A peripheral circuit of a semiconductor device is provided to reduce an inspection time of a wafer by excluding an apparatus, which is determined as a defective one during the first wafer inspection, from inspection targets during the second wafer inspection. CONSTITUTION: According to the peripheral circuit, when a test power supply voltage(VTM) of a high voltage is applied during a test mode, an NMOS transistor(NM1) is turned on. Then, if the device is a good one, an internal power supply voltage(Vint) of the device is applied to a pad(10) through the NMOS transistor. Accordingly, if the internal power supply voltage of the NMOS transistor is applied to the pad, the device is determined as a good one. If, the device is a defective one, the internal power supply voltage is not generated and thus is not applied to the pad. Then, in a normal operation, the test mode signal of a low voltage is applied and thus the NMOS transistor is turned off, and thus an internal power supply voltage detection part(11) is disconnected with the pad. Here, an NMOS transistor(NM2) controls the voltage difference between a node(A) and the pad to be below a threshold voltage(Vt) of the NMOS transistor(NM1), in order to prevent the NMOS transistor(NM1) from being turned on when a minus voltage is applied to the pad. By repeating the above procedure, the state of the device is secondary-evaluated, and the defective device is excluded from the second evaluation by making a fuse(F1) be blown which is connected to the internal power supply voltage detection part.

Description

Peripheral Circuits of Semiconductor Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device device, and more particularly, to a semiconductor device device capable of reducing unnecessary time by performing a defective process by quickly determining a defective product in an initial evaluation in a wafer state.

In recent years, the trend of semiconductor devices has been actively researched in order to be suitable for large capacity and high speed of information from 64M DRAM, which has been put to practical use, to next generation 256M DRAM.

Accordingly, the problem of sharing the evaluation time of the device due to the large capacity also has a great effect on the productivity of the product, and many methods have been devised for reducing the evaluation time.

Currently, the evaluation of the product of the device generally used is subjected to the first evaluation in the state of the first wafer after the process is completed, and the condition of the device is classified into three types, such as a defective product and a good product, and a device that can be repaired as a good product from the defective product.

After the classification is completed, the inspection is performed on the device that can be used to repair the defective product. After the second evaluation in the state of the wafer, the result is determined whether the product is converted to the good product. When the second judgment is completed, the assembly is started as a finished product. do.

FIG. 1 is a circuit diagram showing a configuration of a peripheral circuit of a conventional semiconductor device. As shown in FIG. 1, an internal power supply detecting unit 11 is connected to a drain of an NMOS transistor NM1 having a pad 10 connected to a source. The internal power detector 11 connects a source of the NMOS transistor NM2 applied to the drain to a gate of the NMOS transistor NM1, applies a test power source VTM to the connection point, and applies the NMOS transistor The ground voltage VSS is applied to the gate of NM2, and the operation of the conventional circuit configured as described above will be described.

First, when the test power source VTM is applied at high potential in the test mode, the NMOS transistor NM1 is turned on.

At this time, if the device state is good, the internal power supply Vint of the device is applied to the pad 10 through the NMOS transistor NM1.

That is, when the internal power supply Vint is applied to the pad 10, the device is determined as good quality.

If the device state is defective, the internal power Vint of the device does not occur, and thus, the internal power Vint is not applied to the pad 10.

That is, when the state of the device is defective, the internal power supply Vint is not applied to the pad 10, and when the device state is good, the internal power supply Vint is applied to the pad 10.

Thereafter, the above operation is repeated one more time to evaluate the state of the device.

In this case, since the test mode signal VTM is applied at a low potential when it is normally operated, the NMOS transistor NM1 is turned off to disconnect the connection between the internal power detector 11 and the pad 10.

Here, in order to prevent the NMOS transistor from being turned on when a negative voltage is applied to the pad 10, the NMOS transistor NM2 has a potential difference between the node A and the pad 10. Adjust so that it becomes below the threshold voltage Vt of NM1).

However, conventionally, even in the case of a device judged to be a defective product after the primary wafer evaluation, an evaluation for distinguishing a good product from a defective product is performed again when the secondary wafer is evaluated, thereby causing a problem of loss of time and deterioration in productivity.

Accordingly, the present invention devised in view of the above problems provides a semiconductor device peripheral circuit which can reduce the time by excluding a device which is determined as defective in the evaluation of the first wafer from the evaluation target in the evaluation of the second wafer. There is a purpose.

1 is a circuit diagram showing a configuration of a conventional semiconductor device peripheral circuit.

2 is a circuit diagram showing a configuration of a peripheral circuit of the semiconductor device of the present invention.

***** Description of the symbols for the main parts of the drawings *****

10: Pad 11: Internal power detector

The purpose is to connect a fuse having an internal power supply detection part connected to a drain of a first NMOS transistor having a pad connected to a source, and a gate and a source of the first NMOS transistor commonly connected to the connection point. 2 is connected to the drain of the NMOS transistor, a test power is applied to a common connection point between the gate of the first NMOS transistor and the source of the second NMOS transistor, and the ground voltage is applied to the gate of the second NMOS transistor. It is achieved by the configuration to be applied, this invention will be described with reference to the accompanying drawings.

FIG. 2 is a circuit diagram showing the configuration of a peripheral circuit of the semiconductor device according to the present invention. As shown therein, an internal power supply detecting unit 11 is connected to one side of a drain of an NMOS transistor NM1 having a pad 10 connected to a source. The connected fuse F1, and the gate of the nMOS transistor NM1 and the drain of the NMOS transistor NM2 having a common source connected to the connection point thereof, and the gate of the NMOS transistor NM1 and the gate. The test power supply VTM is applied to a common connection point of the source of the NMOS transistor NM2, and the ground voltage VSS is applied to the gate of the NMOS transistor NM2. Explain.

First, the general operation is the same as in the prior art. That is, when the test power source VTM is applied at high potential in the test mode, the NMOS transistor NM1 is turned on.

At this time, if the device state is good, the internal power supply Vint of the device is applied to the pad 10 through the NMOS transistor NM1.

Accordingly, when the internal power source NM1 is applied to the pad 10, the device is determined as good quality.

If the device state is defective, the internal power Vint of the device does not occur, and thus, the internal power Vint is not applied to the pad 10.

That is, when the state of the device is defective, the internal power supply Vint is not applied to the pad 10, and when the device state is good, the internal power supply Vint is applied to the pad 10.

In this case, since the test mode signal VTM is applied at a low potential when it is normally operated, the NMOS transistor NM1 is turned off to disconnect the connection between the internal power detector 11 and the pad 10.

Here, in order to prevent the NMOS transistor from being turned on when a negative voltage is applied to the pad 10, the NMOS transistor NM2 has a potential difference between the node A and the pad 10. Adjust so that it becomes below the threshold voltage Vt of NM1).

Subsequently, the above operation is repeated one more time to evaluate the state of the device secondly. In the first evaluation, the device that has received the defective article is disconnected from the fuse F1 connected to the internal power detector 11 to evaluate the second time. Exclude from.

In conclusion, the fuse F1 connecting the specific pad 10 and the internal power supply detection unit 11 is cut at the first evaluation of the device, and the classification of the defective product and the defective product is detected initially. Shorten the evaluation time.

As described in detail above, the present invention has the effect of improving the productivity of the product by reducing the unnecessary time by quickly determining the determination of the defective product in the wafer state compared to other good products.

Claims (2)

A second NMOS transistor having a gate connected to an internal power supply detection part at one side thereof to a drain of a first NMOS transistor having a pad connected to a source, and having a gate and a source commonly connected to the connection point. A drain is connected, a test power is applied to a common connection point of the gate of the first NMOS transistor and the source of the second NMOS transistor, and a ground voltage is applied to the gate of the second NMOS transistor. A peripheral circuit of a semiconductor device. The peripheral circuit of a semiconductor device according to claim 1, wherein the fuse is cut when the device is defective in the first evaluation, and the evaluation time is shortened by excluding the defective device from the evaluation object in the second evaluation.

Images