KR100252636B1 - 8x8 block address generating circuit for jpeg coding - Google Patents

Abstract

PURPOSE: An 8x8 block address generating circuit of a JPEG image compression is provided to economize the cost, to improve a data transmission speed, and to reduce a system size by transmitting an image data stored in a frame memory to an image compression chip. CONSTITUTION: A 13 bit horizontal counter(21) receives an A/D sampling clock and provides a horizontal address in units of the 8x8 block in order to read only valid data in a frame memory having a size of 1024x512. A 6 bit vertical counter(22) provides a vertical address in units of 8x8 block. A 2 input AND gate(G1) receives outputs(H11,H12) of 13 bit horizontal counter(21) and provides a clock signal of the 6 bit vertical counter(22) and a clear signal of 13 bit horizontal counter(21). A 4 input AND gate(G2) receives outputs(V2,V3,V4,V5) of the 6 bit vertical counter(22) and provides a clear signal of the 6 bit vertical counter(22).

Description

J. P. rat. 8 × 8 Block Address Generation Circuit for Image Compression

1 is a prior art circuit diagram of a pixel interface for reading data using a line buffer in a JPEG compression chip,

2 is a circuit diagram of an 8 x 8 block address generator that reads data from a JPEG compression chip without a line buffer, according to an embodiment of the present invention.

3 is a block diagram of a block address generator and a peripheral circuit according to an embodiment of the present invention.

4 is a diagram showing a method of generating data by generating an 8x8 block address.

* Explanation of symbols for main parts of the drawings

21: 13-bit horizontal counter section 22: 6-bit vertical counter section

The present invention relates to an 8 × 8 block address generation circuit for JPEG (Joint Photographic Experts Group) image compression. More specifically, the JPEG image compression chip does not use line buffers to store image data stored in frame memory as in the prior art. The present invention relates to an 8x8 address generation circuit composed of a 13-bit horizontal counter section and a 6-bit vertical counter section for direct reading by 8x8 blocks.

JPEG image compression chip performs compression by reading 8 × 8 blocks of image data stored in memory. For this purpose, an address generating circuit capable of generating an address at 8x8 is required.

In the present invention, an 8x8 address is generated for a 768x480 image data by using a 13-bit horizontal counter and a 6-bit vertical counter.

Hereinafter, a pixel interface circuit for reading data using a line buffer in a conventional JPEG compression chip will be described with reference to the accompanying drawings.

1 is a prior art circuit diagram of a pixel interface for reading data using a line buffer in a JPEG compression chip.

As shown in FIG. 1, the conventional technique stores 768x480 image data in a 1024x512 frame memory 13, and then uses 8x8 blocks to read data into the compression chip 11. When performing addressing, a line buffer 12 is generally placed at the input of the compression chip 11 so as to be directly addressed from the compression chip 11. The size of the line buffer 12 is usually SRAM (SRAM) having a size of (pixels per line x 8).

However, the above-described conventional technique requires adding an SRAM to be used as a line buffer in addition to the frame memory to generate an address using the line buffer, so that the overhead of not only increasing the overall system but also increasing the cost thereof is increased. The disadvantage is that it occurs.

Accordingly, an object of the present invention is to solve the above-mentioned disadvantages, and includes a 13-bit horizontal counter unit (designed with an ASIC) so that data can be read directly from the frame memory without using a line buffer. The present invention provides an 8x8 block address generation circuit composed of a 6-bit vertical counter unit (designed by ASIC).

As a means for achieving the above object, the configuration of the present invention,

A 13-bit horizontal counter unit for providing a horizontal address in 8x8 block units to read only valid data (768x480) from a frame memory having a size of 1024x512,

A 6-bit vertical counter unit providing a vertical counter unit in units of 8 blocks;

2 input and gates for providing a clear signal to the 13-bit horizontal counter and a counting clock signal to the 6-bit vertical counter;

It consists of four input and gates that provide a clear signal to a six-bit vertical counter.

With the above configuration, the most preferred embodiment which can be easily carried out by those skilled in the art with reference to the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of an 8x8 block address generator that allows data to be read without a line buffer from a JPEG compression chip according to an embodiment of the present invention.

As shown in FIG. 2, the configuration according to the embodiment of the present invention is

A 13-bit horizontal counter unit 21 for providing a horizontal address in 8x8 block units to read only valid data (768x480) from a frame memory having a size of 1024x512,

A 6-bit vertical counter unit 22 for providing a vertical address in units of 8x8 blocks,

It receives the outputs H11 and H12 of the 13-bit horizontal counter section 21, provides a clock (CLK) signal of the 6-bit vertical counter section 22, and provides a clear (CLR) signal of the 13-bit horizontal counter section 21. Two input and gate G1 provided,

A 4-input end gate G2 receives the outputs V2, V3, V4, V5 of the 6-bit vertical counter section 22 and provides a clear (CLR) signal of the 6-bit vertical counter section 22.

A18-A0 is a frame memory address.

With the above configuration, the operation according to the embodiment of the present invention is as follows.

To generate an 8x8 block address, data must be read in the same manner as in FIG.

One block is composed of 8x8, or 64 pixels.

In order to generate an address in the same manner as in FIG. 4, a 13-bit horizontal counter 21 and a 6-bit vertical counter 22 are used to connect the output to each address line as follows.

t1

By using this connection, the address for the first 8x8 block is generated by the outputs H0, H1, and H2 of the 13-bit horizontal counter unit 21. The next address is 1024 (400H), where H3 of the 13-bit horizontal counter portion 21 is connected to A10. This address becomes the address of the first pixel of the second vertical line, and if an address is generated for eight data of the second line in the same way, the next address jumps to the first pixel of the third line (address 800H). To generate the address for the first 8x8 block.

In more detail,

The 13-bit horizontal counter unit 21 receives an A / D sampling clock, which is used to sample analog image data into digital 8-bit data at the front of the frame memory, as a counting clock (CLK) signal. It operates as a counter addressing data as much as 768 x 8 by 96 addressing. The 6-bit vertical counter section 22 receives the counting clock CLK from the two input and gate G1 and 768 x in the vertical direction. It operates as a counter that assigns data as much as 768 × 480 size by addressing 60 times in 8 units, and the 2 input and gate (G1) is finished addressing the 768th pixel of the 8th line (the general address is 1EFFH to 1F00H). The 13-bit horizontal counter output H12-H0 changes from 17FFH to 1800H.) Since the address (2000H) for the first pixel of the ninth line must be generated, the 13-bit horizontal counter output The two bits H11 and H12 of (21) are ANDed, and their output is used as a counting clock (CLK) signal of the 6-bit vertical counter section 22 (V0 = A13 = 1), and at the same time, the 13-bit horizontal counter section 21 (H0 to H12 = A0 to A12 = 0), and the 4 input end gate (G2) reads data 8 blocks in the vertical direction and then changes from vertical line 480 to 481. Since the V5-V0 value changes from 3BH to 3CH, the upper 4 bits of the 6-bit vertical counter unit 22 output V2-V5 are ANDed to designate the first line, and the output is cleared by the 6-bit vertical counter 22 ( It operates to use as CLR) signal (V0 ~ V5 = A13 ~ A18 = 0).

As a result, the counters are all cleared to address the first pixel of the first line again, repeating for 768 x 480 new data in this way and passing the image data in the frame memory directly to the image compression chip.

3 is a block diagram of an 8x8 block address generation circuit and its peripheral circuits in accordance with an embodiment of the present invention.

As shown in Figure 3,

The JPEG compression / restoration system receives the video signal from the video source 31 by the command of the host CPU 37, converts it to A / D 32, and stores it in the frame memory 33, and compresses / restores the chip ( 34) is a device that compresses the image data stored in the frame memory 33, stores the result in a recording medium 35, such as a hard disk of a computer, and restores it again to output the image to a display device. Here, the 8x8 block address generation circuit 36 is used to read data stored in the frame memory 33 into the compression / restore chip 34.

As described above, in the embodiment of the present invention,

In all image compression / restore systems that read image data stored in frame memory in 8 × 8 block units, image data is transferred directly from frame memory to image compression chip without line buffer, saving cost, improving data transfer speed and system size. It is possible to provide an 8x8 block address generation circuit for JPEG image compression with the effect of reducing the number of pixels.

This effect of the invention

It can be used in the field of digital still camera (Digital Still Camera), image compression / restorer and the like.

Claims (5)

A 13-bit horizontal counter unit for providing a horizontal address in 8x8 block units to read only valid data (768x480) from a frame memory having a size of 1024x512, A 6-bit vertical counter that provides a vertical address in 768 x 8 blocks, A two-input end gate G1 that receives the outputs H11 and H12 of the 13-bit horizontal counter part and provides a clock (CLK) signal of the 6-bit vertical counter part and provides a clear (CLR) signal of the 13-bit horizontal counter part; 8 × for JPEG image compression, characterized in that it consists of four input and gate (G2) receiving the outputs V2, V3, V4, V5 of the 6-bit vertical counter and providing a clear (CLR) signal of the 6-bit vertical counter. 8 block address generation circuit. The method of claim 1, The 13-bit horizontal counter unit receives an A / D sampling clock, which is used to sample analog image data into digital 8-bit data at the front end of the frame memory, as a counting clock (CLK) signal, in units of 8 × 8 blocks in the horizontal direction. An 8x8 block address generation circuit for JPEG image compression, comprising: a counter for addressing 96 times and specifying data as large as 768x8. The method of claim 1, The 6-bit vertical counter unit comprises a counter that receives the counting clock CLK from the two input and gate G1 and addresses 60 times in units of 768 × 8 in the vertical direction to designate data as large as 768 × 480. An 8x8 block address generation circuit for JPEG image compression. The method of claim 1, The two input and gate gates G1, H11, H12 of the 13-bit horizontal counter part are generated so that when the addressing for the 768th pixel of the eighth line of each block is completed, the next address is generated for the first pixel of the next block. AND the two bits and use the output as the counting clock (CLK) signal of the 6-bit vertical counter, and simultaneously use the clear (CLR) signal of the 13-bit horizontal counter (H0 to H12 = A12 = 0). 8x8 block address generation circuit for JPEG image compression. The method of claim 1, The four input end gate G2 reads data 8 blocks in the vertical direction and changes the V5-V0 value from 3BH to 3CH when the data is changed from the vertical line 480 to 481. The high-order 4 bit V2-V5 of the vertical counter output is ANDed, and the output is used as a clear (CLR) signal of the 6-bit vertical counter (V0 to V5 = A13 to A18 = 0). 8 x 8 block address generation circuit.