KR100248987B1 - Manufacturing method of tma - Google Patents

Abstract

A method of manufacturing a thin film type optical path control device capable of preventing diffusion of silicon atoms from inside an active matrix is disclosed. The method includes providing an active matrix with M × N (M, N is an integer) transistors, iii) forming a first diffusion barrier on top of the active matrix, ii) a top of the first diffusion barrier Forming a second diffusion barrier in the second diffusion barrier, and iii) forming a drain pad on the second diffusion barrier, and a support layer on the active matrix and the first metal layer. And forming an actuator having a lower electrode, a strain layer, an upper electrode, and a via contact connecting the lower electrode and the drain pad. According to the above method, the diffusion barrier is formed of a double layer of a first diffusion barrier formed of titanium nitride enriched with titanium and a second diffusion barrier formed of conventional titanium nitride, without separately forming an adhesion layer. Adhesion between the active matrix and the drain pad can be improved, and diffusion of silicon atoms from the inside of the active matrix can be prevented even at a high temperature process, so that the first signal applied from the outside is sufficiently transmitted to the lower electrode, thereby improving device performance. You can.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing AMA (Actuated Mirror Arrays), which is a thin film type optical path control device, and more particularly, a thin film type optical path that can improve the performance of a device by preventing diffusion of silicon atoms from inside an active matrix in a high temperature process. It relates to a manufacturing method of the adjusting device.

An optical path adjusting device or an optical modulator capable of adjusting the light flux may be variously applied to optical communication, image processing, and information display apparatus. In general, such devices are classified into two types according to their optical properties. One type is a direct view type image display device, such as a Cathode Ray Tube (CRT). Another type is a projection type image display device such as a liquid crystal display (LCD).

The liquid crystal display device has an advantage in that the optical structure is simple. However, the liquid crystal display has a disadvantage in that the light efficiency is lowered due to the polarized light and the response speed is slow. Therefore, in order to solve the above problem, a projection type image display device such as AMA or DMD (Deformable Mirror Device) has been developed.

The AMA device is a device capable of adjusting the luminous flux so that each mirror installed therein reflects the light flowing from the light source at a predetermined angle, and the reflected light passes through a slit to form an image on the screen. to be. Therefore, the AMA device has a simple structure and operation principle, and can achieve high light efficiency compared to a liquid crystal display device. In addition, the contrast is improved to obtain a bright and clear image.

Such AMA devices are classified into bulk type optical path control devices and thin film type optical path control devices. The bulk optical path control device is disclosed in, for example, US Pat. No. 5,085,497 (issued to Gregory Um, et al.) 5,159,225 (issued to Gregory Um), 5,175,465 (issued to Gregory Um, et al. have. In the bulk optical path control apparatus, a multilayer ceramic is thinly cut, a ceramic wafer having a metal electrode formed therein is mounted on an active matrix in which a transistor is built, and then processed by sawing or the like. It is done by installing 3 mirrors on the top. However, the bulk AMA device requires a long process time because the actuators must be separated by a sawing method or the like, and the response speed of the deformable part is slow. Therefore, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed.

Such a thin film type optical path control device is disclosed in Korean Patent Application No. 96-25324 (name of the invention: a method of manufacturing a reflective optical path control device) filed by the applicant of the Korean Patent Office on June 28, 1996.

FIG. 1 shows a plan view of the thin film type optical path adjusting device described in the above prior application, and FIG. 2 shows a cross-sectional view taken along the line AA ′ of the device shown in FIG. 1.

As shown in FIGS. 1 and 2, the thin film type optical path adjusting device is formed on an active matrix 1 and an active matrix 1 having M × N (M, N is an integer) MOS transistors embedded therein. Actuator 70 is included.

The active matrix 1 may include an diffusion layer 5 formed on the active matrix 1, a diffusion barrier 10 formed on the diffusion barrier 5, and a blocking layer 10. Drain pad 20 formed on one side of the upper side, the protective layer 15 formed on the portion of the blocking layer 10 except the portion where the drain pad 20 is formed, and the top and the drain of the protective layer 15 The etch stop layer 25 is formed on the pad 20.

The actuator 70 includes a membrane 35, a lower electrode 40 formed on the membrane 35, a deformable portion 45 formed on the lower electrode 40, a deformable portion 45, and a lower electrode 40. ), A via contact 60 formed vertically to the drain pad 20 through the membrane 35 and the etch stop layer 25, and an upper electrode 50 formed on the deformable portion 45. A stripe 55 is formed at one side of the upper electrode 50 to expose a portion of the deformable portion 45.

The membrane 35 has a cross section formed at one side thereof in contact with the etch stop layer 25 having a drain pad 20 formed thereon, and the other side thereof being parallel to the etch stop layer 25 via an air gap 30. . In addition, referring to FIG. 1, one side plane of the membrane 35 has a rectangular concave portion at a central portion thereof, and the rectangular concave portion has a shape widening stepwise toward both edges. The other plane of the membrane 35 has a protrusion that narrows stepwise to correspond to the stepped concave portion of the membrane of the adjacent actuator. Therefore, the protrusion of the membrane 35 is formed by fitting into the concave portion of the adjacent membrane, and the protrusion of the membrane adjacent to the concave portion of the membrane 35 is formed.

3A to 3E show a manufacturing process diagram of the thin film type optical path control device. 3A to 3E, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 3A, a diffusion barrier layer 5 is formed on an active matrix 1 made of silicon and having M × N transistors (not shown) embedded therein. The diffusion barrier layer 5 is formed to have a thickness of about 300 to 500 kPa by using a sputtering method of titanium (Ti). The diffusion barrier layer 5 prevents the silicon in the active matrix 1 from diffusing upward under the influence of subsequent processes.

The blocking layer 10 is formed on the diffusion barrier layer 5. The blocking layer 10 is formed of titanium nitride (TiN) to have a thickness of about 1200 to 1500 kPa using a Low Pressure Chemical Vapor Deposition (LPCVD) method or a sputtering method. Subsequently, the deposited titanium nitride is heat-treated at a temperature of 800 to 900 ° C., preferably 850 ° C. for 5 to 10 minutes, and preferably 10 minutes to convert delta-titanium nitride (δ-TiN) into cubic titanium nitride. Phase change to). Since the blocking layer 10 is incident on not only the upper electrode 50 of which the light flux incident from the light source is the reflective layer but also a portion other than the portion where the upper electrode 50 is formed, the photocurrent is applied to the active matrix 1. To prevent it from flowing.

Referring to FIG. 3B, a protective layer 15 is formed on the blocking layer 10 to protect the active matrix 1 in which the transistor is embedded. The protective layer 15 is formed of Phosphor-Silicate Glass (PSG) to have a thickness of about 1.0 μm using a chemical vapor deposition (CVD) method. Subsequently, a part of the protective layer 15 is etched to expose a part of the blocking layer 10, and then a drain pad 20 is formed by using a lift-off method of a metal such as tungsten (W). The drain pad 20 transmits a first signal (image signal) applied from the outside to the lower electrode 40 through the transistor and via contact 60 embedded in the active matrix 1.

An etch stop layer 25 is formed on the passivation layer 15 and the drain pad 20. The etch stop layer 25 is formed to have a thickness of about 2000 kPa using a low pressure chemical vapor deposition method (LPCVD). The etch stop layer 25 prevents the active matrix 1 and the protective layer 15 from being etched and damaged during the subsequent etching process. Subsequently, a sacrificial layer 28 is formed on the etch stop layer 25. The sacrificial layer 28 is formed of phosphorous silicate (PSG) to have a thickness of about 1 μm using an Atmospheric Pressure CVD (APCVD) method. At this time, since the sacrificial layer 28 covers the surface of the active matrix 1 in which the transistor is embedded, the surface flatness is very poor. Therefore, the surface of the sacrificial layer 28 is planarized using a chemical mechanical polishing (CMP) method or a method using spin on glass (SOG). In addition, a portion of the sacrificial layer 28 in which the drain pad 20 is formed is patterned to expose a portion of the etch stop layer 25.

Referring to FIG. 3C, the nitride layer 35 is formed on the exposed etch stop layer 25 and on the sacrificial layer 28. The membrane 35 is formed to have a thickness of about 1.0 to 2.0 µm using a low pressure chemical vapor deposition (LPCVD) method. Subsequently, a lower electrode 40 is formed on the membrane 35 so as to have a thickness of about 500 to 2000 micrometers by sputtering a metal such as platinum (Pt) or tantalum (Ta). Subsequently, Iso-Cutting is performed to separate the lower electrode 40 for each pixel.

Referring to FIG. 3D, the deformation part 45 is formed on the lower electrode 40. The deformable portion 45 is formed to have a thickness of about 1.0 to 2.0 µm using piezoelectric materials such as PZT or PLZT. The deformable portion 45 is formed by using a sol-gel method, and then thermally deformed by rapid thermal annealing (RTA). The upper electrode 50 is formed on the deformation part 45. The upper electrode 50 is formed of a metal having excellent electrical conductivity and reflectivity, such as aluminum or platinum, to have a thickness of about 500 to 2000 kPa using a sputtering method. Since the upper electrode 50 made of aluminum or platinum has excellent electrical conductivity and reflectivity, the upper electrode 50 performs not only a function of a bias electrode but also a function of a reflective layer reflecting an incident light beam.

The upper electrode 50 is patterned to have a predetermined pixel shape. In this case, the stripe 55 is formed on one side of the upper electrode 50. The stripe 55 operates the upper electrode 50 uniformly to prevent diffuse reflection of the light beam incident from the light source.

Referring to FIG. 3E, the deformable portion 45 and the lower electrode 40 are patterned into a predetermined pixel shape like the upper electrode 50. Subsequently, the deformable portion 45, the lower electrode 40, the membrane 35, the etch stop layer 25, and the protective layer 15 are sequentially etched from one side of the deformable portion 45 to the drain pad 20. The via contact 60 is then formed using a lift-off method of a metal such as tungsten or titanium. Thus, the via contact 60 is vertically formed from the upper side of one side of the deformable portion 45 to the drain pad 20 to electrically connect the drain pad 20 and the lower electrode 40. Subsequently, the membrane 35 is patterned into a predetermined pixel shape, and then the sacrificial layer 28 is etched away using hydrogen fluoride (HF) vapor, and then washed and dried to complete an AMA device.

In the above-described thin film type optical path adjusting device, the first signal (image signal) applied from the outside is applied to the lower electrode through the transistor, the drain pad, and the via contact embedded in the active matrix. At the same time, a second signal (bias signal) is applied to the upper electrode to generate an electric field between the upper electrode and the lower electrode. The deformed portion formed between the upper electrode and the lower electrode causes deformation by this electric field. At this time, since the deformable portion contracts in a direction perpendicular to the generated electric field, the actuator including the deformable layer is bent at a predetermined angle. The upper electrode, which also functions as a mirror that reflects the light beam, is formed on the actuator and is inclined together with the actuator. Accordingly, the upper electrode reflects the light beam incident from the light source at a predetermined angle, and the reflected light beam passes through the slit to form an image on the screen.

In the thin film type optical path adjusting device described in the above application, the adhesion layer composed of titanium (Ti) performs a function of enhancing the adhesion between the diffusion barrier and the active matrix. However, the adhesion layer reacts with the silicon of the active matrix under the influence of a subsequent high temperature process to form a titanium silicide (TiSi ₂ ) compound. The non-uniform titanium silicide compound thus formed serves to promote the rapid movement of silicon atoms in the active matrix to the drain pad stacked thereon. The transferred silicon atoms form tungsten silicide (WSi ₂ ) at the interface of the drain pad. When tungsten silicide is formed at the interface of the drain pad, the first signal applied from the outside is not sufficiently transmitted to the lower electrode, and thus there is a problem that the AMA device may not operate or may malfunction.

Accordingly, an object of the present invention is to provide a method for manufacturing a thin film type optical path control device that can improve the performance of the device by accurately transmitting the first signal to the lower electrode by minimizing the diffusion of silicon atoms from the inside of the active matrix to the drain pad even in a high temperature process. To provide.

1 is a plan view of a thin film type optical path adjusting device described in the applicant's prior application.

FIG. 2 is a cross-sectional view taken along line A′A ′ of the apparatus shown in FIG. 1.

3A to 3E are manufacturing process diagrams of the apparatus shown in FIG.

4 is a plan view of a thin film type optical path control apparatus according to the present invention.

FIG. 5 is a cross-sectional view taken along line B′B ′ of the apparatus shown in FIG. 4.

FIG. 6 is an enlarged cross-sectional view of part 'A' of the apparatus shown in FIG. 5.

7A to 7E are manufacturing process diagrams of the apparatus shown in FIG.

8A to 8D show leakage currents in the upper gate, lower gate, left and right source portions in the thin film type optical path adjusting device described in the applicant's prior application.

9A to 9D illustrate leakage currents in a gate upper portion, a gate lower portion, a left source, and a right source portion in the thin film type optical path adjusting device according to the present invention.

<Description of the code | symbol about the principal part of drawing>

100: active matrix 105a: first diffusion barrier

105b: second diffusion barrier 105: diffusion barrier

110: drain pad 115: stress balance layer

120: first metal layer 125: first protective layer

130: second metal layer 135: second protective layer

140: etch stop layer 145: sacrificial layer

150 support layer 155 lower electrode

160 strain layer 165 upper electrode

170: beer hall 175: beer contact

180: stripe 185: air gap

200: actuator

In order to achieve the above object, the present invention provides a step of providing an active matrix containing M × N (M, N is an integer) transistor, iii) forming a first diffusion barrier on top of the active matrix, ii) Forming a second diffusion barrier over the first diffusion barrier, and iii) forming a drain pad over the second diffusion barrier, and forming the active matrix and the first matrix. Forming a support layer on top of the metal layer, forming a lower electrode on top of the support layer, forming a strain layer on top of the lower electrode, forming an upper electrode on top of the strain layer and the bottom And forming an actuator having a via contact connecting the electrode and the drain pad. To provide a method of manufacturing the control device.

In the thin film type optical path adjusting device according to the present invention, the first signal applied from the outside is applied to the lower electrode through the transistor, the drain pad, and the via contact embedded in the active matrix. In addition, a second signal is applied to the upper electrode to generate an electric field between the upper electrode and the lower electrode. Due to this electric field, the strain layer formed between the upper electrode and the lower electrode causes deformation. The strained layer contracts in a direction perpendicular to the electric field, and the actuator including the strained layer is bent upward at a predetermined angle. As a result, the upper electrode on the actuator is also inclined at the same angle. Since the upper electrode also functions as a mirror that reflects the luminous flux, the luminous flux incident from the light source is reflected by the inclined upper electrode at a predetermined angle, and is then projected onto a screen to form an image.

Therefore, according to the manufacturing method of the thin film type optical path control apparatus according to the present invention, by forming a first diffusion barrier using titanium nitride rich in titanium instead of the adhesion layer formed using titanium, without separately preparing an adhesion layer In addition, adhesion between the active matrix and the second diffusion barrier may be improved, and the formation of titanium silicide that is thermally formed by a subsequent high temperature process to promote diffusion of silicon may be suppressed. Therefore, the diffusion of silicon atoms from the inside of the active matrix can be minimized so that the first signal applied from the outside can be accurately delivered to the lower electrode, thereby improving the performance of the device. In addition, by forming a diffusion barrier as a double layer of a first diffusion barrier and a second diffusion barrier, even if a small amount of silicon atoms are diffused through the first diffusion barrier, the second diffusion barrier blocks the double, thereby preventing the diffusion of silicon atoms more efficiently. can do.

Hereinafter, a method of manufacturing a thin film type optical path control device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view showing a thin film type optical path control device according to the present invention, Figure 5 is a cross-sectional view taken along the line BB 'of the device shown in Figure 4, Figure 6' An enlarged cross-sectional view of part A 'is shown.

4 and 6, the thin film type optical path control apparatus according to the present invention includes an active matrix 100 and an actuator 200 formed on the active matrix.

The active matrix 100 may include a first metal layer 120 formed on the active matrix 100, a first passivation layer 125 formed on the first metal layer 120, and a first passivation layer. The second metal layer 130 formed on the layer 125, the second passivation layer 135 formed on the second metal layer 130, and the etch stop layer 140 formed on the second passivation layer 135. It includes.

Referring to FIG. 6, the first metal layer 120 includes a diffusion barrier including a first diffusion barrier 105a stacked on the active matrix 100 and a second diffusion barrier 105b formed on the first diffusion barrier. 105, a drain pad 110 formed on the diffusion barrier 105, and a stress balance layer 115 stacked on the drain pad 110.

Referring back to FIG. 5, the actuator 200 has one side in contact with a portion of the etch stop layer 140 in which the drain pad 110 is formed and the other side has an etch stop layer 140 through an air gap 185. Supporting layer (150) having a cross-section formed in parallel with the lower electrode 155 stacked on top of the support layer 150, the strained layer 160 stacked on the lower electrode 155, the strained layer ( The strained layer 160, the lower electrode 155, the support layer 150, the etch stop layer 140, and the second passivation layer 135 from one side of the upper electrode 165 and the strained layer 160 stacked on the upper portion 160. ) And a via contact 175 formed in the via hole 170 vertically formed through the first passivation layer 125 to the drain pad 110. On one side of the upper electrode 165, a stripe 180 for uniformly operating the upper electrode 165 is formed.

In addition, referring to FIG. 4, one side plane of the support layer 150 has a concave portion having a rectangular shape at the center thereof, and the concave portion is formed in a stepped shape toward both edges. The other plane of the support layer 150 has a rectangular protrusion that narrows in a stepped manner toward the center portion corresponding to the concave portion. Therefore, the convex portion of the support layer of the actuator adjacent to the concave portion of the support layer 150 is fitted, and the rectangular projection is fitted to the concave portion of the support layer of the adjacent actuator. The support layer 150 of the present invention performs the function of the membrane 35 described in the preceding application.

Hereinafter, a method of manufacturing a thin film type optical path control device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

7A to 7E show a manufacturing process diagram of the apparatus shown in FIG. 7A to 7D, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 7A, first, a first diffusion barrier 105a is formed on an active matrix 100 including M × N MOS transistors (not shown). The active matrix 100 is made of a semiconductor such as silicon or an insulating material such as glass or alumina (Al ₂ O ₃ ). The first diffusion barrier 105a is formed by stacking titanium nitride (Tirich TiN), which is rich in titanium, to have a thickness of about 300 to 500 kW using a sputtering method. The first diffusion barrier 105a improves adhesion between the active matrix 100 and the second diffusion barrier 105b subsequently formed. In the related art, in order to improve adhesion between the diffusion barrier and the active matrix 100, an diffusion layer composed of titanium is stacked on the active matrix 100. However, the titanium of the diffusion barrier layer is bonded to the silicon atoms of the active matrix 100 in a subsequent high temperature process to form a titanium silicide (TiSi ₂ ) compound, which serves to promote the diffusion of silicon atoms in the drain pad direction. Was performed. In contrast, in the present invention, instead of forming a diffusion barrier layer, by stacking a first diffusion barrier 105a composed of titanium nitride, which is rich in titanium, the adhesion to the active matrix 100 can be increased, and subsequent high temperature can be achieved. The diffusion of silicon atoms in the process can be prevented.

A second diffusion barrier 105b is formed on the first diffusion barrier 105a. The second diffusion barrier 105b is formed such that titanium nitride (TiN) has a thickness of about 500 to 700 GPa using a physical vapor deposition (PVD) method. Subsequently, the second diffusion barrier 105b is heat-treated at a temperature of 800 to 900 ° C., preferably 850 ° C. for 5 to 10 minutes, preferably 10 minutes to form delta-titanium nitride (δTiN) as cubic titanium nitride (cubic). Phase transition to TiN). The second diffusion barrier 105b prevents silicon atoms from diffusing into the drain pad 110 from inside the active matrix 100. In general, when the second diffusion barrier 105b is formed by the sputtering method, the (1, 0, 0) plane is predominantly formed in the crystal direction of the titanium nitride constituting the diffusion barrier with respect to the horizontal plane of the active matrix. Since the (1, 0, 0) plane of the titanium nitride is weak against horizontal expansion, micro cracks are generated in the second diffusion barrier 105b due to the subsequent process, so that silicon atoms in the active matrix 100 Easily diffuses through microcracks. Therefore, by forming titanium nitride by physical vapor deposition and heat-treating the phase transition, the crystal direction of titanium nitride is formed horizontally with respect to the active matrix 100 so that the (1, 1, 1) plane predominates. Since the (1, 1, 1) plane has the highest atomic density among the crystal directions of titanium nitride, the smallest cracks are generated with respect to the expansion in the horizontal direction, thereby effectively preventing the diffusion of silicon.

A drain pad 110 is formed on the second diffusion barrier 105b. The drain pad 110 is laminated with tungsten (W) to have a thickness of about 4000 kW using a sputtering method. The first signal applied from the outside is applied to the lower electrode 155 through the transistor embedded in the active matrix 100, the drain pad 110, and the via contact 175 formed subsequently. Subsequently, the first metal layer 120 is formed by stacking the stress balance layer 115 on the drain pad 110. The stress balance layer 115 is formed to have a thickness of about 500 ~ 700Å by using titanium nitride. The stress balance layer 115 serves to alleviate the stress received by the thin films stacked below in a high temperature process to protect them.

Referring to FIG. 7B, the first protective layer 125 is formed on the stress balance layer 115 to protect the active matrix 100 having the transistor embedded therein. The first passivation layer 125 is formed to have a thickness of about 8000 Å by using a chemical vapor deposition (CVD) method of the silicate glass (PSG).

The second metal layer 130 is stacked on the first passivation layer 125. In order to form the second metal layer 130, first, the first layer is laminated to a thickness of about 300 μs using titanium by sputtering. Subsequently, a second layer of titanium nitride is deposited on the first layer to have a thickness of about 1200 kW using physical vapor deposition (PVD). Since the second metal layer 130 is incident on not only the upper electrode 165 where the luminous flux incident from the light source is the reflective layer but also a portion other than the portion where the upper electrode 165 is formed, the second metal layer 130 has a photo current in the active matrix 100. To prevent it from flowing. Subsequently, a portion of the second metal layer 130 in which the via contact 175 is to be formed in a subsequent process is etched and patterned to form a hole in the second metal layer 130, thereby forming a hole in the first protective layer 125. Expose some.

The second passivation layer 135 is stacked on the exposed first passivation layer 125 and the second metal layer 130. The second protective layer 135 is laminated with a silicate glass (PSG) to a thickness of about 2000 kPa using a chemical vapor deposition method. The second protective layer 135 also prevents the transistor embedded in the active matrix 100 from being damaged during subsequent processing. An etch stop layer 140 is stacked on the second passivation layer 135. The etch stop layer 140 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 140 prevents the active matrix 100 and the second passivation layer 135 from being etched during the subsequent etching process.

A sacrificial layer 145 is stacked on the etch stop layer 140. The sacrificial layer 145 is formed of a silicate glass (PSG) to have a thickness of about 2.0 to 3.2 μm by the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 145 covers the top of the active matrix 100 in which the transistor is embedded, the flatness of the surface thereof is very poor. Accordingly, the surface of the sacrificial layer 145 is planarized by polishing the top of the sacrificial layer 145 to have a thickness of about 1. 6 μm by using a spin on glass (SOG) method or a CMP method. Subsequently, a portion of the sacrificial layer 145 where the hole of the second metal layer 130 is formed is patterned in consideration of the position where the support portion of the actuator 200 is to be formed to expose a portion of the etch stop layer 140.

Referring to FIG. 7C, the third layer 149 is stacked on the exposed etch stop layer 140 and on the sacrificial layer 145. The third layer 149 is formed to have a thickness of about 1000 to 3000 GPa using a low pressure chemical vapor deposition (LPCVD) method. The third layer 149 is later patterned into the support layer 150. Subsequently, a lower electrode layer 154 is stacked on the third layer 149. The lower electrode layer 154 is formed to have a thickness of about 2000 to 4000 micrometers using a sputtering method of a metal having electrical conductivity such as platinum, tantalum (Ta), or platinum-tantalum (Pt-Ta). In addition, in order to separate the lower electrode layer 154 for each pixel, Iso-cutting is performed in parallel with the direction in which the actuator 200 is formed. The lower electrode layer 154 is later patterned into the lower electrode 155.

A fourth layer 159 made of a piezoelectric material such as PZT or PLZT is stacked on the lower electrode layer 154. The fourth layer 159 is formed to have a thickness of 4000 to 6000 kPa, preferably about 4000 kPa using a sol-gel method, sputtering method, or chemical vapor deposition method. In addition, the fourth layer 159 is heat-treated by rapid thermal annealing (RTA) to phase change, and then the piezoelectric material constituting the fourth layer 159 is polarized. The fourth layer 159 is later patterned with the strained layer 160 to cause strain by an electric field generated between the upper electrode 165 and the lower electrode 155.

The upper electrode layer 164 is stacked on the fourth layer 159. The upper electrode layer 164 is formed of a metal having electrical conductivity and reflectivity such as aluminum, silver, or platinum so as to have a thickness of about 2000 to 6000 kW using a sputtering method. Subsequently, the upper electrode layer 164 is patterned to form an upper electrode 165 having a predetermined pixel shape. In this case, a stripe 180 is formed on one side of the upper electrode 165 to uniformly operate the upper electrode 165 to prevent diffuse reflection of light beams incident from a light source (not shown). The second signal is applied to the upper electrode 165 from a common electrode line (not shown). Therefore, when the first signal is applied to the lower electrode 155 and the second signal is applied to the upper electrode 165, an electric field is generated between the upper electrode 165 and the lower electrode 155. This deformation causes the deformation layer 160 to deform. Since the upper electrode 165 has excellent electrical conductivity and reflectivity, the upper electrode 165 performs not only a function of a bias electrode but also a mirror reflecting an incident light beam.

Referring to FIG. 7D, the fourth layer 159 and the lower electrode layer 154 are sequentially patterned to form a strained layer 160 and a lower electrode 155 having predetermined pixel shapes, respectively. In this case, the strained layer 160 has a slightly larger area than the upper electrode 165, and the lower electrode 155 has a slightly larger area than the strained layer 160. Subsequently, the strained layer 160, the lower electrode 155, the third layer 149, and the etch stop layer 140 are formed from an upper portion of the strained layer 160 where holes of the second metal layer 130 are formed below. ), The second passivation layer 135, and the first passivation layer 125 are sequentially etched to form the via hole 170 to the drain pad 110 of the first metal layer 120, and then the via hole ( The via contact 175 is formed in the inside of the 170 by using a sputtering method of an electrically conductive metal such as tungsten, aluminum, or titanium. The via contact 175 electrically connects the drain pad 110 and the lower electrode 155. Therefore, the first signal applied from the outside is applied to the lower electrode 155 through the transistor, the drain pad 110, and the via contact 175 embedded in the active matrix 100. Subsequently, the third layer 149 is patterned to form a support layer 150 having a pixel shape slightly larger than that of the lower electrode 155.

Referring to FIG. 7E, the sacrificial layer 145 is etched using hydrogen fluoride (HF) vapor to form an air gap 185 at the position of the sacrificial layer 145, followed by cleaning and drying. Complete the AMA device.

After completing the M × N thin film type AMA devices as described above, the active matrix 100 is formed by sputtering or evaporation of metals such as chromium (Cr), nickel (Ni), and gold (Au). It is deposited at the bottom of the to form an ohmic contact (not shown). In addition, in preparation for bonding (Tape Carrier Package) (not shown) bonding for applying a second signal to the upper electrode 165 which is a subsequent common electrode and the first signal to the lower electrode 155. The active matrix 100 is cut to a predetermined thickness using a conventional photolithography method. Subsequently, a photoresist layer (not shown) is formed over the pad of the AMA panel so that the pad of the AMA panel (not shown) has a sufficient height in preparation for TCP bonding. Subsequently, a portion of the photoresist layer on which the pad is formed is patterned to expose the pad of the AMA panel. Subsequently, the photoresist layer is etched and the active matrix 100 is completely cut into a predetermined shape, and then the pad of the AMA panel and the pad of TCP are connected with an anisotropic conductive film (ACF) (not shown) to form a thin film type AMA module. Complete the manufacture of the module.

8A to 8D show leakage currents at a gate top, a gate bottom, a left source and a right source portion in the thin film type optical path adjusting device described in the applicant's prior application. 9A to 9D illustrate leakage currents at upper gates, lower gates, left and right source portions in the thin film type optical path adjusting device according to the present invention.

8A to 9D, the leakage current in the source and gate portions of the thin film type optical path control apparatus described in the preceding application in which an adhesion layer is formed using titanium is about 10 ⁻⁶ to 10 ⁻⁸ amperes (A). On the other hand, the leakage current of the thin film type optical path control apparatus according to the present invention, which forms a first diffusion barrier using titanium nitride rich in titanium without forming an adhesion layer, is about 10 ⁻⁹ to 10 ⁻¹¹ amperes (A). It can be seen that less. In addition, as shown in FIGS. 8A to 8D, the thin film type optical path control apparatus in which the adhesion layer is formed using titanium has a very large variation in the leakage current distribution, but as shown in FIGS. 9A to 9D, It can be seen that the leakage current of the thin film type optical path control device has a small distribution variation and shows precise results. Therefore, instead of forming an adhesion layer using titanium, a first diffusion barrier is formed using titanium nitride, which is rich in titanium, to diffuse silicon atoms while maintaining adhesion with the active matrix without forming an adhesion layer. The leakage current caused by this can be greatly reduced, so that the device can be driven more efficiently.

In the above-described thin film type optical path control device according to the present invention, the image current signal transmitted through the pad of the TCP and the pad of the AMA panel is a transistor, the drain pad 110 and the via contact 175 embedded in the active matrix 100. It is applied to the lower electrode 155 which is a signal electrode through. At the same time, a second signal is applied to the upper electrode 165 from the common electrode line through the pad of the TCP and the pad of the AMA panel to generate an electric field between the upper electrode 165 and the lower electrode 155. Due to this electric field, the deformation layer 160 between the upper electrode 165 and the lower electrode 155 causes deformation. The strained layer 160 is contracted in a direction perpendicular to the generated electric field, and thus the actuator 200 including the strained layer 160 is bent upward at a predetermined angle. Since the upper electrode 165, which also functions as a mirror that reflects the light beam, is formed on the actuator 200, the upper electrode 165 is inclined together with the actuator 200. Accordingly, the upper electrode 165 reflects the light beam incident from the light source at a predetermined angle, and the reflected light flux passes through the slit to form an image on the screen.

In the thin film type optical path control device according to the present invention, instead of forming an adhesion layer using titanium, a first diffusion barrier is formed using titanium nitride, which is rich in titanium, to be thermally formed by a subsequent high temperature process to form silicon. It is possible to suppress the formation of titanium silicide which promotes the diffusion of. Therefore, diffusion of silicon atoms from the inside of the active matrix can be prevented, and the first signal applied from the outside can be sufficiently delivered to the lower electrode, thereby improving the performance of the device. Furthermore, the adhesion between the active matrix and the second diffusion barrier can be maintained without forming an adhesion layer, and the first diffusion barrier and the second diffusion barrier can be formed in one chamber, thereby simplifying the manufacturing process. have.

Also, by forming the diffusion barrier as a double layer of the first diffusion barrier and the second diffusion barrier, even if the silicon atoms partially diffuse through the first diffusion barrier, the second diffusion barrier blocks the double diffusion so that the diffusion of the silicon atoms can be prevented more efficiently.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (4)

Providing an active matrix containing M × N (M, N is an integer) transistors; Iii) forming a first diffusion barrier over the active matrix, ii) forming a second diffusion barrier over the first diffusion barrier, and iii) forming a drain pad over the second diffusion barrier. Forming a first metal layer comprising; And forming a support layer on the active matrix and the first metal layer, forming a lower electrode on the support layer, forming a strain layer on the lower electrode, and an upper portion on the strain layer. And forming an actuator having a step of forming an electrode and forming a via contact connecting the bottom electrode and the drain pad. The method of claim 1, wherein the forming of the first diffusion barrier is performed using a sputtering method using titanium nitride (Ti­rich TiN) enriched with titanium. The method of claim 1, wherein the forming of the second diffusion barrier is performed using titanium nitride. The method of claim 1, wherein the forming of the second diffusion barrier further comprises heat treating the titanium nitride at a temperature of 800 ° C. to 900 ° C. for 5 to 10 minutes. .

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