KR100248994B1 - Manufacturing method of tma - Google Patents

Abstract

Disclosed is a method of manufacturing a thin film type optical path control device. An active matrix with M × N transistors is provided. One side contacts the upper portion of the active matrix and the other side forms a support layer in parallel with the active matrix through the air gap. After forming a lower electrode on the support layer, a strained layer made of PZT and a lead oxide (PbO) layer are sequentially formed thereon. After performing a heat treatment to phase change the PZT strain layer, the lead oxide layer is removed. An actuator is formed by forming an upper electrode on the deformation layer. Since lead (Pb) in the PbO layer covering the PZT strain layer diffuses into the PZT layer, it is possible to maintain the stoichiometric composition of the PZT strain layer by preventing the lack of lead (Pb) on the surface and inside of the PZT strain layer. High permittivity and spontaneous polarization (Ps) values can be obtained.

Description

Manufacturing method of thin film type optical path control device

The present invention relates to a method for manufacturing a thin film type optical path control apparatus using AMA (Actuated Mirror Array), and more particularly, to an actuator having a strained layer made of PZT (Pb (Zr, Ti) O ₃ ). The present invention relates to a method for manufacturing a thin film type optical path control device capable of maintaining a stoichiometric composition.

Optical path control devices or spatial light modulators for projecting optical energy onto a screen may be applied to various fields such as optical communication, image processing, and information display devices. Typically, such devices are classified into a direct-view image display device and a projection-type image display device according to a method of displaying optical energy on a screen.

An example of a direct-view image display device is a CRT (Cathode Ray Tube). The CRT device is called a CRT, which has excellent image quality but increases in weight and volume as the screen is enlarged, leading to an increase in manufacturing cost. There is. Projection type image display apparatuses include a liquid crystal display (LCD), a deformable mirror device (DMD), and an AMA. Such projection image display devices can be further divided into two groups according to their optical characteristics. That is, devices such as LCDs can be classified as transmissive spatial light modulators, while DMD and AMA can be classified as reflective spatial light modulators.

Transmission optical modulators, such as LCDs, have a very simple optical structure, which makes them thinner, lighter in weight, and smaller in volume. However, due to the polarity of the light, the light efficiency is low, there is a problem inherent in the liquid crystal material, for example, there is a disadvantage that the response speed is slow and the inside is easy to overheat. In addition, the maximum light efficiency of existing transmission light modulators is limited to a range of 1-2%, requiring dark room conditions to provide acceptable display quality. Therefore, optical modulators such as DMD and AMA have been developed to solve the above problems.

Although DMD shows a relatively good light efficiency of about 5%, the hinge structure employed in the DMD not only causes serious fatigue problems, but also requires a very complicated and expensive driving circuit. In the AMA, each of the mirrors installed therein reflects light incident from the light source at a predetermined angle, and the reflected light is projected on the screen through an aperture such as a slit or a pinhole. It is a device that can adjust the speed of light to form an image. Therefore, its structure and operation principle are simple, and high light efficiency (more than 10% light efficiency) can be obtained compared to LCD or DMD. In addition, the contrast of the image projected on the screen is improved to obtain a bright and clear image.

Each actuator of the AMA generates a deformation in accordance with the electric field generated by the applied electric picture signal and the bias signal. As the actuator deforms, each of the mirrors mounted thereon is tilted. Accordingly, the inclined mirrors reflect light incident from the light source at a predetermined angle to form an image on the screen. Piezoelectric materials such as PZT (Pb (Zr, Ti) O ₃ ) or PLZT ((Pb, La) (Zr, Ti) O ₃ ) are used as actuators for driving the respective mirrors. The actuator may also be configured as a warping material such as PMN (Pb (Mg, Nb) O ₃ ).

These AMA devices are largely divided into bulk type and thin film type. The bulk optical path control device is disclosed in US Pat. No. 5,085,497 to Gregory Um et al. The bulk optical path adjusting device is made by thinly cutting a multilayer ceramic to mount a ceramic wafer having a metal electrode formed therein in an active matrix in which a transistor is embedded, and then processing by a sawing method and installing a mirror thereon. However, the bulk optical path control device requires very high precision in design and manufacturing, and has a disadvantage in that the response of the strained layer is slow.

Accordingly, a thin film type optical path control apparatus that can be manufactured using a semiconductor manufacturing process has been developed. The thin film type optical path control device is disclosed in Korean Patent Application No. 96-42197 (name of the invention: a method of manufacturing a thin film type optical path control device that can control the stress of the membrane) filed by the applicant of the Korean Patent Office on September 24, 1996. It is.

Figure 1 shows a cross-sectional view of the thin film type optical path control device described in the preceding application.

Referring to FIG. 1, the thin film type optical path adjusting device includes an active matrix 1 and an actuator 60. An active matrix 1 having M × N (M, N is an integer) MOS (Metal Oxide Semiconductor) transistors and a drain pad 5 formed on one surface thereof includes the active matrix 1 and The protective layer 10 may be stacked on the drain pad 5, and the etch stop layer 15 may be stacked on the protective layer 10.

The actuator 60 may be stacked such that one side of the actuator 60 is in contact with a portion of the etch stop layer 15 in which the drain pad 5 is formed, and the other side thereof is parallel to the etch stop layer 15 via the air gap 25. Membrane 30, lower electrode 35 stacked on top of membrane 30, strained layer 40 stacked on top of lower electrode 35, upper electrode stacked on top of strained layer 40 ( 45, and from one side of the strained layer 40 to the drain pad 5 through the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer 10. The via contact 50 may include a via contact 55 formed to electrically connect the lower electrode 35 and the drain pad 5 to each other in a vertically formed via hole 50.

A stripe 46 is formed on a portion of the upper electrode 45. The stripe 46 operates the upper electrode 45 uniformly to prevent diffuse reflection of light incident from the light source.

Hereinafter, a method of manufacturing the thin film type optical path control device will be described with reference to FIGS. 2A to 2D. 2A to 2D, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 2A, an active matrix 1 formed of n-type doped silicon and including M × N (M, N is an integer) P-MOS transistors and a drain pad 5 formed on one side thereof is formed. A protective layer 10 made of Phosphor-Silicate Glass (PSG) is formed. The protective layer 10 is formed to have a thickness of about 1.0 μm by using a chemical vapor deposition (CVD) method. The protective layer 10 protects the active matrix 1 from subsequent processes.

An etch stop layer 15 made of nitride is formed on the protective layer 10. The etch stop layer 15 is formed to have a thickness of about 1000 to 2000 kPa using a low pressure chemical vapor deposition (LPCVD) method. The etch stop layer 15 prevents the protective layer 19 and the active matrix 1 from being etched during the subsequent etching process.

The sacrificial layer 20 is formed on the etch stop layer 15. The sacrificial layer 20 is formed of phosphorous silicate glass (PSG) having a high concentration of phosphorus (PG) to have a thickness of about 1.0 to 3.0 μm using the Atmospheric Pressure Vapor Deposition (APCVD) method. do. In this case, since the sacrificial layer 20 covers the upper portion of the active matrix 1 in which the transistor is embedded, the surface flatness is very poor. Therefore, the surface of the sacrificial layer 20 is planarized by using a spin-on glass (SOG) method or a chemical mechanical polishing (CMP) method. Subsequently, a portion of the sacrificial layer 20 in which the drain pad 5 is formed is etched to expose a portion of the etch stop layer 15, thereby forming a support of the actuator 60.

Referring to FIG. 2B, the membrane 30 is formed on the exposed etch stop layer 15 and the sacrificial layer 20 to a thickness of about 0.1 to 1.0 μm. Membrane 30 is formed using low pressure chemical vapor deposition (LPCVD). At this time, by forming the membrane 30 while varying the ratio of the reaction gas in the reaction vessel of low pressure, the stress in the membrane 30 is controlled.

The lower electrode 35 made of a metal such as platinum (Pt) or platinum-tantalum (Pt-Ta) is formed on the membrane 30. The lower electrode 35 is formed to have a thickness of about 0.01 to 1.0 탆 using the sputtering method. Subsequently, the lower electrode 35 is etched by a reactive ion etching process using an etching end point to separate the lower electrode 35 for each pixel so that an independent first signal (image signal) is applied to each pixel (Iso -Cutting process).

The strain layer 40 formed of PZT is formed on the lower electrode 35. The strained layer 40 made of PZT is spin-coated to have a thickness of about 0. 1 to 1.0 μm, preferably about 0.4 μm using a sol-gel method. ) And then phase change by Rapid Thermal Annealing (RTA) method. The strained layer 40 is deformed by an electric field generated between the upper electrode 45 and the lower electrode 35.

The upper electrode 45 is formed on the strained layer 40. The upper electrode 45 is formed of a metal having excellent electrical conductivity and reflectivity, such as aluminum or platinum, to have a thickness of about 0.01 to 1.0 탆 using a sputtering method. The second signal (bias signal) is applied to the upper electrode 45 from the outside through a common electrode line (not shown). In addition, the upper electrode 45 also functions as a mirror that reflects light incident from the light source.

Subsequently, the upper electrode 45 is patterned into a predetermined pixel shape. In this case, the stripe 46 is patterned to form one side of the upper electrode 45. Subsequently, the strained layer 40 and the lower electrode 35 are sequentially patterned into a predetermined pixel shape.

Referring to FIG. 2C, the strained layer 40, the lower electrode 35, the membrane 30, the etch stop layer 15, and the protective layer may be formed from an upper portion of one side of the strained layer 40 to an upper portion of the drain pad 5. The via hole 50 is formed by sequentially etching 10). Subsequently, a metal such as tungsten, platinum or titanium is deposited by a lift-off method to form a via contact 55 that electrically connects the drain pad 5 and the lower electrode 35. Therefore, the via contact 55 is formed vertically from the lower electrode 35 to the top of the drain pad 5 in the via hole 50. Therefore, the first signal applied from the outside is applied to the lower electrode 10 through the transistor, the drain pad 5 and the via contact 55 embedded in the active matrix 1.

Referring to FIG. 2D, a photoresist (not shown) is coated on the entire surface of the resultant product in which the via contact 55 is formed and patterned to expose the membrane 30. Subsequently, the membrane 30 is etched using the photoresist as an etching mask, thereby patterning a predetermined pixel shape. Subsequently, using the photoresist as an etching mask, the sacrificial layer 20 is etched by 49% hydrogen fluoride (HF) vapor to form an air gap 59, followed by rinsing and drying to perform AMA. Complete the device.

In the above-described thin film type optical path adjusting device, the first signal is applied to the lower electrode 35 through the MOS transistor, the drain pad 5, and the via contact 55 embedded in the active matrix 1. In addition, a second signal is applied to the upper electrode 45 to generate an electric field between the upper electrode 45 and the lower electrode 35. Due to this electric field, the strained layer 40 stacked between the upper electrode 45 and the lower electrode 35 causes deformation. The strained layer 40 contracts in a direction perpendicular to the electric field, and the actuator 60 including the strained layer 40 is bent in a direction opposite to the direction in which the membrane 30 is formed. Therefore, the upper electrode 45 on the actuator 60 is also inclined in the same direction. Light incident from the light source is reflected by the upper electrode 45 at a predetermined angle, and then is projected onto the screen to form an image.

However, according to the above-described thin film type optical path control apparatus, when the phase change (ie, crystallization) of the PZT layer as the strained layer is performed, lead oxide (PbO) is evaporated from the PZT layer so that lead (Pb) in the PZT layer is lost. do. That is, since PbO has a property of increasing volatility during the heat treatment, Pb in the PZT layer is released while PbO evaporates during the heat treatment of the PZT layer. As a result, it is difficult to match the stoichiometric composition on the surface of the PZT layer, resulting in a problem of decreasing the dielectric constant and spontaneous polarization (Ps) value of the PZT layer.

Accordingly, it is an object of the present invention to provide a method for manufacturing a thin film type optical path control apparatus capable of maintaining the stoichiometric composition of the PZT layer in an actuator having a strained layer made of PZT.

1 is a cross-sectional view of a thin film type optical path adjusting device described in the applicant's prior application.

2A to 2E are cross-sectional views illustrating a method of manufacturing the apparatus shown in FIG. 1.

3 is a plan view of the support layer of the thin film type optical path control apparatus according to the present invention.

4 is a cross-sectional view of the apparatus shown in FIG. 3 taken along the line A-A '.

5A to 5F are cross-sectional views illustrating a method of manufacturing the device shown in FIG. 4.

<Description of the code | symbol about the principal part of drawing>

100: active matrix 120: device isolation film

115: gate 110: source

105: drain 114: polysilicon pad

155: first metal layer 151: gate line

152: source line 153: drain pad

160: first protective layer 165: second metal layer

170: second protective layer 175: etch stop layer

180: sacrificial layer 185: support layer

190: lower electrode 195: strained layer

200: upper electrode 205: actuator

210: Beer Hall 215: Beer Contact

220: stripe 225: air gap

In order to achieve the above object, the present invention provides a method comprising the steps of providing an active matrix containing M × N (M, N is an integer) transistor; And i) forming a support layer in parallel with the active matrix with one side contacting the top of the active matrix and the other side through an air gap, ii) forming a bottom electrode on the top of the support layer, iii) the bottom Sequentially forming a PZT strain layer and a lead oxide (PbO) layer on top of an electrode, iv) performing a heat treatment to phase change the PZT strain layer, and then removing the lead oxide layer, and v) It provides a method of manufacturing a thin film type optical path control device comprising the step of forming an actuator having a step of forming an upper electrode on top of the strained layer.

In the above-described thin film type optical path control apparatus according to the present invention, the first signal transmitted from the outside is applied to the lower electrode through the transistor, the drain pad and the via contact embedded in the active matrix. At the same time, a second signal is applied to the upper electrode from the outside to generate an electric field between the upper electrode and the lower electrode. Due to this electric field, the strain layer formed between the upper electrode and the lower electrode causes deformation. The strained layer contracts in a direction orthogonal to the electric field, whereby the actuator is bent at a predetermined angle. The upper electrode, which also functions as a mirror that reflects light, is formed on the actuator and is inclined with the actuator. Accordingly, the upper electrode reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

According to the thin film type optical path control device according to the present invention, a PZT strain layer is formed on the lower electrode of the actuator, and a PbO layer is formed thereon, followed by heat treatment. As a result, lead (Pb) in the PbO layer covering the PZT layer diffuses into the PZT layer. Therefore, it is possible to maintain the stoichiometric composition of the PZT layer by preventing deficiency of lead (Pb) on the surface and the inside of the PZT layer, and obtain high dielectric constant and spontaneous polarization (Ps) values.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

Figure 3 is a plan view of the support layer of the thin film type optical path control apparatus according to the present invention, Figure 4 is a cross-sectional view taken along the line AA 'of the apparatus of FIG.

3 and 4, the thin film type optical path control apparatus includes an active matrix 100 and an actuator 205 formed on the active matrix 100.

The active matrix 100 is preferably made of n-type silicon and includes M × N (M, N is an integer) P-MOS transistors including a gate 115, a source 110, and a drain 105. do. In addition, the active matrix 100 includes a first protective layer 160 and a first protective layer 160 stacked on the first metal layer 155 and the first metal layer 9155 stacked on the active matrix 100. ) A second metal layer 165 stacked on top of the second metal layer 165, a second protective layer 170 stacked on the second metal layer 1650, and an etch stop layer 175 stacked on the second protective layer 170. Here, reference numeral 120 denotes an isolation layer for dividing the active matrix 100 into an active region and a field region, and reference numeral 125 denotes a gate 115 of the MOS transistor thereon. An insulating film for insulating from the stacked first metal layer 155 is shown.

The first metal layer 155 includes a drain pad for transmitting a first signal (image signal) to the lower electrode 190. The second metal layer 165 includes a first layer 165a stacked using titanium (Ti) and a second layer 165b stacked using titanium nitride (TiN).

The actuator 205 may have a support layer having a cross-section formed in parallel with the etch stop layer 175 through one side of the etch stop layer 175, the one side of which is in contact with a portion where the drain pad is formed, and the other side via the air gap 225. 185, the lower electrode 190 stacked on the support layer 185, the strained layer 195 stacked on top of the lower electrode 190, the upper electrode 200 stacked on top of the strained layer 195, The strain layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second passivation layer 170, and the first passivation layer 160 are formed from one side of the strain layer 195. And a via contact 215 formed in the via hole 210 vertically up to the drain pad.

In addition, referring to FIG. 3, one side of the plane of the support layer 185 has a rectangular concave portion at the center thereof, and the concave portion is formed to have a stepped shape toward both edges. The other side of the plane of the support layer 185 has a rectangular protrusion that narrows stepwise toward the central portion corresponding to the concave portion. Therefore, the concave portion of the support layer of the actuator adjacent to the concave portion of the support layer 185 is fitted, and the rectangular projection is fitted into the concave portion of the adjacent support layer. The support layer 185 functions as a membrane supporting the actuator of the thin film type optical path adjusting device described in the previous application. A stripe 220 is formed on one side of the upper electrode 200 to uniformly operate the upper electrode 200 to prevent diffuse reflection of light incident from the light source.

Hereinafter, a method of manufacturing a thin film type optical path control device according to the present invention will be described in detail with reference to the drawings.

5A to 5F are cross-sectional views for explaining the method for manufacturing the device shown in FIG. 4. 5A to 5F, the same reference numerals are used for the same members as in FIG.

Referring to FIG. 5A, after preparing an active matrix 100 made of n-type doped silicon, the active matrix 100 is prepared using a conventional device isolation process, for example, a local oxidation of silicon (LOCOS) method. An isolation layer 120 is formed in the active region and the field region. Subsequently, a gate 115 made of a conductive material such as polysilicon doped with impurities is formed on the active region, and then p ⁺ source 110 and drain 105 are formed by an ion implantation process. N P-MOS transistors are formed.

After forming the first insulating layer 125 made of an oxide on the resultant formed MOS transistor, the first metal layer 155 is formed thereon. The first metal layer 155 is made of tungsten and titanium, and includes a drain pad extending to one side of the support layer 185 formed in a subsequent process.

Referring to FIG. 5B, the first protective layer 160 is formed on the first metal layer 155 to protect the active matrix 100 having the MOS transistor. The first passivation layer 160 is formed to have a thickness of about 8000 kPa using the silicate glass (PSG) method using a chemical vapor deposition (CVD) method. The first protective layer 160 prevents the transistor embedded in the active matrix 100 from being damaged during subsequent processes.

A second metal layer 165 is formed on the first passivation layer 160. In order to form the second metal layer 165, first, titanium (Ti) is sputtered to form the first layer 165a having a thickness of about 300 μm. Subsequently, titanium nitride (TiN) is deposited on the first layer 165a using physical vapor deposition (PVD) to form a second layer 165b. Since the light incident from the light source is incident not only to the upper electrode 200, which is a reflective layer, but also to a portion other than the portion where the upper electrode 200 is formed, the second metal layer 165 may have a light leakage current in the active matrix 100. To prevent it from flowing. Subsequently, a portion of the second metal layer 165 where the via contact 215 is to be formed in a subsequent process is etched through a photolithography process.

Subsequently, a second protective layer 170 is formed on the second metal layer 165. The second protective layer 170 is formed to have a thickness of about 2000 GPa using in-silicate glass (PSG). The second protective layer 170 also prevents damage to the transistor embedded in the active matrix 100 during the subsequent process.

Subsequently, an etch stop layer 175 is formed on the second passivation layer 170. The etch stop layer 175 prevents the active matrix 100 and the second passivation layer 170 from being etched due to the subsequent etching process. The etch stop layer 175 is formed by depositing nitride (Si ₃ N ₄ ) by a low pressure chemical vapor deposition (LPCVD) method to have a thickness of about 1000 ~ 2000Å.

Subsequently, a sacrificial layer 180 is formed on the etch stop layer 175. The sacrificial layer 180 is formed by depositing phosphorus silicate glass (PSG) to a thickness of about 2.0 to 3.0 μm by the atmospheric pressure chemical vapor deposition (APCVD) method. In this case, since the sacrificial layer 180 covers the top of the active matrix 100 in which the transistor is embedded, the surface flatness is very poor. Therefore, by using a spin on glass (SOG) method or a chemical mechanical polishing (CMP) method by polishing the surface of the sacrificial layer 180 so that the sacrificial layer 180 to a thickness of about 1.1㎛ Planarize. Subsequently, a portion of the sacrificial layer 180 under which the drain pad is formed and a portion (not shown) where the gate line 151 is formed are etched to expose a portion of the etch stop layer 175 to thereby expose the actuator 205. The support 182 is formed.

Referring to FIG. 5C, the support layer 185 is formed on the exposed etch stop layer 175 and on the sacrificial layer 180. The support layer 185 is formed to have a thickness of about 0.1 to 1.0 μm using low pressure chemical vapor deposition (LPCVD).

Subsequently, a lower electrode 190 is formed on the support layer 185. The lower electrode 190 is formed to have a thickness of about 0.01 to 1.0 탆 by sputtering a metal such as platinum (Pt), tantalum (Ta), or platinum-tantalum (Pt-Ta). At the same time, the lower electrode 190 is separated for each pixel so that an independent first signal (image signal) is applied to each pixel (Iso-Cutting process). The first signal transferred from the transistor embedded in the active matrix 100 is applied to the lower electrode 190.

Subsequently, a strain layer 195 formed of PZT is formed on the lower electrode 190. The strained layer 195 made of PZT is formed to a thickness of about 0.01 to 1.0 탆 using a sol-gel method, a sputtering method, or a chemical vapor deposition method. Preferably, the PZT strain layer 195 is spin-coated to have a thickness of about 0.4 μm using the sol-gel method. Next, a PbO layer 196 is formed on the PZT strained layer 195 to a thickness of about 800 GPa.

Referring to FIG. 5D, the PZT strained layer 195 may be thermally phased by rapid thermal annealing (RTA). In the above heat treatment process, since lead (Pb) in the PbO layer 196 covering the PZT strained layer 195 diffuses into the PZT strained layer 195, the PZT strained layer 195 is generated on and in the surface of the PZT strained layer 195. Pb deficiency can be prevented. Subsequently, the PbO layer 196 is removed using dilution water (D.I water).

Next, an upper electrode 200 is formed on the strained layer 195. The upper electrode 200 is formed to have a thickness of about 0.01 to 1.0 μm by sputtering a metal such as aluminum (Al), silver (Ag), or platinum (Pt). The upper electrode 200 receives a second signal (bias signal) for generating an electric field from the outside through a common electrode line (not shown). Since the upper electrode 200 has excellent electrical conductivity and reflectivity, the upper electrode 200 performs not only a function of a bias electrode but also a mirror reflecting incident light.

Subsequently, the upper electrode 200, the deformation layer 195, and the lower electrode 190 are sequentially patterned from a top of the upper electrode 200 into a predetermined pixel shape. In this case, a stripe 220 is formed at one side of the upper electrode 200 to uniformly operate the upper electrode 200 to prevent diffuse reflection of light incident from the light source.

Referring to FIG. 5E, the strained layer 195, the lower electrode 190, the support layer 185, the etch stop layer 175, the second passivation layer 170, and the first passivation layer from one side of the strain layer 195. The via holes are sequentially etched to form the via holes 210. Accordingly, the via hole 210 is formed from one side of the strained layer 195 to the drain pad of the first metal layer 155. Subsequently, a metal having excellent electrical conductivity such as tungsten (W), aluminum (Al), or titanium (Ti) is deposited using a sputtering method to form a via contact 215. The via contact 215 electrically connects the drain pad and the lower electrode 190 of the first metal layer 155. Therefore, the first signal applied from the outside is applied to the lower electrode 190 through the transistor, the drain pad, and the via contact 215 embedded in the active matrix 100. Subsequently, the support layer 185 is patterned into a predetermined pixel shape.

Referring to FIG. 5F, the sacrificial layer 180 is etched using hydrogen fluoride (HF) vapor to form an air gap 225, and then a rinse and dry process is performed to rinse the AMA device. Complete

Although not shown, after completing the M × N thin film type AMA device, sputtering or evaporation of metal silicides such as titanium (Ti) silicide, cobalt (Co) silicide and nickel (Ni) silicide is performed. It is deposited on the bottom of the active matrix 100 to form an ohmic contact. Subsequently, a conventional photo is prepared in preparation for a tape carrier package (TCP) (not shown) bonding for applying a second signal to a subsequent upper electrode 200 and a first signal to the lower electrode 190. The active matrix 100 is cut to a predetermined thickness using a lithographic method. Subsequently, a photoresist layer (not shown) is formed over the pad of the AMA panel so that the pad of the AMA panel (not shown) has a sufficient height in preparation for TCP bonding. Subsequently, a portion of the photoresist layer on which the pad is formed is patterned to expose the pad of the AMA panel. Subsequently, the photoresist layer is etched and the active matrix 100 is completely cut out into a predetermined shape, and then the pad of the AMA panel and the TCP pad are connected with an anisotropic conductive film (ACF) (not shown) to form a thin film AMA. Complete the manufacture of the module.

In the above-described thin film type optical path control device according to the present invention, the first signal transmitted through the pad of the TCP and the pad of the AMA panel is lowered through the transistor, the drain pad, and the via contact 215 embedded in the active matrix 100. Is applied to the electrode 190. At the same time, a second signal is applied to the upper electrode 200 through a pad of TCP, a pad of an AMA panel, and a common electrode line to generate an electric field between the upper electrode 200 and the lower electrode 190. Due to this electric field, the deformation layer 195 formed between the upper electrode 200 and the lower electrode 190 causes deformation. The strained layer 195 contracts in a direction orthogonal to the electric field, whereby the actuator 205 including the strained layer 195 is bent at a predetermined angle. The upper electrode 200, which also functions as a mirror that reflects light, is formed on the actuator 205 and is inclined together with the actuator 205. Accordingly, the upper electrode 200 reflects the light incident from the light source at a predetermined angle, and the reflected light passes through the slit to form an image on the screen.

As described above, according to the thin film type optical path adjusting device according to the present invention, a PZT strain layer is formed on the lower electrode of the actuator, and a PbO layer is formed thereon, followed by heat treatment. As a result, lead (Pb) in the PbO layer covering the PZT layer diffuses into the PZT layer or the lower Pt layer. Therefore, it is possible to maintain the stoichiometric composition of the PZT layer by preventing the lack of lead (Pb) in the surface of the PZT layer and in the PZT layer, and obtain high dielectric constant and spontaneous polarization (Ps) value.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (3)

Providing an active matrix containing M × N (M, N is an integer) transistors; And I) forming a support layer on top of the active matrix, i) forming a support layer in parallel with the active matrix with one side contacting the top of the active matrix and the other side via an air gap, ii) forming a lower electrode on the support layer Step, iii) sequentially forming a PZT strain layer and a lead oxide (PbO) layer on the lower electrode, iv) performing a heat treatment to phase change the PZT strain layer, and then removing the lead oxide layer. And v) forming an actuator having a step of forming an upper electrode on top of the strained layer. The method of claim 1, wherein the forming of the lead oxide layer is performed using a sol-gel method. The method of claim 1, wherein the removing of the lead oxide layer comprises removing the lead oxide layer using dilution water.

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