KR100247001B1 - Protocol changer between frame relay and atm switching center and method there of - Google Patents

Abstract

SUMMARY OF THE INVENTION An aspect of the present invention provides an interlocking device between a frame relay and an ATM switch, wherein the central processing unit controls the operation of the interlocking device and performs a protocol conversion function, between the first bus forming the data path and the central processing unit. A second buffer connected between the first bus and a second bus forming a control information path and the central processing unit, a shared packet memory storing interlocking data, and a frame received in association with the frame relay side HDLC frame storing data in the shared packet memory and notifying the central processing unit, and accessing the data stored in the shared packet memory when converting the frame data into the frame format of the frame relay when the central processing unit outputs the frame data. Re-synthesizing the received ATM cell in association with a processing unit and the ATM switch; An AAL5 processing unit for notifying the central processing unit after storing the data in a kit memory and converting the frame data stored in the shared packet memory into ATM cell data when the central processing unit outputs the command; and the HDLC frame processing unit The AAL5 processor separates the first bus from the shared packet memory access, and the AAL5 processor comprises a bus controller configured to separate the HDLC frame processor and the first bus from the shared packet memory access.

Description

Protocol conversion device and method of frame relay and ATM switch {PROTOCOL CHANGER BETWEEN FRAME RELAY AND ATM SWITCHING CENTER AND METHOD THERE OF}

The present invention relates to an interworking apparatus and method of a frame relay and an ATM, and more particularly, to an apparatus and a method capable of converting a protocol using a shared memory.

In general, an Asynchronous Transfer Mode switch should be able to interoperate with a frame relay that accepts a frame relay subscriber to enable frame data transmission of the frame relay through an ATM switching network. In the interworking device of the frame relay and the Asynchronous Transfer Mode (ATM), since the two devices receive data of two protocols having different data formats and transmit them to the opposite party, a function capable of converting the protocol to the other device should be provided. do.

1 illustrates a structure of an interlock apparatus of a conventional frame relay and an ATM switch. The interlocking device having the configuration as shown in FIG. 1 includes a T1 / E1 line interface 105, a T1 / E1 frame processor 106, an HDLC frame processor 107, and an AAL5 control memory AAL5. control memory 109, bus controller 101, central processing unit (CPU) 104, IPC communication unit (Inter Processor Communication) 111, and local memory (CPU local memory) 110 and the like.

Referring to FIG. 1, the T1 / E1 frame processor 106, HDLC frame processor 107, HDLC transmit / receive packet memory 103, AAL5 processor 108, AAL5 transmit / receive packet memory 102, AAL5 control memory 109, IPC communication unit 111 and local memory 110, etc. All elements of the device are connected on a single CPU local bus. The bus controller 101 determines whether the HDLC transmit / receive packet memory 103 is to be accessed by the HDLC frame processor 107 or the central processing unit 104 to generate a control signal for activating each of the buffers 112 and 113. For the AAL5 control memory 109, it is determined whether the AAL5 processing unit 108 or the central processing unit 104 will access, and also generates a control signal for activating or deactivating the respective buffers 114 and 115. FIG. The AAL5 processing unit 108 receives a bus occupancy right from the bus control unit 101 without a buffer and accesses the transmission / reception packet memory 102 and the control memory 109.

The T1 / E1 line interface unit 105 and the T1 / E1 frame processing unit 106 receive the T1 / E1 signal transmitted from the frame relay side to recover data and clock, extract data from the T1 / E1 frame, and then extract the data from the HDLC frame processing unit 107. A T1 / E1 transmission frame is generated from the data received from the HDLC frame processing unit 107 or line coded and transmitted to the frame relay.

The HDLC frame processor 107 extracts frame data of the frame relay from the T1 / E1 PCM data received from the T1 / E1 frame processor 106 and stores the frame data of the frame relay in the HDLC transmit / receive packet memory 103. When the reception of one frame is completed, the HDLC frame processing unit 107 notifies the central processing unit 104 of this. Then, the central processing unit 104 corrects the data for conversion to the ATM protocol for the received frame data, and then instructs the AAL5 processing unit 108 to segment the ATM cell. In addition, when frame data to be transmitted to the frame relay side is reassembly completed in the AAL5 processing unit 108 and copied by the central processing unit 104 from the AAL5 transmit / receive packet memory 102 to the HDLC transmit / receive packet memory 103, the HDLC frame processing unit 107 reconstructs it. To the T1 / E1 frame processing unit 106 according to the frame format.

When the frame relay data received by the HDLC frame processor 107 is copied from the HDLC transmit / receive packet memory 103 to the AAL5 transmit / receive packet memory 102 by the central processing unit 104, the AAL5 processor 108 divides the frame data into an ATM cell to divide the cell bus. The ATM exchange side forwards it to the subscriber concentrator. In addition, the AAL5 processing unit 108 receives the ATM cell from the subscriber concentrator on the ATM switch side, resynthesizes the frame data, and stores it in the AAL5 transmit / receive packet memory 102. When the resynthesis of the frame data is completed, the AAL5 processor 108 notifies the CPU 104 of this. Then, the central processing unit 104 notified of the completion of the resynthesis of the frame data corrects the data for conversion to the frame relay protocol in the resynthesized frame data of the AAL5 transmit / receive packet memory 102, and then reconfirms the HDLC transmit / receive packet memory 103 Copy to

The AAL5 control memory 109 is a memory that stores various control information required to perform an operation of the AAL5 processing unit 108. The bus controller 101 allocates the bus occupancy right from the current state of the bus and the requested state of the bus, and generates a control signal for activating the buffers 112, 113, 114, and 115. The local memory 110 is a memory that stores a program or data necessary to perform a function of the central processing unit 104. The IPC communication unit 111 is a port for communication with the upper processor of the ATM switch and performs a port function for transmitting / receiving connection establishment / release, connection management information, connection status information, system status information, and the like.

The conventional frame relay and ATM interworking apparatus as shown in FIG. 5 includes an HDLC transmission / reception packet memory 103 for storing frame data according to the protocol of the frame relay and a memory for storing cell data according to the ATM protocol, and the HDLC frame. The processing unit 107 and the AAL5 processing unit 108 process each packet, and the conversion between the two protocol data is performed by the central processing unit 104 after reading all the data in the memory, calculating the conversion parameters, and handing them over according to the format of the partner protocol data.

FIG. 2 is a diagram illustrating the structure of a packet memory and a descriptor in a conventional companion device having the configuration as shown in FIG. 1, wherein the descriptors of the HDLC frame processing unit 107 and the AAL5 processing unit 108, and the transmit / receive packet memories 103 and 102 are shown. The structure of the is shown. In FIG. 2, the descriptor of the HDLC frame processor 107 is composed of a packet pointer, packet length, packet state information, and next descriptor pointers. The descriptor of the AAL5 processor 108 is composed of a packet pointer, packet length, packet state information, and the like. Since the HDLC frame processor 107 only needs to process data of the frame relay protocol, the HDLC frame processor 107 divides the HDLC transmit / receive packet memory 103 into small sized packets according to variable length packets and allocates them to the scripters. Therefore, one frame relay frame is stored by one or several descriptors depending on the packet length. The AAL5 processor 108 allocates an AAL5 transmit / receive packet memory 102 to one descriptor as long as it can accommodate the maximum packet length of the frame relay, so that one reassembly is completed by a descriptor of one AAL5 processor 108. Stored.

3 is a flowchart illustrating a process of converting a protocol when data received at the frame relay side is transmitted to the ATM side in a conventional interlocking apparatus, and FIG. 4 is a frame relay of data received at the ATM side in a conventional interlocking apparatus. A flowchart illustrating the process of converting a protocol that can be transmitted.

Referring to the operation of the interlocking device between the conventional ATM switch and the frame relay having the above components, the T1 / E1 frame processing unit 105, HDLC frame processing unit 107, AAL5 processing unit 108, IPC communication unit 111, local memory 110, HDLC transmission and reception packet memory Components such as 103, AAL5 transmit / receive packet memory 102, and AAL5 control memory 109 are all connected to one local bus of the central processing unit 104. In particular, in order to accommodate a large number of frame relay subscribers, the T1 / E1 line interface unit 105, the T1 / E1 frame processing unit 106, and the HDLC frame processing unit 107 independently transmit and receive frame data. When the processing unit 107 accesses the HDLC transmit / receive packet memory 103, it must occupy the local bus of the central processing unit 104 alone. The AAL5 processor 108 must occupy the local bus of the central processing unit 104 alone in order to segment the frame data or to generate the frame data by resynthesizing the received cell data.

The central processing unit 104 performs protocol conversion between the frame relay and the ATM exchange period between the frame data from the frame relay side and the cell data to the ATM switch side, processing packet data transmitted and received, managing the state of each element, and establishing a connection. Perform / release, manage connection state, etc. In this case, when the central processing unit 104 performs the above function, the central processing unit 104 has to compete frequently to obtain the occupancy rights of the bus when transmitting and receiving frame data in the HDLC frame processing unit 107 and transmitting and receiving cell data in the AAL5 processing unit 108. Can not fully exhibit the performance.

The transfer paths of the frame data and the cell data of the user to be transmitted / received and transmitted to and from the functional processing of the central processing unit 104 related to the operation and management of the interworking device of the ATM exchanger and the frame relay are transferred to the local bus of the central processing unit 104. Since the HDLC frame processing unit 107 or the AAL5 processing unit 108 does not acquire the right to occupy the bus for a predetermined time, a serious delay occurs in user data to be transmitted.

The conventional interlock device as described above transmits data transmitted from the frame relay side to the ATM as shown in FIG. 1, 3, and 4, the HDLC frame processor 107 receiving frame data transmitted from the frame relay side stores the packet data of the received HDLC frame in the HDLC transmit / receive packet memory 103. When the reception of the HDLC frame is completed, the central processing unit 104 notifies of this. The CPU 104 detects this in step 211, reads the contents of the first descriptor in step 213, and reads data of the packet length from the packet address of the descriptor in step 215 and stores the data in the local memory 110. Thereafter, in step 217, the first descriptor for the frame is checked. If not, in step 219, the next descriptor stored in the next descriptor pointer area is read, and the process returns to step 215 and repeats the above process.

Thereafter, the CPU 104 copies the data from the HDLC transceiver packet memory 103 to the AAL5 transceiver packet memory 102. For this purpose, the CPU 104 analyzes an address area and calculates an ATM cell header mapping value in step 221. In step 223, an AAL5 CPCS PAD and a trailer are calculated, and in step 225, a CPCS PDU is stored in the AAL5 transmit / receive packet memory 102. In step 227, the descriptor of the AAL5 processing unit 108 is allocated and set, and when the AAL5 processing unit 108 is notified in step 229, the AAL5 processing unit 108 divides and outputs the packet data stored in the AAL5 transmission / reception packet memory 102 into an ATM cell.

In addition, when one frame of data is received from the ATM switch, the AAL5 processing unit 108 resynthesizes and stores the data in the AAL5 transmission / reception packet memory 102 and notifies the central processing unit 104 of this. Then, the central processing unit 104 detects this in step 311, performs the steps 313-319, reads the descriptor, reads the packet length data from the packet address, analyzes the descriptor and the CPCS trailer, and maps the address area. After calculating the value, the required number of descriptors of the HDLC frame processing unit 107 is calculated. Thereafter, the CPU 104 converts the data stored in the AAL5 transmit / receive packet memory 102 into the HDLC transmit / receive packet memory 103. For this, the descriptor of the HDLC frame processor 107 is allocated in step 321, and steps 323 to 325. After storing the address region in the first descriptor, the CPCS payload region is stored up to the last descriptor, and in step 327 it is notified to the HDLC frame processor 107. Then, the HDLC frame processor 107 performs an operation for transmitting data stored in the HDLC transmit / receive packet memory 103 to the frame relay side.

In the conventional interlocking device having the above configuration and operation, the central processing unit 104 transmits the HDLC transmit / receive packet memory 103 and the AAL5 transmit / receive packet memory when the protocol conversion from the frame relay to the ATM switch or the protocol exchange from the ATM switch to the frame relay is performed. There is a problem that the data is copied between the 102, such a copy of the data is a very heavy load on the central processing unit 104, thereby lowering the processing capacity of the central processing unit 104. In other words, the conventional interworking apparatus separately sets the HDLC transmit / receive packet memory 103 and the AAL5 transmit / receive packet memory 102 so that the central processing unit 104 copies these converted data when a protocol conversion occurs between the frame relay and the ATM protocol. Due to the heavy load of the 104, there is a problem that causes a processing delay and transmission delay in the system due to the deterioration of the control and the limited bus usage of the peripheral components.

Accordingly, an object of the present invention is to provide an interworking device and a method for communication communication between an ATM terminal and a frame relay device by accessing a frame relay service device in an ATM switch.

Another object of the present invention is to provide an apparatus and a method for reducing contention for bus occupancy by using a data bus as a dual bus structure in an ATM exchanger and a frame relay interworking device.

It is still another object of the present invention to provide an apparatus and method for reducing data copy time by sharing a transmission / reception packet memory of a frame relay processing unit and a transmission / reception packet memory of an ATM adaptive layer processing unit in an ATM exchanger and a frame relay interworking device.

According to an aspect of the present invention, there is provided an interworking apparatus of a frame relay and an ATM exchange system, the central processing unit controlling the operation of the interlocking apparatus and performing a protocol conversion function, a first bus forming the data path, and the central processing unit. A second bus that forms a first buffer and a control information path connected between a processing device and a second buffer connected between the central processing device, a shared packet memory for storing interlocked data, and interworking with the frame relay side. And store the received frame data in the shared packet memory and notify the central processing unit, and the central processing unit accesses the data stored in the shared packet memory when converting the frame data into a frame format of the frame relay. An HDLC frame processing unit for outputting and receiving an ATM cell interworking with the ATM switch; An AAL5 processing unit for synthesizing and storing the data in the shared packet memory and notifying the central processing unit, and converting the frame data stored in the shared packet memory into ATM cell data when the central processing unit outputs the converted data; And an HDLC frame processor separating the AAL5 processor and the first bus when the shared packet memory is accessed and the AAL5 processor is configured as a bus controller which separates the HDLC frame processor and the first bus when the shared packet memory is accessed. do.

1 is a diagram showing the configuration of a conventional frame relay and ATM interlock device

FIG. 2 is a diagram showing the structure of a packet memory in FIG.

3 is a flowchart illustrating a process of converting a protocol performed from a frame relay to an ATM in a conventional interlocking device;

4 is a flowchart illustrating a process of converting a protocol performed from ATM to frame relay in a conventional interlocking device;

5 is a diagram illustrating a configuration of a frame relay and an ATM interworking apparatus according to an embodiment of the present invention.

6 shows a frame structure of a frame relay;

7 illustrates a frame structure of an AAL5 CPCS PDU.

8 is a diagram illustrating a packet memory structure of a companion device according to an embodiment of the present invention.

9 is a flowchart illustrating a protocol conversion process from a frame relay to an ATM in an interworking device according to an embodiment of the present invention.

10 is a flowchart illustrating a protocol conversion process from an interworking device to an ATM frame relay according to an embodiment of the present invention.

The interworking device between the ATM switch and the frame relay according to the embodiment of the present invention has the configuration as shown in FIG. Referring to FIG. 5, the central processing unit 503 initializes, operates, and manages each component and element of an interlocking device, protocol conversion between a frame relay and an ATM exchange, establishes and releases a connection, manages a state of a connection, and a higher level. Controls functions such as communication with ATM switches.

The bus of the CPU 503 is configured in a double bus structure by buffers 511 and 512. The bus 520 on the buffer 512 side is connected with blocks having functions independent of the data transmission path to be transmitted and received, and the bus 519 on the buffer 511 side is connected with elements related to the path of user data to be stored. That is, the processing path of the information related to the operation of the interlock device is configured on the bus 250 on the buffer 512 side, and the transmission path of the user frame data or the cell data is configured only on the bus 519 on the buffer 511 side.

The transmission and reception shared packet memory 502 capable of storing the transmitted and received frame data and cell data in the same packet memory is provided on the user data transmission path bus, and the HDCL frame processing unit 506 stores the received frame data therein by the buffer 513. The frame relay frame is generated by reading the resynthesized cell data. The CPU 503 accesses the frame data stored in the shared packet memory 502 or the resynthesized cell data by the buffer 514 for protocol conversion.

The AAL5 processing unit 507 receives the bus occupancy right from the bus control unit 501 without a buffer, accesses the shared packet memory 502, segments the received frame data into ATM cells, or receives the ATM cell from the subscriber concentrator, and recombines the frame data into the shared packet memory 502. Will be stored. The AAL5 processing unit 507 functions to segment the frame data received from the frame relay side to generate an ATM cell or to receive the ATM cell from the subscriber concentrator on the ATM switch side to resynthesize the frame data.

The bus controller 501 controls the occupancy of each bus and generates an activation or deactivation signal of each of the buffers 511-515.

The T1 / E1 line interface unit 504 and the T1 / E1 frame processing unit 505 transmit and receive and process frame data on the frame relay side. The HDLC frame processing unit 506 is connected to the T1 / E1 line interface unit 504 and the T1 / E1 frame processing unit 505 to receive T1 / E1 PCM data to process a frame relay protocol to extract frame data of a frame relay or to extract a frame of a frame relay. It forms and delivers to the T1 / E1 frame processing unit 505.

The local memory 509 is a memory that stores a program or data necessary for performing a function of the CPU 503. The IPC communication unit 510 performs a function of transmitting and receiving connection or status information between the companion device and the upper processor of the ATM switch according to an embodiment of the present invention.

The interlocking apparatus according to the embodiment of the present invention having the configuration as shown in FIG. 5 has a double bus structure by dividing the user data processing path and the control and management information processing path of the central processing unit 503. This improves the data processing and transmission performance of the CPU 503, the HDLC frame processor 506, and the AAL5 processor 507. In the dual bus structure, the user data bus 519 separated by the buffer 511 is a bus allocated for storing and transmitting frame data and ATM cell data of a frame relay to be transmitted and received. The bus 520 divided by the buffer 512 is a bus that the CPU 503 accesses for initialization, control, and state management of each element constituting the interlocking device.

In the above dual bus structure, the CPU 503 deactivates the buffer 511 and activates the buffer 512 while the HDLC frame processor 506 or the AAL5 processor 507 occupies the user data path bus 519 to access the shared packet memory 502. Other functions not related to protocol conversion of data may be performed, thereby improving performance of the CPU 503. In addition, the HDLC frame processing unit 506 or the AAL5 processing unit 507 can occupy the user data path bus 519 while the CPU 503 accesses the bus 520, thereby improving the processing capacity of the user data to be transmitted and reducing the transmission delay. have.

In addition, the companion device having the configuration as shown in FIG. 5 integrates the memory storing the HDLC transmission / reception packet and the memory storing the AAL5 transmission / reception packet into the shared packet memory 502. When the shared packet memory 502 is used as described above, when there is a protocol conversion, the central processing unit 503 occupies a bus and does not copy data, and modifies data for protocol conversion without copying data on the shared packet memory 502. After that, the completion of protocol conversion is notified to the HDLC frame processing unit 506 or AAL5 processing unit 507.

Referring to the operation of the interlocking device of the ATM switch and the frame relay having the configuration as shown in FIG. 5, the bus of the CPU 503 is divided into two buses 519 and 520 by buffers 511 and 512. The processing path of the information related to the operation of the companion device is made on the bus 520 on the buffer 512 side, and the transmission path of user frame data or cell data is made only on the bus on the buffer 511 side. The above operation is performed by controlling the buffer 511 and the buffer 512 in the bus controller 501.

Fig. 6 is a program structure of a frame relay, which is composed of a start byte of 1 byte, an address of 2 bytes, user information of 1 to 8188 bytes, an FCS of 2 bytes, and an end flag of 1 byte. . 7 is a frame structure of an AAL5 CPCS PDU, which includes a payload area of 0 to 65535 bytes, a PAD area of 0 to 47 bytes, a CPCS-UU area of 1 byte, a CPI area of 1 byte, and a length of 2 bytes. (length) area, and a 4-byte CRC-32 area. In the above configuration, CPCS-UU, CPI, Length, and CRC-32 become CPCS trailer information.

8 is a diagram illustrating a structure of a shared packet memory 502 according to an embodiment of the present invention, wherein the HDLC frame processing unit 506 and the AAL5 processing unit 507 read and write corresponding packet information, respectively, and the central processing unit 503 uses the protocol. Perform the function of converting.

The packet to be transmitted and received by the HDLC frame processor 505 and the packet to be transmitted and received by the AAL5 processor 507 are stored together in the shared packet memory 502. The shared packet memory 502 having the structure as shown in FIG. 8 is configured so that the HDLC frame processing unit 506 and the AAL5 processing unit 507 can simultaneously identify one packet. The descriptor of the HDLC frame processor 506 allocates one descriptor to one frame data, and the length of the shared packet memory 502 is as large as the size of the PAD and CPCS trailer for converting the AAL5 PDU to the maximum user information length of the address and frame relay. Leave the space empty. The packet pointer points to the first address in the address field. The descriptor of the AAL5 processing unit 507 points to the first address of the user information area excluding the address area.

9 is a diagram illustrating a process of converting protocol data of a frame relay into ATM protocol data according to an embodiment of the present invention, and FIG. 10 is a diagram illustrating a process of converting protocol data of an ATM into protocol data of a frame relay. to be.

Look at the protocol conversion process as described above.

The process of processing frame data transmitted from the frame relay side to the ATM switch will be described. The frame data of the frame relay received through the T1 / E1 line interface unit 504 and the T1 / E1 frame processor 506 is processed by the HDLC frame processor 506 and stored in the transmission / reception shared packet memory 502. At this time, the buffer 513 is activated, the buffer 514 is deactivated, and the function of the AAL5 processing unit 507 to access the shared packet memory 502 is deactivated. When one frame data of the frame relay is received, the HDLC frame processor 506 notifies the CPU 503 of this.

Then, the CPU 503 receiving the notification performs the protocol conversion process by the process shown in FIG. First, when the CPU 503 is notified of the completion of the reception of the HDLC frame in step 611, in step 613, the central processing unit 503 reads the descriptor value of the HDLC frame processing unit 506, and in step 615, accesses only an address area from the packet address of the descriptor. After that, in step 617, the address region accessed is calculated to calculate the mapping value of the ATM cell header, and in step 619, the AAL5 CPCS PAD and the trailer are calculated. In operation 621, the calculated PAD and trailer information are stored after the user information area in the frame structure of the frame relay shown in FIG. 6. In step 623, the descriptor of the AAL5 processing unit 507 is allocated and set, and in step 625, the segment is commanded to the AAL5 processing unit 507.

As described above, the CPU 503 accesses the shared packet memory 502 and modifies the received frame relay frame data into a data format suitable for the ATM protocol. At this time, the buffer 514 is activated, the buffer 513 is deactivated, and the access of the shared packet memory 502 by the AAL5 processing unit 507 is deactivated.

After modifying the ATM protocol conversion as described above, the CPU 503 notifies the AAL5 processing unit 507 to instruct the segmentation into the ATM cell. The AAL5 processor 507 notified that the frame data segmented into the ATM cell is ready, accesses the shared packet memory 507 and starts segmentation. At this time buffers 513 and 514 are deactivated. The fragmented frame data is transmitted to the subscriber aggregation unit of the ATM switch in the form of an ATM cell.

In the protocol conversion method described above, when data reception of one frame is completed by the HDLC frame processing unit 506, the CPU 503 reads an address area from the shared packet memory 502 indicated by the packet pointer in the descriptor of the HDLC frame processing unit 506. The parameter value of the ATM cell header to be indented is calculated, and the PAD and CPCS trailer in the CPCS PDU of the ATM are filled immediately after the user information area using the packet length information of the descriptor. This completes the ATM's CPCS PDU, sets the packet pointer of the descriptor of the AAL5 processing unit 507 to point to the first address of the user information area, and adds the packet length information to the sum of the user information (payload), PAD, and CPCS trailer. Set it. Then, the AAL5 processing unit 507 divides the converted CPCS PDU into an ATM cell and outputs the divided part.

Secondly, a process of processing ATM cell data input from the ATM switch side and transmitted to the frame relay side will be described with reference to FIG. 10. The ATM cells inputted from the subscriber concentrator on the ATM switch side are resynthesized by the AAL5 processing unit 507 for each connection to the shared packet memory 502. At this time, the buffers 513 and 514 are inactivated. When the resynthesis is completed, the AAL5 processing unit 507 notifies the central processing unit 503 of this. The CPU 503 then accesses the shared packet memory 502 and converts the resynthesized cell data into a frame suitable for the protocol of the frame relay. At this time, the buffer 514 is activated, the buffer 513 is deactivated, and access to the shared packet memory 502 of the AAL5 processing unit 507 is deactivated.

When the AAL5 processing unit 507 is notified of the recombination completion, the CPU 503 detects this in step 711, and in step 713 reads the descriptor of the AAL5 processing unit 507. In step 715, the CPU 503 analyzes the descriptor and the CPCS trailer, calculates an address region mapping value, and stores the address region in front of the CPCS payload in step 717. Thereafter, in step 719, the descriptor of the HDLC frame processor 506 is allocated, and then in step 721, the HDLC frame processor 506 is frame-framed and transmitted.

As described above, when the protocol data of the ATM exchange is converted to the frame relay, the CPU 503 notifies the HDLC frame processing unit 506 of this request and transmits the data. Then, the HDLC frame processing unit 506 accesses the shared packet memory 502 to form a frame format of a frame relay, and transmits the frame format to the frame relay through the T1 / E1 frame processing unit 505 and the T1 / E1 line interface unit 504.

The bus controller 501 controls the bus occupancy right assignment for the bus usage request of the CPU 503, the HDLC frame processor 505, and the AAL5 processor 507, and controls the buffers 511 to 515 to prevent bus errors.

In the protocol conversion method as described above, when the AAL5 processing unit 507 completes resynthesis of the CPCS PDU from the ATM cell in the form as shown in FIG. 7, the CPU 503 returns the packet pointer and packet length information of the descriptor of the AAL5 processing unit 507. After calculating the address area parameter values of the frame relay from the connection information and the connection information, and stores the address value in front of the address indicated by the packet pointer of the descriptor of the AAL5 processing unit 507. One descriptor of the HDLC frame processor 506 is assigned to the frame pointer, the packet pointer points to an address of an address area, and the length of the packet sets a length obtained by adding an address and a payload (user information) area. Then, the HDLC frame processor 506 starts transmitting the protocol-converted frame as described above.

As described above, the interlocking apparatus according to the embodiment of the present invention operates HDLC by dividing the bus of the central processing unit 503 into a bus 519 for transmitting and receiving user data and a bus 250 for operating, controlling, and managing the interlocking apparatus. Since the frame processor 506 or the AAL5 processor 507 accesses the shared packet memory 502 to store and process user data, the central processing can be performed by accessing components other than the shared packet memory 502 through the buffer 512. The performance of the device 503 can be improved.

The companion device according to the embodiment of the present invention can process the data by accessing the shared packet memory 502 by the HDLC frame processor 506 or the AAL5 processor 507 while the CPU 503 accesses other components through the buffer 512. As a result, bus occupancy for processing user data of the processing units 506 and 507 can be increased, thereby improving data processing capability and reducing user data processing delay time.

The companion device according to the embodiment of the present invention shares the memory storing the transmission / reception packets of the HDLC frame processing unit 506 and the AAL5 processing unit 507 as one memory, so that the HDCL frame processing unit 506 and the AAL5 processing unit 507 share data for protocol conversion. You can remove the copy. This reduces the load that the central processing unit 503 has to process and eliminates the bus occupancy time of the central processing unit 503 for data copying, thereby increasing the user transmit / receive data throughput of the entire system and at the same time delay time in the companion device. Can be reduced.

Therefore, as described above, the ATM exchanger and the frame relay interworking device according to the embodiment of the present invention can improve the processing performance of the CPU 503 and the data processing performance of the HDLC frame processing unit 506 and the AAL5 processing unit 507, This has the advantage of being able to accommodate a large number of frame relay subscribers.

Claims (4)

In the interworking of the frame relay and the ATM exchanger, A double bus comprising a first bus to which data processing interfaces with an ATM switch and a frame relay side are connected, a second bus to which components for processing control information of an interworking device are connected, and A shared memory connected to the second bus, the ATM exchanger and the frame relay side, and configured to store data generated by interworking with the ATM exchanger and the frame relay side; Central processing for controlling the overall operation of the interlocking device, connected to the first bus through a first buffer, and connected to the second bus through a second buffer to separate and process data and control information of the interlocking device. Interworking device between the frame relay and the ATM switch, characterized in that provided with a device. In the interworking of the frame relay and the ATM exchanger, A central processing unit controlling the operation of the interlocking device and performing a protocol conversion function; A first buffer connected between the first bus forming the data path and the central processing unit and a second buffer connected between the second bus forming the control information path and the central processing unit; A shared packet memory for storing interlocked data, Frame data received in association with the frame relay side is stored in the shared packet memory and notified to the central processing unit, and the central processing unit accesses the data stored in the shared packet memory when a frame data output command is issued to the frame relay. HDLC frame processing unit for converting to the frame format of the output; After resynthesizing the received ATM cell by interworking with the ATM switch and storing it in the shared packet memory, the central processing unit is notified, and when the central processing unit outputs, the frame data stored in the shared packet memory is segmented. An AAL5 processing unit for converting and outputting ATM cell data; And the HDLC frame processor separates the AAL5 processor and the first bus when the shared packet memory is accessed, and the AAL5 processor is configured as a bus controller that separates the HDLC frame processor and the first bus when the shared packet memory is accessed. Frame relay and interlock of ATM switch. In the protocol conversion method of the frame relay and the ATM exchanger comprising an HDLC frame processing unit for processing frame data of a frame relay, an AAL5 processing unit for processing an ATM cell of an ATM exchanger, and a shared packet memory, When the frame data is output from the frame relay, when the HDLC frame processing unit stores the frame data received in the shared packet memory, the frame structure of the frame relay is converted into an AAL5 frame structure, and the segment is notified to the AAL processing unit. Converting, by the AAL5 processor, the frame data stored in the shared packet memory into an ATM cell; When the ATM switch outputs ATM cell data, when the AAL5 processing unit resynthesizes the received ATM cells for each connection and stores them in the shared packet memory, the AAL5 frame structure is converted into a frame relay structure and notified to the HDLC frame processing unit. And converting the HDLC frame processing unit into the frame format of the frame relay by accessing the shared packet memory. In the protocol conversion method of the frame relay and the ATM exchanger comprising an HDLC frame processing unit for processing frame data of a frame relay, an AAL5 processing unit for processing an ATM cell of an ATM exchanger, and a shared packet memory, When the frame data of the frame relay is stored in the shared packet memory, accessing an address stored in the shared packet memory from an HDLC descriptor, calculating a parameter value of an ATM cell header, and converting the protocol into an AAL5 frame structure; When the AAL5 frame data is stored in the shared packet memory, the packet information is accessed from the AAL5 descriptor, the address of the frame relay is calculated, and the protocol is converted into a frame relay frame structure. Protocol conversion method.

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