JPH0654027A - Layer 2 termination circuit - Google Patents

Abstract

PURPOSE:To provide the high multiplexity and high throughput layer 2 termination circuit applicable even to a broad band ISDN. CONSTITUTION:An external RAM is used for a state management table required for protocol processing and the RAM and a processor in a layer 2 termination circuit 100 are connected by an internal bus 101. Moreover, a timer circuit 180 consists of an exclusive controller and a RAM. Furthermore, when the number of setting links is less, a part of the RAM in the timer circuit is used also for a stage management memory. Thus, high multiplexing is realized while suppressing required hardware quantity. Moreover, the built-in RAM in the layer 2 termination circuit 100 is effectively utilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device, and more particularly, to a layer 2 termination circuit which realizes a layer 2 protocol process.

[0002]

2. Description of the Related Art Narrowband ISDN currently in practical use
In, the maximum line speed available to the user is 1.
It is 5 Mbit / s or 2 Mbit / s. In addition, in a layer 2 protocol processing device of HDLC (High level Data Link Control) system or LSI, the maximum usable line speed is 10 Mbit / max.
It is about s. As an example of this kind of LSI for realizing the layer 2 protocol processing, for example, in Technical Report SSE89-85 of the Institute of Electronics, Information and Communication Engineers, "Study of Hi
The LSI proposed under the title "gh Speed Control of Data Link Layer Protocol" can be cited.

[0003]

At the present time, CCITT (International Telegraph and Telephone Advisory Committee) is studying broadband ISDN as a next-generation ISDN. Broadband I
The SDN provides the user with, for example, 150 Mbit /
s line speed service. However, the conventionally proposed layer 2 protocol processing LSI cannot support the line speed of the broadband ISDN. Therefore, the realization of a new layer 2 termination circuit that can effectively utilize the line speed of the broadband ISDN is an important issue.

In order to effectively utilize the line speed of the broadband ISDN, it is necessary to realize the following two points.

(1) Realization of "high throughput": The applicable maximum line speed is set to, for example, 150 Mbit / s or more, and the frame processing capacity (the number of frames that can be transmitted / received per unit time) is commensurate with the improvement of the maximum line speed. ) Also improve.

(2) Realization of "high multiplexing": Increase the maximum number of links that can be set or processed at the same time. In this case, the partner terminal (layer 2 protocol processing LSI) cannot always process the line speed of 150 Mbit / s. Also, during the introduction period of wideband ISDN, most of the partner terminals have a maximum line speed of 16 kbit /
It is considered to be a layer 2 protocol processing LSI of about s or 64 kbit / s, and if the same layer 2 termination circuit processes a plurality of links, the maximum line speed of the broadband ISDN can be effectively utilized.

Among the above-mentioned two problems, an LSI that realizes "high throughput" is "protocol control VSI for broadband.
Packet communication ”(PROTOCOL CONTOROL
VLSI FOR BROADBAND PACKET COMMUNICATIONS), GRO
The LSI described in BECOM '88, 45.6 can be mentioned.

Generally, when implementing protocol processing,
A memory is required to store variables such as status variables for each link and retry counters. It is also necessary to provide a timer for each link. Therefore, the technical problem for realizing "high multiplexing" is, in other words, how to realize a large number of state management memories and timers. However, if a large amount of memory or a plurality of timer circuits are easily added to realize the above-mentioned problem, the required amount of hardware increases in proportion to the increase in the number of links supported by the layer 2 termination circuit. In addition, the chip area of the LSI increases accordingly, which causes a problem of increased manufacturing cost. On the other hand, if such an LSI is applied to a small number of links, most of the hardware is wasted.

An object of the present invention is to solve the above technical problems and to realize a layer 2 termination circuit applicable to wideband ISDN.

[0010]

In order to achieve the above object, in the present invention, a large number of timers required for realizing protocol processing are configured by a dedicated controller and RAM,
RAM for timer when the number of links to set is small
It is characterized in that a part of the area can be used as a state management memory.

Another aspect of the present invention is that a large amount of state management memory necessary for implementing protocol processing is placed outside the chip of the layer 2 termination circuit LSI, and this memory is provided with an internal bus in the layer 2 termination circuit. Is connected to the processor in the layer 2 termination circuit so that the state management memory can be directly accessed.

[0012]

According to the present invention, since the timer is composed of the timer controller and the memory, high multiplexing can be realized while suppressing the required hardware amount. Further, when the number of links to be set is small, the hardware can be effectively used by using a part of the timer memory as the state management memory.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows an example of the system configuration of an ATM exchange to which the present invention is applied.

Broadband ISDN is an ATM (Asynchronous
Transfer Mode (Asynchronous Transfer Mode) It is realized by the exchange method. The "ATM switching system" is a system in which all data such as call control signals, voice, and images are transmitted and received in fixed length packets called "cells". For example,
When the layer 2 frame of the signaling channel shown in FIG. 3 is transmitted, the frame is once decomposed into fixed-length cells in the ATM switch (this process is called "segmentation").
Then, the cell is transmitted to the subscriber line / relay line. On the contrary, when a cell is received, a frame is reproduced from the received cell (this process is called "reassembly"). In the CCITT Recommendation I.121 (blue book), the segmentation / reassembly process is positioned as a function of the adaptation layer, which is a lower layer of Layer 2. Hereinafter, in the present specification, the adaptation layer processing circuit including the segmentation / reassembly processing is referred to as an “ADP processing circuit”.

In FIG. 2, a signal processing device 30 includes an ADP processing circuit 40 for performing adaptation processing such as segmentation and reassembly, and a layer 2 termination circuit 100 for performing layer 2 protocol processing of a signal channel.
A bus 14 (transmission bus 1 for transmitting data of a signal frame)
4a and the receiving bus 14b).

The signal processing device 30 is connected to the ATM switch 20 via a bus 13 (a transmission bus 13a and a reception bus 13b) and transmits / receives data to / from a processor bus 15 having a 16-bit or 32-bit width, for example, a 32-bit width. Layer 3 of the signaling channel via the data bus 16
A processor 50 for performing protocol processing (call control) of
It is connected to the memories 51 and 52.

The memory 52 is a memory that functions as a buffer for storing transmitted / received data.
Is a memory used to store the program executed by the processor 50, and to notify the layer 2 termination circuit 100 of buffer address information of transmission / reception data stored in the memory 52. In addition, 11 (11-
1 to 11-j) are optical fibers having a data transmission rate of, for example, 150 Mbit / s or 600 Mbit / s, and 12 (12-1 to 12-j) and 13 are transmission buses each having an 8-bit width, for example. It is an internal bus composed of a reception bus and a reception bus. Reference numeral 10 (10-1 to 10-j) is a line interface unit (LIF), which performs conversion of optical / electrical signals and setting of route information in the ATM switch for each cell. Reference numeral 20 is an ATM switch for exchanging fixed-length cells.
The method described in No. 1-309546 "Packet switch" can be adopted.

Next, details of the layer 2 termination circuit 100 will be described with reference to FIG.

The direct memory access controller (DMAC) 190 is connected to the memory 51 via the processor bus 15, and is activated by the processor (CP) 130 to send a transmission start command or transmit / receive commands from the memory 51.
The reception buffer address and the like are read and transferred to the local memory (LM) 131.

The LM 131 is a work memory for the CP 130. Since the LM 131 is also accessed by the DMAC 190, for example, by applying a dual port memory or the like, access conflict does not occur.

Reference numeral 130 denotes protocol state transition control,
This is a processor that passes commands / statuses to / from the upper processor 50, manages a transmission / reception buffer, and the like. For example, when this processor receives a transmission start command from the upper processor 50, it performs state transition control prescribed by the protocol, sends a timer start instruction to the timer circuit 180 as necessary, and transmits the transmission control processor. For (TxP) 110,
Send a send start command.

An external RAM (CM) 200 has a relatively large memory capacity, for example, a capacity of about 256 kbytes.
It is used as a work area for temporarily storing state variables of each link necessary for transmission / reception control and information exchanged between each processor. Forming a large-capacity memory of about 256 kbytes on the LSI chip of the layer 2 termination circuit is disadvantageous in terms of chip yield. Also, when the number of links to be set is small, a large amount of memory on the chip is wasted. Therefore, in this embodiment, such a memory is provided outside the layer 2 termination circuit 100. However, as will be described later, in the present embodiment, a part of the memory in the timer circuit 180 can be used also as the work area described above, so that the external RAM 200 is not necessary in the case where the number of links to be set is small. Is.

The CP 130 sends a signal for switching between the "small link mode" of 300 links or less and the "multilink mode" of, for example, about 8,000 links at the signal line 108 according to an instruction from the host processor 50. Via the bus interface circuit 132 and the timer circuit 18
Send to 0. However, a signal for switching the mode may be input from an external input pin or the like of the layer 2 termination circuit. Bus interface circuit 132
When receiving a signal from the CP 130 indicating that it is in the low link mode, the terminal sets the termination of the internal bus 101 to high impedance and disconnects the internal bus 101 from the outside of the layer 2 termination circuit. On the contrary, when a signal indicating the multi-link mode is received, the internal bus 101 is connected to the outside of the layer 2 termination circuit so that the three processors in the layer 2 termination circuit are connected to the internal bus. Via 101,
The external RAM 200 can be accessed.

On the other hand, when the timer circuit 180 receives a signal indicating the small link mode from the CP 130, as will be described later, part of the RAM in the timer circuit causes the bus to operate.
It is made accessible from 101, and conversely, when a signal indicating the multilink mode is received, it is made inaccessible.

The transmission control processor (TxP) 110 is
When receiving the transmission activation command from the CP 130, the local memory (LM) 111 is used as a work area, a layer 2 header (address field 202 and control field 203 shown in FIG. 3) is generated, and this is generated by the transmission interface circuit (TxIF). ) 140, then activates the DMAC 191 via the signal line 103, and finally activates transmission to the transmission interface circuit 140,
Start sending frames.

In the case of a frame such as an FRMR (Frame Reject) frame in which the information field 204 must also be generated / transmitted in Layer 2, the information field is generated by the transmission control processor 110, and in the above procedure, , Instead of activating the DMAC 191, the generated information field is stored in the transmission FIFO 160, and then transmission activation is performed to the transmission interface circuit 140 to transmit the frame.

The transmission interface circuit 140 is connected to the ADP processing circuit 40 via the transmission bus 14a, and at the time of frame transmission, the frame start / end flag 201 and the frame check sequence (FCS) in the frame format shown in FIG. 205 is automatically added.

Reception interface circuit (RxIF) 15
0 is connected to the ADP processing circuit 40 via the reception bus 14b. When a reception frame is detected, the frame start / end flag 201 and the FCS 205 are removed, and only the header parts 202 and 203 of the frame are sent to the reception control processor 150. The information field 204 is transferred to the reception FIFO 170. Also, the FCS of the received frame is checked, and the check result is notified to the RxP 120.

The reception control processor (RxP) 120 is
When the header of the received frame is received from the RxIF 150, the local memory (LM) 121 is used as a work area, the header is checked, and then the signal line 104
The DMAC 191 is activated via.

The DMAC 191 transfers the reception data (information field 204 of the reception frame) to the reception buffer on the memory 52, and notifies the RxP 120 of the transfer result.

Upon receiving the transfer end notification from the DMAC 191, the RxP 120 notifies the CP 130 of the result, and the CP 130 performs the necessary procedure processing.

When a layer 2 needs to process the information field of the frame, such as a FRMR (Frame Reject) frame, the RxP 120 uses the DMAC.
191 is not started and the received information field is RxF
It is taken out from the IFO 170, and the necessary protocol processing is performed in the CP 130.

In the present embodiment, in order to realize high throughput, the transmission / reception line which was conventionally 1 bit is changed to an 8-bit bus, and the DMAC and the bus for transmission / reception data transfer are used for the interface with the upper processor. DMAC
And it is separated from the bus. Next, details of the timer circuit 180 will be described.

FIG. 5 shows a first embodiment of the timer circuit 180, which is a timer controller (TCNT).
181, two-sided RAMs 182-1 and 182-2, and a selector 183.

The RAM 182-1 is a RAM having a capacity of about 8 kbytes, for example, and is used only as a timer counter. On the other hand, the RAM 182-2 is also a RAM having a capacity of about 8 kbytes, for example.
Different from 1, it is used as a timer counter in the multi-link mode and as a shared work area of three processors in the layer 2 termination circuit in the low-link mode. This switching is performed by the selector 183. Selector 183
When receiving a signal from the CP 130 via the signal line 108 indicating the multi-link mode, the timer controller (TCNT) 181 enables access to the RAM 182-2, and conversely indicates the low-link mode. Upon receiving the signal, it enables the three processors in layer 2 termination circuit 100 to access RAM 182-2 via bus 101.

The timer controller 181 uses the RAM 182-1 in the small link mode and also uses the RAM 182-2 in the multi link mode to realize a timer function for a plurality of links.

FIG. 4 shows an example of using the RAM 182 in the timer circuit in the multi-link mode. Each timer is an 8-bit (1 byte) counter, and two types of timers are used for each link.

When the timer controller 181 receives a timer start notification from the processor in the layer 2 termination circuit, the timer controller 181 calculates the address of the target timer counter from the specified link number and timer type, and the specified timer at that address. The timer is started by writing the initial value of. The timer controller 181 always scans the timer memory from the beginning, and subtracts 1 when the memory content is other than 0. When the memory content is 0, it indicates that the timer is not activated. As a result, the memory contents are 0
If it occurs, the CP 130 is notified of the occurrence of timeout by the signal line 102. When the CP 130 receives the timeout occurrence notification, the CP 130 retrieves the information of the link number and the timer type in which the timeout has occurred from the timer controller 181 via the bus 101, and performs necessary protocol processing.

The timer controller 181 uses the CP
When the timer stop instruction is received from 130, the timer is stopped by setting the contents of the timer counter of the specified link number and timer type to zero.

In the first embodiment of the timer circuit shown in FIG. 5, the RAM is divided into two (182-1 and 182-2), but this system has the same capacity as these two RAMs. There is a problem that the area of the RAM occupied on the chip increases as compared with the case where the RAM is realized by one RAM. Therefore, as shown in FIG. 6, these two RAs are
It is also possible to realize a timer circuit equivalent to the above by realizing M with one RAM 182 and using a time division circuit.

[0042]

As is apparent from the above description, according to the present invention, since the timer is composed of the timer controller and the memory, it is possible to realize high multiplexing while suppressing the required hardware amount. . In addition, if the number of links to be set is small, you can use a part of this timer memory as the status management memory to add external RAM.
Is unnecessary, and the internal RAM can be effectively used.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a configuration of a layer 2 termination circuit according to the present invention.

FIG. 2 is a diagram showing an example of application of the layer 2 termination circuit to an ATM exchange.

FIG. 3 is a diagram showing a frame format.

FIG. 4 is a diagram showing a usage example of a RAM 182 in the timer circuit.

FIG. 5 is a diagram showing a first embodiment of a timer circuit 180.

FIG. 6 is a diagram showing a second embodiment of the timer circuit 180.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... ATM switch, 15 ... Control bus, 16 ... Data bus, 20 ... ATM switch, 30 ... Signal processing device, 40
... Adaptation processing circuit, 100 ... Layer 2 termination circuit, 180 ... Timer control circuit, 200 ... External RAM.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sakae Miki 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (5)

[Claims] 1. In a communication control circuit for realizing a communication protocol such as an HDLC procedure, a plurality of timers required for protocol processing are composed of a dedicated controller, a two-sided memory and a selector, and a signal to the selector is sent. By switching, both of the two side memories are used as timer counters, or only one side memory is used as a timer counter, and the other side memory is used by the processor in the communication control circuit for protocol processing. A layer 2 termination circuit characterized in that it can be used as a work area necessary for performing. 2. A communication control circuit for realizing a communication protocol such as an HDLC procedure, wherein a plurality of timers required for protocol processing are composed of a dedicated controller, one surface memory and a time division circuit, and the time division circuit is provided. By switching the signal to, the entire area of the memory is used as a timer counter, or a part of the memory is used as a timer counter, and the remaining area is processed by the processor in the communication control circuit by protocol processing. A layer 2 termination circuit characterized in that it can be used as a work area necessary for performing. 3. Layer 2 according to claim 1.
The termination circuit, which is a memory outside the layer 2 termination circuit,
It is characterized in that it is connected to the bus of the processor in the layer 2 termination circuit, and the processor in the layer 2 termination circuit can use a memory outside the layer 2 termination circuit as a work area for performing protocol processing. Layer 2 termination circuit. 4. Layer 2 according to claim 2.
The termination circuit, which is a memory outside the layer 2 termination circuit,
It is characterized in that it is connected to the bus of the processor in the layer 2 termination circuit, and the processor in the layer 2 termination circuit can use a memory outside the layer 2 termination circuit as a work area for performing protocol processing. Layer 2 termination circuit. 5. The layer 2 termination circuit according to claim 1, further comprising a notification means for switching the maximum number of links. circuit.