JPH10313325A - Cell-discarding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently discard cells by discarding the cell which lingers the most and storing the cell which is newly received, when a free buffer ring for realtime connection is separately managed and overflow occurs in a buffer. SOLUTION: In a free buffer ring 43 used for real time connection, respective entries are managed by a tail pointer 41 and a head pointer 42. The entries of the free buffer ring 43 have start addresses for the respective buffers 44-1 to 44-6. When the values of the head pointer 42 and the tail pointer 41 are matched in the structure of the free buffer ring, overflow occurs. The value of the head pointer 42 is increased, the cell which previously arrives is discarded, and the cell which is received later is stored in the address which the tail pointer 41 points. Thus, the cell whose significance has deteriorated and whose time delay is the lorgest can be discarded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM network interface card (NIC), and more particularly to an ATM NIC.
The present invention relates to a method for discarding received ATM cells in the event that an overflow occurs in the reorganization buffer while the system is operating in real time.

[0002]

2. Description of the Related Art ATM (Asynchronous Transmission System) provides a circuit switching network for providing services such as voice and video at a constant bit rate, and provides services such as data and video at a variable bit rate. A fast cell switching technology based on cells of a fixed length (eg, 53 bytes) that combines the greatest advantages with a packet switched network to do so. That is, the message on the transmitting side is divided into a plurality of cells and transmitted, and the receiving side restores the received message through a reorganization process.

[0003] Such an ATM communication system has a hierarchical structure. FIG. 1 is a schematic diagram of a general ATM protocol reference model having a hierarchical structure. The B-ISDN protocol reference model is composed of three planes: a management plane, a control plane, and a user plane.

[0004] The management plane has two functions of hierarchy management and plane management. This plane management function has all management functions related to the entire system. No layer structure is used in the management plane. The hierarchical management has a layer structure, and performs management related to resources and parameters remaining in the protocol entity.

[0005] In the control plane, call control and connection control are performed, which are signaling functions required to set up, manage and release calls or connections. The user plane serves to convey user information and has associated mechanisms such as flow control or error recovery.

The control plane and user plane protocols are:
As shown in Table 1 below, upper layer, ATM adaptation layer, ATM
It consists of a hierarchy and a physical hierarchy.

[0007]

[Table 1]

As shown in Table 1 above, the ATM communication system uses a physical layer, an ATM layer, and an ATM adaptive layer (AAL: ATM).
It has a vertically hierarchical structure such as an adaptation layer and an upper layer. The AAL layer is divided into a convergence (CS) sublayer and a division and reorganization (SAR) sublayer, and the physical layer is subdivided into a physical medium (PM) sublayer and a transmission convergence (TC) sublayer.

[0009] The service to the user can be classified as shown in Table 2 below.

[0010]

[Table 2]

AA corresponding to the service described in Table 2 above
The L protocol includes AAL1 to AAL5 as shown in Table 3 below.
Divided by

[0012]

[Table 3] As shown in Table 3, the AAL hierarchy is AAL1, AAL2,
AAL3 / 4, AAL, etc., can be divided in a plane.

On the other hand, connecting a user terminal to an ATM network requires an ATM NIC and appropriate software.
ATM NICs are connected to user terminals connected to the ATM network.
A NIC driver for controlling the function is installed, and performs a function of an upper layer according to a predetermined protocol.
More specifically, the NIC driver allocates / deallocates a buffer in a memory in the NIC for transmitting / receiving a packet,
Update the value of a control variable or handle various interrupts.
A packet is a bundle of data in a predetermined format, but does not coincide with a cell in the ATM system.

Upon receiving the ATM cells, the NIC temporarily stores the received cells in a buffer, eg, a reorganization buffer, in the order in which they arrive in the buffer, before the reorganization process takes place. At this time, if the reorganization buffer is full and cannot accommodate any more incoming cells due to the limited capacity of the reorganization buffer, an overflow occurs in the reorganization buffer.

[0015] For this reason, cells supplied from a message in a real-time process may be lost due to transmission delay or process delay. As the data is transmitted in real time, the longer the delay, the less important the data initially stored in the current buffer. Thus, when an overflow occurs, the cells stored in the reorganization buffer must be discarded, and it is necessary to determine what cells should be discarded. In that case, it is more preferable to discard the initial cells since the cells arriving earlier are less important in time than the cells arriving last.

[0016]

SUMMARY OF THE INVENTION It is therefore a primary object of the present invention to provide a QOS by discarding received ATM cells when an overflow occurs in the reorganization buffer while the ATMNIC is operating in real time. It is to provide an improved ATM cell discarding method.

[0017]

In order to achieve the above object, according to the present invention, an ATM network interface card is provided.
(NIC) for discarding cells received for processing time-dependent data, said ATM NI
C converts a message from the user into a cell suitable for the ATM-based communication system under the control of the host system, and reorganizes the received cell stored in the data buffer pointed to by the entry of the free buffering to revert to the original cell. A step of setting up the free buffering, each consisting of a plurality of entries pointing to the data buffer using a head pointer and a tail pointer, and a cell requiring real-time service to the ATM NIC. If input, the B step of comparing the value of the head pointer and the value of the tail pointer existing in the free buffering, and if the value of the head pointer does not match the value of the tail pointer, Stores the received cell in the buffer pointed to by the tail pointer Step C, and if the value of the head pointer matches the value of the tail pointer, increment the value of the head pointer by 1, discard the first received cell, and discard the last received cell. There is provided a cell discarding method, comprising: a step D for storing the value in the buffer pointed to by the tail pointer; and an step e for increasing the value of the tail pointer by one.

[0018]

Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a schematic block diagram showing an example of an ATM network interface card (NIC) according to a preferred embodiment of the present invention.

As shown in FIG. 2, the host system 10
Is connected to an ATM network (not shown) through the ATM NIC 20, and exchanges data with the host system on the opposite side by the ATM method. Further, the host system 10 is a workstation or a decapsulator, and the ATM NIC 20
Is a card or board inserted into a workstation or decap.

The host system 10 includes the application program 1
1, NIC driver 12, memory 13, processor 14
And an ATM NIC 2 through an input / output bus (S bus in the embodiment of the present invention) 30.
0 is connected.

The application program 11 is usually a group of software wafers and is executed to provide an interactive service to a user. The NIC driver 12 is also composed of a group of software wafers, and provides the user with an ATM.
It is for providing a communication service. In response to a request from the NIC driver 12, the ATM NIC sets up various tables and rings related to ATM network communication and updates data in the tables as shown in FIG.

The NIC driver 12 is a NIC driver 20
Serves to directly control the Memory 13 incorporates buffers such as descriptor rings, completion rings and data buffers.

As shown in FIG. 2, the ATM NIC 20 includes an AAL processing unit 21, a SONET / ATM line adapter 22, a transceiver 23, a control RAM 25, and a ROM 26.
ATM communication method physical layer, ATM
It processes the functions of the hierarchy and the AAL hierarchy. In particular, in the embodiment of the present invention, the ATM NIC 20 transmits the ATM cells to a synchronous optical network (SONET: SynChRono).
us Optical Network K) After matching with the STS-3C frame format (155.52 Mbps), it is connected to an ATM network through an optical synchronous transmission network. Referring to FIG. 2, the AAL processing unit 21 is connected to a control RAM 25 through a local memory bus, and is connected to a ROM 26 through a local slab bus. At this time, the ROM 26 is connected to the SON through the local bus.
It is also connected to the ET / ATM line adapter 22.

The AAL processing unit 21 is connected to the input / output bus 3
0 and connected so that the host memory 11 can be directly accessed and the control RAM 25 can be read / written, and the processor 12 of the host system can also directly access and read / write the control RAM 25 through the input / output bus. Has become.

When an application program operated by the host system 10 requests an ATM-related service, an NIC driver operated by the host system controls the ATM NIC 20 in response to the request to transfer the ATM-related service to the application program. Supply. For example, when the application program stores predetermined message data in the host memory 11 and requests data transmission, the NIC driver requests the AAL processing unit 21 to transmit data via the input / output bus 30.

The AAL processing unit 21 reads a message stored in the host memory 11 in units of a predetermined length (48 bytes) to form an ATM cell according to a protocol format, and then reads the SONET / ATM line of the physical layer 24. The data is transmitted to the adapter 22. The SONET / ATM line adapter 22 converts each ATM cell into a SONET STS-
The data is matched in the 3C format, and the transmitter / receiver 23
The serial data in the C format is converted into an optical signal and output to the ATM network via an optical cable.

On the other hand, data received through the transceiver 23 is transmitted from the SONET / ATM line adapter 22 to the AT.
After being separated into M cells and taken out, they are input to the AAL processing unit 21. After separating the header and the pay load from the received ATM cells, the AAL processing unit 21 restores the message (packet) by combining the pay load again, and when the reorganization of the message is completed, the AAL processing unit 21 interrupts to the host system 10. Inform this. When an interrupt indicating the completion of the reorganization is received from the AAL processing unit 21, the NIC driver of the host system transmits the message received through a predetermined process to the application program.

As described above, the AAL processing unit 21 divides the message transmitted from the upper layer into ATM cells and transmits the ATM cells to the opposite side, and reconstructs the received ATM cells to reconstruct the message. Is completed, the NIC driver of the host system is notified of this through the overlap.

The structure in which data is transmitted between the upper layer and the AAL processing unit in such an ATM NIC will be described in more detail.

The host system 10 and the ATM NIC 20
3 is divided into transmission and reception as shown in FIG. 3, and is located in the host memory 11 and the control RAM 25, respectively. That is, the host memory 11 has a transmission descriptor ring (TX descriptor ring) used for transmission and a transmission completion ring (TX completion rin).
g), the data buffer is located, and the data buffer used at the time of reception, the reception completion ring (RX c
Omissionion ring) and two free buffering rings. In the control RAM 25 of the NIC, a bandwidth allocation table and a transmission DMA status table used for transmission are located, and a reception DMA status table used for reception is located.

The transmission descriptor ring implemented in the host memory 11 includes 255 virtual channels and can have 255 virtual channels. Here, each ring has 256 entries. And each entry is 4
It is embodied in words (one word is 32 bits) and refers to one queued transmit data buffer for transmission. Typically, not all 255 transmit descriptor rings are used, and each ring is used as many as the required virtual channels. For example, a first transmission descriptor ring is used for an audio channel, a second transmission descriptor ring is used for a video channel, and a third transmission descriptor ring is used for TCP / IP.

In this case, each entry of the transmission descriptor ring is composed of four words. Where word 3
Indicates the tail of AAL5, word 2 indicates the 4-byte ATM head, word 1 indicates the buffer pointer indicating the start position of the transmission data buffer, and word 0 indicates the control field, packet length, buffer length, etc. . In more detail with respect to word 0, bit 31 of word 0 is set by the host when the packet for transmission is queued as an own bit so that the AAL processing unit is accessed, and when the transmission of the packet is completed. , Reset and allow host access. Bit 30 of word 0 represents the starting buffer when multiple buffers are used to transmit one packet, and bit 29 represents the last buffer. Bit 27 indicates the AAL type, bits 26 to 16 indicate the length of the packet, and bits 15 to 0 indicate the length of the buffer. At this time, the maximum size of the buffer is 64 Kbytes. Thus, the transmission descriptor represents a buffer in the host memory that has the packet to be transmitted.

The transmission data buffer stores data to be transmitted, and after the transmission preparation is completed, the AAL processing unit 21
The data stored in the transmission buffer is read and transmitted.

Referring to FIG. 3, the transmission complete ring has 25
It has six entries. Here, one entry is 1
One packet indicates that transmission has been completed, and each entry consists of four words. When the bit 31 of the word 0 of the four words is set to 1 as an own bit, the AAL processing unit 21 has the right to use it. That there is. Bits 30 through 8 of word 1 are not used, and bits 7 through 0 represent an index in the bandwidth allocation table.

The reception free buffering is composed of two rings for pointing to respective free buffers of different sizes, and each ring is composed of 256 entries. The host system 10 writes a pointer to an empty buffer in each ring, and determines the size of the buffer during the initialization process. For example, the two free bufferings are divided into a first free buffering and a second free buffering. Here, the first free buffering is used to refer to an 8K byte buffer for TCP / IP based applications, and the second free buffering is used to refer to a 48 byte buffer for CBR service. Can be used for Therefore, the virtual channel set for the CBR application uses the buffer indicated by the second free buffering, and the TCP / I
The virtual channel set for P application uses the buffer indicated by the first free buffering.

In this case, each free buffering entry consists of four words. Where bit 3 of word 0
"1" is set as an own bit when each free buffering entry is owned by the AAL processing unit 21, and reset when it is owned by the host system 10. Bits 30 through 28 are not used, and bits 27 through 0 represent the start pointer of the buffer. During the initialization process, the reception buffer is formed in units of 16 bytes up to a maximum length of 48 Kbytes and a maximum length of 64 Kbytes due to two free bufferings. Here, the size of the buffer specified by one free buffering is the same.

The reception completion ring has 256 entries, and each entry has 4 words. Where word 0
Is the control field, packet length, etc., word 1 is 2
Word 2 represents an 8-bit start buffer pointer, and word 2 represents a 4-byte ATM header. Bit 31 of word 0
Indicates that it is processed by the AAL processing unit 21 when it is set as an own bit, and indicates that it is processed by the host system 10 when it is reset. Bit 30 informs the host that a receive buffer overflow has occurred while processing the current packet as a packet overflow bit, and bit 29 informs the host that a CRC error has occurred in the AAL5 packet as a CRC condition bit. Bit 21 to bit 11
Indicates reception of a congested cell, and bits 10 to 0 indicate the length of the packet.

[0038] The receive complete ring also contains a pointer to the received packet present in the host memory to be processed. When receiving the interrupt, the host system 10 processes the entry whose own bit is reset after checking the reception completion ring.

On the other hand, as shown in FIG. 3, the control memory includes a bandwidth allocation table, a transmission DMA status table, and a reception DMA status table. Such a table is A
It can be accessed by the AL processing unit and the host.

The bandwidth allocation table has 4800 entries, each entry consisting of one byte. Transmission DMA
The status table consists of 255 DMA entries, each DMA entry consists of 8 words, and the receive DMA state table is used for reception and consists of 1024 DMA entries (each entry has 8 words).

The bandwidth allocation table allocates bandwidth for 255 transmit descriptor rings by allocating an index from 0 to 255 to each 8-bit entry. At this time, “0” indicates that an invalid cell is transmitted. Such a bandwidth allocation table is set during the initialization process. The bandwidth allocation table includes a pointer pointing to the transmission DMA status table, and the AAL processing unit 21 accesses the tables of the size determined in the initialization process in order, and indicates the transmission directory indicated by the index of the table. Transmits scripting data.

The transmit DMA status table comprises 255 bandwidth allocation DMA entries, each DMA entry having 8
Represents a transmit buffer composed of words and divided. DMA
Of the eight words constituting the entry, word 0, word 1, word 2, and word 7 are directly copied from the transmission descriptor ring. Here, word 0 indicates the control field, packet length, and buffer length, word 1 indicates the pointer of the current buffer, word 2 indicates the 4-byte ATM header, and word 7 indicates the AAL5 tail. Word 3 is an area programmed only by the host, bit 1 of word 3 is BWG
When the _ON bit is “1”, data is transmitted based on the bandwidth allocation table, and when the _ON bit is “0”,
No transmission data is transmitted, and a NULL cell is transmitted. In word 4, bits 31 to 12 are used as transmission descittering pointers to indicate the position of the current entry of the corresponding transmission descittering DVMA.
Address. Word 6 is CRC of AAL5 packet
This part is used for calculation.

The reception DMA status table is composed of 1024 reception DMA entries as a table used for reception, and each DMA entry is composed of 8 words. Bit 31 of word 0 is set when the DMA channel is activated, and bits 21 through 11 are E
xplicit Forward Congestio
Used for n Notification (EFCN) cell counter. Here, bits 10 to 0 indicate the length of the packet. Word 1 represents the current buffer pointer, word 2 represents the starting buffer pointer, and word 3 represents the length of the AAL packet. VC_O of word 4
The N bit is turned on during the reorganization of the packet, but if reset, the AAL processing unit 21 discards the received cell of the corresponding VC. The buffer type bit indicates whether the corresponding buffer belongs to the first free buffering or the second free buffering.

The fact that a packet is transmitted and received through such a data format will be specifically described.

The transmission buffer can be formed at an arbitrary position on the host memory, and its size is up to 64 Kbytes. When the packet to be transmitted from the host is prepared,
The ATM NIC 20 transmits the data included in each packet in order. The received packet is stored in one reception buffer in the host memory 11. At this time, the size of the buffer is indicated by two types, that is, the first free buffering or the second free buffering.

First, the data transmitted by the application program of the host is stored in the transmission data buffer, and the pointer of this buffer is recorded in the transmission descriptor ring to set the transmission descriptor ring. When the processing of the host for the packet interferes, the own bit of the corresponding input in the transmission descriptor ring is set and the processing of the corresponding packet is passed from the host system 10 to the AAL processing unit 21.

The AAL processing unit 21 processes the data stored in the transmission data buffer according to the transmission DMA status table indicated by the index of the entry of the bandwidth allocation table while circulating through the bandwidth allocation table in order. In this case, the corresponding entry data of the transmission descriptor ring is copied in the transmission DMA state table. Therefore, the AAL processing unit 21 reads and transmits 48-byte data from the transmission data buffer indicated by the pointer in the transmission DMA status table.

Subsequently, when a pay load of 48 bytes is transmitted, the AAL processing unit 21 updates the internal register, and then processes the entry in the transmission DMA status table indicated by the next entry in the bandwidth allocation table. As described above, the AAL processing unit 21 continuously transmits data according to the index of the table entry while circulating through the bandwidth allocation table, and returns to the transmission DMA state table being processed again without accessing the transmission descriptor ring. , Only the transmission DMA state table is accessed and processed. At this time, the transmission DMA status table has been updated to the pointer of the transmission data buffer indicating the cell to be transmitted next.

When the transmission to one transmission data buffer is completed by transmitting the data in this way, the AAL processing unit 21 copies the data of the next entry of the transmission descriptor ring to the entry of the transmission DMA status table, and Processing continues for two buffers. That is, one entry of the transmission descriptor ring points to one transmission data buffer, but when the packet to be transmitted supplies five buffers, five entries of the transmission descriptor ring are required to process the packet. Is required. In this case, if the first buffer does not end in 48-byte units and 16-byte data remains, AA
After the L processing unit 21 processes 16 bytes of the first buffer, the DMA status table is updated, and data of the remaining 32 bytes is read from the second buffer in units of 48 bytes.

When the processing of the last buffer forming one packet is completed and the transmission of the packet is completed, the end-off packet (EOP) is processed. For example, in the case of AAL5 type transmission, the EOP process fills the pads and forms the AAL5 tail.

When the transmission for one packet is completed, the AAL processing unit 21 clears the own bit of the transmission descriptor ring entry assigned to the packet and forms a transmission completion ring entry. An interrupt is generated in the host system 10. In this case, the own bit and the bandwidth allocation index are recorded in the transmission completion ring entry.
Here, the bandwidth allocation index is used to enable the host to re-use the memory of the processed packet.

On the other hand, in the receiving process, one DMA entry of the receiving DMA table is assigned by the 10-bit VCI of the received ATM cell. One DMA entry of the reception DMA table corresponds to one entry of the two reception free bufferings on a one-to-one basis.

If the received ATM cell is the corresponding VCIn
o If it is the first cell, the DMA entry indicates whether some free buffer is used to store the received cell. For example, DMA indicated by VCI
After determining whether the buffer allocated to the entry belongs to the first free buffering or the second free buffering, the first descriptor of the corresponding free buffering is accessed to set the address of the free buffer to the DMA entry. Copy to Then, the first received cell is stored in the buffer designated by the corresponding DMA entry.

Subsequently, when the next cell having the same VCI is received, 48 bytes are stored in the buffer specified by the DMA entry without accessing the reception free buffering. In this case, the DMA entry is updated and points to the next stored address.

If the VCI of the received ATM cell is still different from the VCI of the cell, after accessing the corresponding DMA entry, the start address of the free buffer is obtained from the reception free buffering, and the A
Stores a TM cell.

When the above operation is repeated and the reception of one packet is completed, the AAL processing unit 21 records this in the reception completion ring, generates an interrupt, and notifies the host system 10 of this. At this time, the own bit of the reception descriptor and the own bit of the reception completion ring entry are reset, and the authority is transferred to the host system 10.

Although the above-described ATM NIC has transmission and reception buffers in the host memory, such a transmission and reception buffer may be embodied in a memory inside the NIC, and control data for controlling transmission and reception may be transmitted. A great variety of formats can be used.

Subsequently, according to the above description, the ATM NI
After understanding the operation of C, an embodiment according to the present invention will be described in detail.

FIG. 4 is a schematic diagram showing a free buffer used for real-time connection according to the present invention, and a buffer indicated by the entry of the free buffering.

Referring to FIG. 4, each entry of the free buffering 43 used for real-time connection is managed by a tail pointer 41 and a head pointer 42, and the entries of the free buffering 43 are stored in the buffers 44-1 to 44-6. Has a starting address for In this case, the head pointer 42 points to the entry of the buffer in which the cell received first is stored, and the tail pointer 41 points to the entry of the buffer for storing the newly received cell.

In such a free buffering structure, when the values of the head pointer 42 and the tail pointer 41 match, an overflow occurs. On this occasion,
The value of the head pointer is incremented, the previously arrived cell is discarded, and the later received cell is stored at the address pointed to by the tail pointer. By separately managing the packet data for the real-time connection in the ring structure, when an overflow occurs in the reorganization buffer,
The less important, most time-delayed cells may be discarded to store cells received later.

FIG. 5 is a flowchart showing the flow of the operation according to the present invention. In the cell discarding method according to the present invention, as shown in FIG. 5, a step S100 of setting free buffering for a real-time connection constituted by an entry indicating a buffer of a cell stored by a head pointer and a tail pointer. And when the cell of the packet corresponding to the real-time connection is received, comparing the free buffering head pointer and the tail pointer for managing the real-time connection with step S1.
02, when the head pointer matches the tail pointer (that is, when the buffer does not overflow), the step S104 of storing the received cell in the buffer pointed to by the tail pointer, and when the head pointer does not match the tail pointer ( That is, when an overflow occurs in the buffer), the value of the head point is increased by 1, the longest cell is discarded, and the received cell is stored in the buffer pointed to by the tail pointer (step S).
103 and 104, and step S105 of increasing the tail pointer by one.

Referring to FIG. 5, during the setting process,
Once the real-time connection is set up, set up free buffering for this. Free buffering consists of a plurality of entries, each entry having the address of a free buffer. The free buffering entry is indicated by the head pointer and the tail pointer. Here, the head pointer points to the first entry, and the tail pointer points to an entry for storing the currently received cell while increasing in order. Therefore, when an entry such as a head pointer is pointed during the increase of the tail pointer, an overflow occurs.

If the tail pointer becomes the same as the head pointer and an overflow occurs, the head pointer is increased by one and the newly received cell is stored in the buffer pointed to by the entry specified by the tail pointer. . In this case, data stored in the buffer pointed to by the entry before the head pointer is increased is lost, and a newly received cell is stored.

If no overflow occurs, the received cell is stored in the buffer pointed to by the entry pointed to by the tail pointer, and then the tail pointer is incremented by one.

Although the preferred embodiments of the present invention have been described above, those skilled in the art will be able to make various modifications without departing from the scope of the present invention.

[0067]

Therefore, according to the present invention, free buffering for real-time connection is separately managed, and when an overflow occurs in a buffer, the longest cell is discarded and a newly received cell is stored. As a result, cells can be more efficiently discarded.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing a reference model of a normal ATM protocol.

FIG. 2 is a configuration diagram showing a normal ATM NIC.

FIG. 3 is a schematic diagram showing an example of a data format processed in FIG. 2;

FIG. 4 is a conceptual diagram illustrating a ring and a buffer for providing a real-time connection according to the present invention;

FIG. 5 is a flowchart illustrating discarding ATM cells according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Host system 11 Host memory 12 Processor 13 Bus control part 20 ATM NIC 21 AAL processing part 22 SONET / ATM line adapter 23 Transceiver 30 I / O bus 41 Tail pointer 42 Head pointer 43 Free buffering 44-1 to 44-6 Buffer

Claims (4)

[Claims] 1. An ATM network interface card (NI)
C) discarding the received cell in order to process the time-dependent data in the ATM NIC, wherein the ATMNIC transmits a message from the user under the control of the host system.
Converting the cells into cells suitable for TM-based communication, reconstructing the received cells stored in the data buffer pointed to by the free buffering entry and restoring the original message; An A step of setting up the free buffering, comprising a plurality of entries pointing to the data buffer using: a cell requiring a real-time service to the ATM NIC; A step B of comparing the value of the head pointer with the value of the tail pointer; and if the value of the head pointer does not match the value of the tail pointer, storing the received cell in a buffer pointed to by the tail pointer. Step C, the value of the head pointer and the tail pointer If the value of the pointer matches, the value of the head pointer is incremented by 1, the first received cell is discarded, and the last received cell is stored in a buffer pointed to by the tail pointer. E) increasing the value of the tail pointer by one. 2. When an overflow occurs in a buffer, a received cell is discarded in such a manner that a cell stored first is discarded in order to secure a space for storing a newly arriving cell. The method, wherein the buffer is a memory device that receives and stores sequentially input data, and the overflow is a condition in which the buffer is full and cannot accommodate any more input cells. Cell disposal method. 3. The method of claim 2, wherein the characteristics of the cell are defined by the ATM communication architecture. 4. The method according to claim 3, wherein the cell has information that requires real-time processing.