JPH07221762A - Packet processing method and communication interface device - Google Patents

Abstract

PURPOSE:To suppress the increase in a management memory by applying a list structure to a frame of an optional size or an optional number of fixed length data blocks and storing tentatively the data to a buffer divided into plural banks and processing the data so as to utilize effectively the buffer memory. CONSTITUTION:A recovery frame and logic channel information sent from a data unit generating section via a bus 3 is written in a buffer memory 102 in a transmission section 100, data are read corresponding to a channel designated by a traffic control section 150, a cell header processing section 110 adds a header and transfers the result to a bus 4. Then a buffer memory 102 is divided into plural banks each having plural data blocks of a fixed length packet, and when a frame length exceeds the bank capacity, the frame is allocated to the plural banks and a link processing circuit 120 applies list structure to the data blocks based on pointer information registered in a bank information table 141 to store a frame of an optional size or an optional number of fixed length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet processing method and a communication interface device, and more particularly to a connection interface with a network which handles ATM cells which are fixed length packets, and ATM cells and variable length frames (user data). The present invention relates to a packet processing (packet generation and frame assembly) method for mutual conversion with and.

[0002]

2. Description of the Related Art ATM (Asynchronous Tranfer Mode)
In the communication system, all information is transmitted / received in the form of fixed length packets called "cells" each consisting of a header of 5 bytes and an information field of 48 bytes. ATM
The network terminating device divides a variable-length frame (frame containing user data) received from the terminal device side into a plurality of fixed-length data blocks, attaches a header to each data block, and fixes a fixed-length packet (ATM). cell)
Sent to the ATM network side as
A function (adaptation function) for assembling the data portion of the ATM cell received from the network side into a variable length frame is required.

As a prior art relating to the adaption function, for example, a cell-to-frame conversion method is disclosed in Japanese Patent Laid-Open No. 3-126346, and a frame decomposing device is disclosed in Japanese Patent Application Laid-Open No. 3-141747. ", A frame-to-cell conversion method is known.

The "packet assembling method" disclosed in Japanese Patent Laid-Open No. 3-126346 proposes a configuration in which a buffer memory is allocated for each logical channel and an arriving cell is distributed to the buffer memory according to the logical channel. Also,
In order to effectively use the buffer memory, the buffer memory for frame assembly is configured by chaining a large number of memory units according to the data block length of each cell, and an empty buffer chain, an assembling buffer chain for each logical channel, and We have proposed a method of forming an assembled buffer chain and assembling received cells for each logical channel.

Further, in the "frame disassembling device" of Japanese Patent Laid-Open No. 3-141747, a plurality of input buffers are provided so that frames (user data) received from a host device can be stored in units of frame status information. Accordingly, a structure is proposed in which the frame data is read from each input buffer for each fixed block length to enable multiplex transmission of cells.

[0006]

However, in the above-mentioned conventional packet assembling method, the buffer memory is divided into a large number of memory units each having the maximum data block length of a cell,
Since the memory unit in which the cell data is written has a structure (list structure) for each logical channel,
A large number of memory units are required for assembling one frame, and a large capacity is required as a management memory for managing chain information between the memory units.

Further, in the above conventional frame disassembling apparatus,
Since each frame is input to one fixed-length input buffer, it is necessary to adjust the input buffer to the maximum expected user data length to handle arbitrary variable-length user data. is there. Therefore, when transmitting short user data, there is a problem in that the memory area of the input buffer is wasted and the memory utilization efficiency is poor.

An object of the present invention is to provide a packet processing method capable of effectively utilizing a buffer memory and suppressing an increase in the capacity of a management memory, and a communication interface device.

Another object of the present invention is to provide a packet processing method and a communication interface device capable of converting a frame into a packet or converting a packet into a frame at high speed.

Another object of the present invention is to provide a packet processing method and a communication interface device suitable for a device for multiplex communication using a plurality of logical channels.

Another object of the present invention is to provide a packet processing method and a communication interface device capable of transmitting packets by controlling the band for each logical channel.

[0012]

To achieve the above object, in a packet processing method and a communication interface device of the present invention, a buffer memory for temporarily storing a variable length frame to be packetized, or a variable length frame. The buffer memory for temporarily storing the data portion of the received packet for assembly is divided into a plurality of banks each having a capacity of a plurality of fixed-length packet data blocks, and one frame of data is stored. Is not able to be accommodated in one bank, a plurality of banks are allocated and these banks are structured into a list by pointer information.

The "variable length frame" referred to here is a length adjustment field for making the frame received by the communication interface from the network, the host computer or the terminal device an integral multiple of the fixed length packet data block. And a configuration in which an auxiliary field such as a control information field is added.

In packet processing in which a variable-length frame is divided into a plurality of fixed-length data blocks and a header is attached to each data block and transferred as fixed-length packets (cells), the size of the variable-length frame is the bank length. If the frame size is exceeded, the frame is divided into a plurality of list-structured banks according to the bank address and stored, and a fixed-length data block is read out in order from one of the single or a plurality of list-structured banks. Generate a packet.
The bank allocation in the buffer memory forms a list structure corresponding to the logical channels of the variable length frame.

When the band of the output packet is designated for each logical channel, the bank corresponding to each logical channel is accessed at a frequency determined based on the band information, and the header of the read data block is read. Is added to generate a packet. The band control, for example, prestores the correspondence relationship between the time slot of the output line and the bank designation information, and includes the data block read from the bank designated by the bank designation information in each time slot. Send a packet. If the continuous transmission amount of fixed-length packets and the maximum burst length allowed for the logical channel are specified, the fixed-length data block from the bank corresponding to each logical channel must be within the range in which the continuous transmission amount does not exceed the maximum burst length. Burst control can be performed by reading.

To store the frame data (or the one to which the auxiliary field is added) received from the host device or the frame network in the bank, for example, an empty address for designating the bank in the empty state is stored in the address buffer. Every time, the variable length frame is written while counting the data length to one bank specified by the address fetched from here, and whenever the accumulated data length reaches the bank length, the next empty address is fetched and a new bank is fetched. Is received, and a plurality of banks used in the same frame are associated with each other and stored in an address table, thereby coping with frame reception of an arbitrary length. With respect to the bank for which reading of all the data blocks for packetization has been completed, the addresses are registered in the empty address buffer to be released to other frames to be input thereafter.

In packet processing for receiving a fixed-length packet and assembling related packets, for example, a plurality of packets belonging to the same logical channel into a variable-length frame, there is an empty state for the first received packet of each frame. When a new bank is allocated and all the data block parts constituting the same frame cannot be accommodated in one bank, the data block part of the received packet is associated with the packet while allocating a new bank structured as a list by pointer information. When the last data block portion of each frame is stored in the bank, information indicating the completion of frame assembly is generated.

The correspondence between the received packet and the used bank is stored, for example, in a table in which the correspondence between the logical channel information and the bank address is stored, and when the packet is received, it is included in the header of the received packet from the table. To obtain the bank address corresponding to the logical channel information
The data block portion of the received packet is stored in the bank specified by the bank address.

The assembling completion information is, for example, a bank address and is registered in the completion address buffer. The bank addresses registered in the completion address buffer are sequentially taken out, and the contents of the assembled frame are read from one bank specified by the bank address. When one frame is divided and accommodated in a plurality of banks having a list structure, the subsequent bank is specified by the bank address stored as pointer information, and the remaining data is read.

[0020]

According to the present invention, the buffer is divided into a plurality of banks, each bank is set to a size capable of storing a data block of a plurality of packets, and when one bank cannot accommodate one frame of data, a plurality of banks are provided. Since banks are assigned and the banks are structured into a list, a frame of an arbitrary length or an arbitrary number of packets forming one frame can be received and processed. In this case, by properly designing the size of each bank, it is possible to reduce the waste of the memory area occupied by a specific frame without storing data. In addition, since one bank has a size capable of storing a data block of a plurality of packets, the list structure can be reduced compared to the case where the list structure is formed in a memory area unit having a data block size of one packet. It is possible to reduce the memory area required for managing the link information or the pointer information.

[0021]

Embodiments of a packet processing method and a communication interface device according to the present invention will be described below in detail with reference to the drawings. In the following embodiment, the packet processing using the bank having the list structure according to the present invention is applied to the adaptation processing unit 1.

In the system configuration shown in FIGS. 2 to 4,
The adaptation processing unit 1 receives a frame received via a transmission line or a bus 2 as a fixed-length packet (hereinafter referred to as A
It is converted to a TM cell) and the generated ATM cell is sent to the transmission line or the bus 4. Also, the ATM cells received via the transmission line or bus 5 are converted into variable length frames, and the variable length frames are sent to the transmission line or bus 7.

FIG. 2 shows a system configuration in which the adaptation processing unit 1 is applied to an ATM interface 50 for connecting a terminal device to an ATM network. Here, the terminal device includes a processor 51, a memory 52, and a processor bus 53, and the ATM interface 50 is
The processor bus 53 via the bus controller 54
, And is connected to the ATM network through an ATM-IF 55 or the like having a function as an ATM network line termination.

When the communication information (user data) to be transmitted to the ATM network is generated, the processor 51 stores a frame which is the communication information in the memory 52 and issues a transfer request to the ATM interface 50. When the adaptation processing unit 1 receives a transfer request from the processor 51, it reads a frame from the memory 52, temporarily stores it in an internal buffer memory, converts it into an ATM cell, and transmits it to the ATM network. Also, from the ATM network to ATM
When the cell is received, it is stored in the internal buffer memory, and when the frame assembly is completed, the transfer request is issued to the processor 51 via the bus controller 54,
A frame transfer operation to the memory 52 is performed. Note that the adaptation processing unit 1 can be connected to the terminal device by using a FIFO type communication buffer or a dual port memory instead of the bus controller 54.

FIG. 3 shows a system configuration when the adaptation processing unit 1 is applied to a terminal adapter which performs mutual conversion between a frame and an ATM cell between a frame network and an ATM network. The adaptation processing unit 1
It is connected to the frame network line through the frame processing unit 61 that fulfills the frame network line termination function, and is connected to the ATM network through the ATM-IF 55.

FIG. 4 shows a system configuration when the adaptation processing unit 1 is applied to a multiplexer for multiplexing and connecting a plurality of frame network lines to an ATM network line. The adaptation processing unit 1 is provided for each frame network and is connected between the frame processing unit 71 and the multiplexing circuit 72.

FIG. 5 is a block diagram schematically showing the configuration of the adaptation processing unit 1. PDU creation unit 30
Is a data unit (CPCS-PDU) having a length which is an integral multiple of the data block of the ATM cell by adding a PAD for adjusting the data length described later and a trailer of a fixed length to the frame received from the bus 2. Create a bus 3
To the cell transmission unit 100 via. Cell transmitter 100
Divides the CPCS-PDU into a plurality of fixed-length data blocks, adds a cell header to each data block, and
It is converted into a TM cell and transmitted to the bus 4.

The cell receiving section 200 assembles a reproduction frame (correctly, CPCS-PDU) from the data block extracted from the ATM cell received from the bus 5, and passes it to the frame normality checking section 40 via the bus 6. . The frame normality checking unit 40 confirms the normality of the frame by using the check code included in the trailer of the reproduced frame, and then transfers the frame unit excluding the PAD and the fixed length trailer to the bus 7.

FIG. 6 is a block diagram showing the configuration of the PDU creating unit 30. The PDU creating unit 30 receives a frame from the bus 2-1 which is a part of the bus 2, and calculates a check code CRC, a CRC calculating unit 31, a PAD length and a CPCS to be inserted for adjusting the length of the frame. -P
The length / PAD calculation unit 32 for calculating the length of the DU and the trailer addition unit 33 for inserting the PAD and adding the trailer after the frame are provided, and the length is an integer multiple of the ATM cell data block. The data unit CPCS-PDU having the same is transferred to the cell transmission unit 100. At this time, information indicating the total length of the CPCS-PDU is calculated by the calculation unit 32.
To the cell transmission unit 100 via the bus 3-2. The bus 2-2 which is a part of the bus 2 is for notifying the logical channel information of the frame, and the logical channel information is transferred from the PDU creating unit 30 to the cell transmitting unit 100 via the bus 3-3. To be done.

FIG. 7 is a block diagram showing the structure of the frame normality check unit 40 shown in FIG. The frame normality check 40 includes a CRC calculation unit 41 that calculates a CRC of the CPCS-PDU received via the bus 6-1 that is a part of the bus 6, a CRC calculation result, and a CRC field of the CPCS-PDU trailer. The cell receiving unit 200 is connected via the CRC check 42 for comparing the CRC value set in the cell 6 and the bus 6-2 forming a part of the bus 6.
CPCS-PDU full length value and CPCS-
Len for checking the length of the received frame from the value set in the Length field in the PDU trailer
a gth check unit 43, an error signal generation unit 44 that receives a notification from the CRC check 42 and the Length check unit 43 when an error occurs, and outputs an error signal to the bus 7-2 when there is any error notification. CRC
Remove the PAD 19 and trailer 20 from the CPCS-PDU received from the calculator, and connect the frame 18 to the bus 7-1.
And a trailer removing unit 45 for outputting to.

FIG. 8 shows an example of a frame handled by the adaptation processing section, which is "AAL" defined in ITU.
5 shows a frame structure applied to an adaptation method called "5". However, the present invention can also be applied to other adaptation methods than AAL5.

As shown in FIG. 8A, the frame 18
By adding a PAD (Padding) 19 and a trailer 20 to the cell data block 12 (12A to 12A).
A CPCS-PDU 17 having a length that is an integral multiple of N) is obtained. ATM cells 10A to 10N are generated by dividing the CPCS-PDU 17 into data blocks (SAR-PDU) 12A to 12N by 48 bytes and adding a cell header 11 to each block. CPC
Last data block of S-PDU17 (SAR-PD
A header 11 including flag information for indicating the end of the frame is added to (U) 12N.

FIG. 8B shows the detailed structure of the trailer section of the CPCS-PDU17. CPCS-PDU17 is
Frame 18 and PAD field 1 of 0 to 47 bytes for making CPCS-PDU length an integral multiple of 48 bytes
9 and 8 bytes of CPCS-PDU trailer 20. The CPCS-PDU trailer 20 has a 1-byte CPCS-UU (CPCS User-) used by the CPCS user.
to-UserIndication) field 21 and trailer 6
1-byte CP inserted to make it a multiple of 4 bits
An I (Common Part Indicator) field 22, a 2-byte Length field 23 indicating the length of the frame 18, and a 4-byte CRC check field 24 are included.

FIG. 9 shows the format of an ATM cell. Each cell 10 is composed of a 5-byte cell header 11 and a 48-byte information field 12, and is a fixed-length packet having a total length of 53 bytes.

The cell header 11 has a 12-bit VPI (V
irtual Path Identifier) and 16-bit VCI (Virt
Logical channel field 13 including the ual channel identifier) and 3-bit PT (Payload) indicating the cell type.
Type) field 14, a 1-bit CLP (Cell Loss Priority) field 15 indicating a cell loss priority rate,
8-bit HEC (HeaderEr) for detecting cell header abnormality
ror Check) field 16.

It should be noted that, in a cell including data blocks divided from the same frame in the information field 12, the same value (VPI +) is set in the logical channel field 13.
VCI) is given. Further, in the cell including the last data block of the CPCS-PDU 17, the lower 1 bit of the PT field 14 of the header becomes "1".

FIG. 1 shows an example of a detailed configuration of the cell transmitting section 100 shown in FIG. The cell transmission unit 100 receives the CPCS-PDU 17, the total length of the CPCS-PDU 17, and the logical channel information from the PDU creation unit 30 via the bus 3-1, the bus 3-2, and the bus 3-3. CP
The CS-PDU 17 is once latched by the latch 101 and then written in the buffer memory 102.

The buffer memory 102 is composed of a plurality of banks having a memory capacity of a plurality of cells as described later,
Depending on the length of the CPCS-PDU 17, one or a plurality of banks having a list structure may be input PCS-PDUs.
Assigned to.

Cell transmission is performed according to the logical channel number designated by the traffic control unit 150. That is,
Of the plurality of banks of the buffer memory 102, the bank belonging to the list structure corresponding to the logical channel number designated by the traffic control unit 150 is accessed, the data block (SAR-PDU 12) is read, and the cell header processing unit 110 is read into this. The cell obtained by adding the cell header 11 is transferred to the bus 4.

The write control circuit 103 and the read control circuit 104 respectively generate data (CPCS-PDU1) to the buffer memory while generating the in-bank address.
7) writing and data from the buffer memory (SA
The R-PDU12) is read.

The link processing circuit 120 and the delink processing circuit 130 respectively register a table of pointer information (bank addresses) for linking a plurality of banks in the buffer memory 102 and delink an unnecessary bank. Release the pointer information of. 1
A buffer management table memory 40 stores a bank information table 141 for storing management information of accumulated data corresponding to banks, an empty bank FIFO 142 for accumulating addresses of empty banks, and a plurality of banks forming a list structure. First link table (table 1) 14 for storing pointer information (bank address) for linking
3 and a second link table (table 2) 144. The timing circuit 160 generates timing signals for write processing and read processing.

FIG. 10 and FIG. 11 are explanatory views of the data writing process to the buffer memory 102 performed by the cell transmitting unit 100. The buffer memory 102 is composed of a plurality of fixed-length banks 124, and the length of each bank is LTmax.
In the first link table 143, the bank number (bank address) WB1 to be written is associated with the logical channel.
43a and a bank number (bank address) RB143b to be read are stored. The second link table 144 has, for each bank, a control flag 144b relating to the frame data accumulated in the bank and a bank number NB indicating the next bank linked to the bank.
144a are stored. Bank information table 141
Stores a length (LT) 141a of data accumulated in the bank and a pointer (RP) 141b indicating a read data block in the bank corresponding to the bank.

FIG. 10 shows a data unit (CPCS-P).
An example of the writing process when the total length TL of DU) is equal to or less than the bank length TLmax will be shown. When the logical channel information is received from the bus 3-3, the first link table 143 is accessed using this as the address [A], and the write bank address (WB) 143a-A corresponding to the address [A] is read. The address WB has been fetched from the empty bank FIFO 142 in advance, so that the C received via the bus 3-1 in order from the head of the i-th empty bank.
PCS-PDU17 is written.

As in this example, the total length TL of the CPCS-PDU 17 received from the bus 3-2 is the bank length LTmax.
If less than 124, one CPCS in i-th bank
-The length LTi (= TL) of the data stored in this bank, which has finished writing the PDU 17, is the bank information table 1
41 is written in the i-th LT area 141a-i,
A bit “1” indicating the end of one CPCS-PDU 17 is set in the i-th flag Fg area 144b-i of the second link table 144. Also, empty bank FIF
A new bank address j is read from O142 and written as link information in the i-th NB area 144a-i of the second link table. At this time, the bank address j is registered in the WB area 143a-A at the address [A] of the first link table 143 so that the next CPCS-PDU 17 having the same logical channel information can be stored in the jth bank. I will do it.

FIG. 11 shows the CPCS-PDU to be written.
An example of the writing process when the total length TL 17 is longer than the bank length LTmax124 is shown. In this case, the front part of the data CPCS-PDU 17 is stored in the i-th bank according to the bank address WB read from the first link table 143. The length LTi (= bank length LTmax) of the stored data is the i-th L of the bank information table 141.
The data is written in the T area 141a-i, and the bit "0" indicating that the following data exists in the i-th Fg area 144b-i of the second link table 144 is set.
Furthermore, the empty bank address j fetched from the empty bank FIFO 142 is the i-th Nth address of the second link table 144.
B area 144a-i stores as link information, and C
The remaining data of the PCS-PDU 17 is written from the beginning of the j-th empty bank designated by the empty bank address j.

When the remaining data length is longer than the bank length LTmax, the above operation is repeated and a plurality of banks are linked one after another. When the writing of the last data portion of the CPCS-PDU17 is completed, as in the case of FIG.
One CPCS-P in the flag Fg area 144b-j
A bit "1" indicating the end of DU17 is set, and a new bank address k is read from the empty bank FIFO 142, which is the jth NB area 144a-j of the second link table and the WB of the first link table 143. It is registered in the area 143a-A.

As described above, in the writing process of the cell transmission unit 100, a bank is secured for each CPCS-PDU 17, and when the length of the CPCS-PDU 17 exceeds the bank length LTmax, a plurality of banks are listed by link information. Data is stored while being structured. In the above embodiment, the empty bank is reserved before the CPCS-PDU 17 arrives, but the CPCS-PDU is used.
A new empty bank may be secured when 17 arrives. In this case, the time required to secure the bank is given by the delay in the latch 101.

New CPCS-PDU1 given next
If 7 has the same logical channel number as the previous one, the data is written in such a manner that the list structure of the bank is extended. In the case of having a new logical number, data is written in such a manner that a new bank list is generated, and a plurality of frames (C
(PCS-PDU) is stored. Note that, by the data reading process described later, the banks for which the data reading has been completed are released one after another as empty banks, so there is no shortage of memory.

Next, with reference to FIGS. 12 to 14, the process of reading a data block from the buffer memory performed by the cell transmission unit 100 will be described.

When the logical channel number [A] is designated, the first link table is accessed using this as an address, and the read bank number (bank address RB) 143b-A corresponding to the channel number [A] is read.
If the bank address is i, the bank information table 14
The pointer PBi is read from the i-th read pointer area 141b-i of 1, and the data block 12a is read from the storage position indicated by the pointer value (internal address) RPi in the i-th bank. As shown in FIG. 12, when there is still a data block in the bank at the time when one data block has been read (R
For P'i <LTi), the value of the RP area 141b-i in the bank information table is updated to the value RP'i of the next internal address. FIG. 13 shows the operation when the data block at the last internal address position of one bank is read. When the reading of the data block (SAR-PDU) 12b is finished, the value R of the read pointer after the update
When P′i reaches the in-bank data length LTi indicated by the LT area 141a-i, the content Fg of the flag area 144b-i of the second link table 144 is checked.
If Fg continues to indicate the existence of data (Fg
= "0"), the value j of NB is read from the i-th next bank number area 144a-i of the second link table, and this is written in the read bank number area 143b-A of the first link table 143 to write the data. The address of the bank i for which reading has been completed is registered in the empty bank FIFO 142.

FIG. 14 shows the operation when the last data block SAR-PDU 12c of the CPCS-PDU is read. After reading the data block, the value RP′i of the bank internal address is set to L in the bank information table 141.
When the in-bank data length LTi indicated by the T area 141a-i is reached, if the flag area 144b-i of the second link table 144 is Fg = “1”, the cell header 11 indicating the last cell is set. SAR-PDU12c
Added to. After that, as in the case of FIG. 13, the NB value j of the next bank number area 144b-i is read and written in the bank number area 143b-A of the first link table 143, and the address i of the bank for which all the data reading has been completed. Are registered in the empty bank FIFO 142.

As described above, in the read process of the cell transmitter 100, the list bank formed by the write process is accessed corresponding to the logical channel to read the cell. In the above embodiment, the first link table 143, the second link table 144, and the bank information table 141 have been described as being separate, but they may be configured by physically dividing the area in the same memory. . Further, an area for each of the above tables may be prepared in the buffer memory 102.

FIG. 15 shows an example of a concrete circuit configuration of the cell transmitting section 100 which executes the above-mentioned functions. The selectors 161, 162, 163 are for switching at the timing of the writing process and the reading process. Bus 3
When the logical channel information is received via -3, the first link table 1 uses this logical channel information as an address.
43, the bank address WB is read from the write bank number area 143a and the write address (W
A) It is given to the generation circuit 103. At this time, the bank address WB read from the first link table 143 is latched in the latch 122.

The WA generation circuit 103 includes the buffer memory 1
02, the internal address in the bank area designated by the bank address WB is generated, and the data (CP) input from the bus 3-1 and latched in the latch 101 is generated.
CS-PDU17) is sequentially written into the bank. The WA generation circuit 103 generates a data length L in parallel with data writing.
Count T. The value of LT is compared with the bank length LTmax 124 in the comparison circuit 123, and compared with the total length of the CPCS-PDU 17 received from the bus 3-2 in the comparison circuit 126.

When the total length matches LT, the comparison circuit 1
A stop signal is output from 26 to instruct the WA generation circuit 103 to stop writing. At this time, the bank information table 1
The data length LT141a in the bank is stored in 41.
Also, in order to secure the next bank, an empty bank FIFO
The Read signal is given to 142, and the address of the empty bank is read. The bank address is stored in the WB area 143a of the first link table 143 and the NB area 144a of the second link table 144. Also,
Bit "1" is set in the Fg area 144b.

When LT reaches LTmax, the data length (= LTmax) in the bank is written in the LT area 141a, and the empty bank FIF is set in order to secure the next bank.
The Read signal 127 is provided to the O142. The read empty bank address is stored in the NB area 144a corresponding to the previous write bank number in the second link table, and the bank is linked by this. Further, the empty bank address is notified to the WA generation circuit 103 (121), and the writing of the remaining data is continued in the bank designated thereby. Each time the bank is switched, the remaining data length (128) obtained by subtracting LTmax from the total length of the data (CPCS-PDU17) is compared with the in-bank data length LT (126), and the remaining data length is L.
The data writing process is repeated until it matches T.

The data block is read from the buffer memory 102 for each time slot generated by the transmission time slot generation circuit 151. The band control table 152 stores the relationship between the time slot and the logical channel number, and when the time slot is generated, the corresponding logical channel number is read. The cell header 11 is read from the header table 105 corresponding to the logical channel number. Further, the RB is read from the area 143b of the first link table, and the area 141b corresponding to the RB of the bank information table 141 is read.
To RP, and the start address of the read data block in the bank is obtained.

At the same time, the in-bank data length LT14
1a is read and the value obtained by subtracting 48 bytes from this is RP.
It is compared 132 with 141b. If they match, it means that all the data in the bank has been read out, the Write signal is given to the empty bank FIFO 142, and the empty bank F is used as the empty bank address.
Return to IFO. Further, the next bank number NB144a is read from the second link table 144 and registered in the RB143b of the first link table 143 (134). If F
When g = "1", it means the final cell, and the final cell signal is given to the cell header generation circuit 111 to generate the final cell header. Then, the cell header adding circuit 112 is caused to output the cell header 11 generated by the cell header generating circuit 111, and subsequently, the 48-byte data read from the buffer memory 102 is outputted. If it is not the last cell, the read pointer is written in the RP 141b of the bank information table 141.

As a modification of the above embodiment, the number of cells that can be continuously output for each logical channel (maximum allowable burst value)
May be stored in a table, the number of continuous outputs may be counted by a counter corresponding to the logical channel each time a cell is generated, and output control may be performed so that this does not exceed the allowable burst value.

FIG. 16 is a block diagram showing an example of the configuration of the cell receiving section 200. The cell receiving unit 200 uses the bus 5
When the cell 10 is received via the cell header processing unit 21
The cell header 11 is separated by 0, the SAR-PDU 12 is once latched by the latch 201, and then the buffer memory 20
Write to 2. Frame assembled (CPCS-
The PDU 17) is transferred to the frame normality check 40 via the bus 6-1. At this time, CPC on the bus 6-2
The length of S-PDU17 is output.

The write control circuit 203 and the read control circuit 204 are circuits for generating write / read addresses of the buffer memory 202. Buffer memory 20
Reference numeral 2 divides and manages into fixed length banks, and link processing 220 and delink processing 230 are for performing link processing for forming a bank into a list structure and delink processing for releasing an empty bank.

The buffer management table 240 for managing the buffer includes a bank information table 241 for storing information in the bank, an empty bank FIFO 242 for accumulating addresses of empty banks, and a bank for which frame assembly is completed. Completion bank FIFO 24 for specifying
3 and a first link table 244 and a second link table 245 that store information for linking a plurality of related banks. Timing circuit 250
Is for generating the timing of the writing process and the reading process.

17 to 19 are diagrams for explaining the writing process to the buffer memory 202 in the cell receiving section 200.

The buffer memory 202 is composed of a plurality of fixed length banks, and the length of each bank is LTmax2.
22. The first link table 244 uses a logical channel information as an address to access a storage area,
A write bank number (bank address WB) 244a and a read bank number (bank address RB) 244b are stored.

The second link table 245 has a bank address (NB) 245a indicating the next bank listed.
And the flag 245b for each bank, and the bank information table 241 is for storing the write address (pointer WP) 241 in each bank for each bank.

In the writing process, as shown in FIG. 17, the logical channel number [A] of the cell received via the bus 5 is read, and the writing corresponding to the channel number [A] is written from the first link table 143. Bank number W
B: Read 244b-A. When receiving the first cell in the new logical channel, the empty bank FIFO 24
It is assumed that the bank number extracted from 2 is already set in the first table.

Now, assuming that the bank number is i, the in-bank write pointer WP241-i corresponding to the bank i is obtained from the bank information table 241, and the received cell of the received cell is stored at the storage position indicated by the write pointer value WPi of the bank i. The data part (data block: SAR-PDU 12d) is written.

As shown in FIG. 17, one data block S
At the time when the AR-PDU 12d has been written, if there is a free space in the bank (WP'i <LT), WP24
Update the value of 1-i to WP'i.

As shown in FIG. 18, when the pointer value WP'i reaches the bank length LTmax at the time when one data block (SAR-PDU 12b) is written and the value of the write pointer is updated, the reception cell Is not the final cell, the flag (Fg) 2 of the second link table 245
A bit "0" is set in 45b-i to indicate that there is a subsequent data block in the same frame. Further, a new empty bank address j is fetched from the empty bank FIFO 242, the NB value j is written in the i-th next bank number area 245a-i of the second link table, and the j-th bank is linked to the i-th bank. The bank number j is registered in the write bank number area 244a-A of the first link table 244 so that the cell arriving next to the same logical channel can be written in the jth bank.

As shown in FIG. 19, one frame (C
Final data block (SAR) of PCS-PDU17)
-When the cell of PDU12f) is received, CPCS-
Flag Fg of bank i to indicate the end of PDU17
Set the bit "1" to. In addition, the frame (CPCS
The first link table 2 in the completion bank FIFO 243 to indicate that the assembly of the PDU 17) is complete.
The read bank number RB244b-A of 44 is registered. At this time, the next empty bank address j is taken out from the empty bank FIFO 242, and this is taken out by the first link table 24.
4 WB area 244a-A and RB area 244b-A
In this case, a bank for assembling another frame (CPCS-PDU) belonging to the same logical channel number A to be received next is reserved.

As described above, in the writing process in the cell receiving section 200, the data block SAR-PDU 12 is sequentially written in the bank secured for each logical channel, and when the frame exceeds the bank length, the newly acquired bank is obtained. Link, write a data block of subsequent cells to this new bank, and receive the last cell,
The head bank number of the CPCS-PDU 17 is stored in the completion bank FIFO 243 (= read bank number RB244b).
By registering, it becomes possible to assemble a frame of arbitrary length. Banks that have become vacant are released one after another by the frame reading process described later, so there is no shortage of banks.

In this embodiment, the first cell 1 of the next frame
Although the method of securing an empty bank before the arrival of 0 is adopted, the bank may be secured when the leading cell 10 arrives. In this case, the time required to secure the bank is
This can be secured by the delay time in the latch 201.

Next, referring to FIGS. 20 and 21, the assembled frame (CPCS-PDU) from the buffer memory is
The reading process of 17) will be described.

As shown in FIG. 20, the completion bank FIFO
The bank number i is read from 243, and the data from the head of the bank specified by this to the pointer position indicated by WP 241-i of the bank information table 241 is read. The read data is transferred to the frame normality check 40 via the bus 6-1. When the data read from one bank is completed, the bank number i is set to the empty bank FIFO in order to release the used bank.
Register at 242.

Next, the flag Fg245b-i of the second link table 245 is checked, and if the bit "1" is set, one frame (CP
Since CS-PDU17) has been completed, CPCS-P
The DU length TL (= WPi) is notified to the frame normality check 40 via the bus 6-2. After that, the next bank number j is read from the completion bank FIFO 243, and the data read from the buffer memory and the transfer operation for another CPCS-PDU 17 are repeated.

FIG. 21 shows a reading process when one frame is divided into a plurality of banks and stored.
When data has been read from the i-th bank based on the bank number i obtained from the completion bank FIFO 243, the flag Fg of the second link table corresponding to the bank number i
When the bit "0" is set in the area 245b-i, it can be seen that the following data exists.

In this case, the number j of the bank in which the data to be read next is stored is read from the NB area 245a-i of the second link table, the jth bank is accessed, and the data up to the pointer position indicated by WP241-j is read. Read out. If the flag Fg245 of the second link table
If b-i is "1", the total length TL of the CPCS-PDU is calculated by adding the value WPi accumulated in WP241-i and the value WPj accumulated in WP241-j, Output to 6-2. By repeating such a procedure, it is possible to read out the long CPCS-PDU 17 extending over an arbitrary number of banks.

In the above description, the first link table 24
4, second link table 245, bank information table 2
Although 41 has been described as being separate, these may be configured by physically dividing the area on the same memory. Also,
It is also possible to use the area provided in the buffer memory 202.

FIG. 22 shows an example of a concrete circuit configuration of the cell receiving section 200. The selectors 251 and 252 are for alternately switching the timing of the writing process and the reading process.

When the cell 10 is received via the bus 5, the cell header separation circuit 211 separates the cell header 11,
The T field is sent to the final cell signal generation circuit 213, and V
The PI / VCI field is sent to the header conversion circuit 212. The SAR-PDU 12 from which the cell header is separated is once latched in the latch 201.

The header conversion circuit 212 uses the separated VP.
The I / VCI 17 is converted into logical channel information and used as the address of the first link table 244. The write bank number WB244a corresponding to the logical channel is read from the first link table 244. The bank information table 241 is accessed using this bank number as an address, and the in-bank write pointer WP is read. Further, the write address (WA) generation circuit 203 generates a write address in the bank having the bank number, and the latched SAR-PDU 12 is accumulated in a predetermined bank in the buffer memory 202. The write pointer WP of the bank information table 241 is updated every time one cell is received.

When the value of "WP + 48 bytes" (221) matches the bank length LTmax 222 (223), it means that the bank is full of data. In this case, the write pointer WP is added to the bank information table 241.
After storing, the Read signal generation circuit 22 generates a Read signal to read the next empty bank number from the empty bank FIFO 242. Then, the next bank number NB area 245a of the second link table and the write bank number W
Register the above-mentioned empty bank number in the B area 244a and use the same C
Subsequent SAR-PDU 12 belonging to PCS-PDU 17
Reserve a bank to store.

P separated by the cell header separation circuit 211
If T indicates the final cell, a final cell signal is generated (213). In the case of the last cell, a bit “1” is set in the flag Fg area 245b of the second link table 245, indicating that the last data block of the CPCS-PDU 17 is included. In addition, the completion bank FIFO 243 W
A write signal is given and the read bank number RB244b of the first link table 244 is set to the completion bank FIFO24.
Write to 3 (243). After that, the read signal generation circuit 224 generates a read signal for the empty bank FIFO 242, the next empty bank number is taken out from the empty bank FIFO 242, and this is read out as the WB of the first link table 244.
Register in area 244a.

Reading of the assembled CPCS-PDU 17 from the buffer memory 202 is performed as follows.

When the completion bank FIFO 243 is not empty, the Read signal generating circuit 23 generates a read signal using the empty signal of the completion bank FIFO 243. As a result, the bank number is read from the completion bank FIFO 243, and the RA generation circuit 204 is provided with the bank number. The RA generation circuit 204 generates a read address in the bank having the bank number, reads the data from the buffer memory 202, and transfers the data to the frame normality check 40 via the bus 6-1. At this time, the read address and the write pointer 241 are compared (234), and if they match, an empty bank FI
The write signal is given to the FO242, and the bank number of the bank that has become empty after the reading is completed is set to the empty bank FIFO24.
Register with. Flag Fg of second link table 245
When the bit “0” is set in 245b, the next bank number NB area 245a of the second link table 245 is read and given to the RA generation circuit 204. by this,
The remaining data is read from the subsequent bank. If the flag bit is set to "1" (235), the Read signal generation circuit 231 reads the next bank number of the completed bank FIFO 243 and repeats the series of read processing described above.

Each time a new bank is read, each WP 24
The value of 1 is added by the adder 233 and one CPCS-
Each time PDU 17 is transferred, the full length data is transferred to bus 6
2 to the Laem sanity check.

[0087]

As described above, according to the present invention,
The buffer memory for temporarily storing the frame to be packetized or the fixed-length data block portion of the received packet is divided into a plurality of fixed-length banks, and each bank is set to the size of a plurality of data blocks. By linking a plurality of banks for each channel at any time, an arbitrary size frame or an arbitrary number of fixed length data blocks can be stored. According to the present invention, the buffer memory and the memory area for link information management can be effectively used, and the packet processing of a plurality of logical channels, the packet multiplexing processing, and the band control can be easily performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a cell transmission unit according to the present invention having a function of packetizing a frame.

FIG. 2 is a system configuration diagram showing an application example of a communication interface according to the present invention to a computer.

FIG. 3 is a system configuration diagram showing an application example of a communication interface according to the present invention to an inter-network connecting device.

FIG. 4 is a system configuration diagram showing an application example of a communication interface according to the present invention to a multiplexing device.

FIG. 5 is a diagram showing a configuration of an adaptation processing unit 1.

6 is a diagram showing a configuration of a PDU creating unit 30 in FIG.

7 is a diagram showing a configuration of a frame normality check unit 40 in FIG.

FIG. 8 is a diagram showing a relationship between a structure of a frame targeted for packet processing and a packet.

FIG. 9 is a diagram showing the structure of a fixed length packet (ATM cell).

FIG. 10 is a diagram for explaining a process of storing frame data in the buffer memory when the frame is shorter than the bank length.

FIG. 11 is a diagram illustrating a process of storing frame data in a buffer memory when the frame exceeds the bank length.

FIG. 12 is a diagram for explaining a process of reading a data block from the buffer memory when the frame is shorter than the bank length.

FIG. 13 is a diagram for explaining a process of reading a data block from the buffer memory when the frame exceeds the bank length.

FIG. 14 is a diagram for explaining a process of reading a frame last data block from a buffer memory.

FIG. 15 is a configuration diagram showing an example of a detailed configuration of a cell transmission unit.

FIG. 16 is a block diagram showing an embodiment of a cell receiving unit according to the present invention having a function of assembling received packets into frames.

FIG. 17 is a diagram for explaining a process of storing a packet data block in the buffer memory when the assembled frame is shorter than the bank length.

FIG. 18 is a diagram for explaining a process of storing a packet data block in a buffer memory when the assembled frame exceeds the bank length.

FIG. 19 is a diagram for explaining a process of storing a packet data block at the end of a frame in a buffer memory.

FIG. 20 is a diagram for explaining a process of reading frame data from the buffer memory when the assembled frame is shorter than the bank length.

FIG. 21 is a diagram for explaining a process of reading frame data from the buffer memory when the assembled frame exceeds the bank length.

FIG. 22 is a diagram showing an example of a detailed configuration of a cell reception unit.

[Explanation of symbols]

1 ... Adaptation processing unit, 50 ... ATM interface, 100 ... Cell transmitting unit, 200 ... Cell receiving unit, 1
02, 202 ... Buffer memory, 103, 203 ... Write control unit, 104, 204 ... Read control unit, 14
0, 240 ... Buffer management table, 142 ... Empty bank FIFO.

Claims (22)

[Claims] 1. A packet processing method for dividing a variable-length frame into a plurality of fixed-length data blocks, attaching a header to each data block, and transferring the fixed-length packets, wherein the variable-length frame is temporarily stored. If multiple banks of a specified length with a capacity of multiple blocks are defined for each buffer memory and the received variable-length frame cannot be accommodated in one bank, a plurality of lists structured by pointer information The packet processing method is characterized in that a fixed-length data block is sequentially read from one of a plurality of banks having a single structure or a list structure, and the packet is generated. 2. The packet processing method according to claim 1, wherein a plurality of list structures are formed in the buffer memory in correspondence with the logical channel information of the received variable length frame. 3. Bandwidth information of an output packet is stored in advance for each logical channel, and a bank corresponding to each logical channel is accessed at a frequency determined based on the bandwidth information to generate a packet. The packet processing method according to claim 2. 4. A correspondence relationship between a time slot of an output line and bank designation information is stored in advance, and a data block read from a bank designated by the bank designation information is packetized in each time slot. The packet processing method according to claim 1, wherein: 5. A vacant address for designating a vacant bank in the buffer memory is stored, and a variable-length frame is counted for one vacant bank while counting the accumulated data length. Each time the write / stored data length reaches the bank length, a new bank is acquired based on the next empty address, and the addresses of multiple banks used in the same frame are stored in association with each other. Claim 1
~ The packet processing method according to claim 4. 6. An empty address for designating an empty bank in the buffer memory is stored in an address buffer, and the used bank is specified by empty addresses sequentially taken from the address buffer to specify the used bank Is stored in the buffer, and the address of the bank for which reading of all fixed-length data blocks for packetization has been completed is registered in the empty address buffer as an empty address. Described packet processing method. 7. The variable length frame has an integral multiple of the data block length by adding an auxiliary field to a frame received from a host device or a network. 6. The packet processing method described in 6. 8. A plurality of variable length frames having different logical channels are divided into a plurality of fixed length data blocks, respectively.
In the adaptation process in the network terminating equipment to multiplex transfer each data block to the same line as a fixed length packet, the buffer memory for temporarily storing the received variable length frame stores the length of multiple data blocks. When a fixed length bank is defined and a variable length frame is received, a single bank or a plurality of structured banks according to the length of the frame is secured for the logical channel, and the variable length A packet processing method characterized in that a frame is stored in the buffer memory, a fixed-length data block is sequentially read from each bank, and a predetermined header containing logical channel information is added to this to form a fixed-length packet. 9. A continuous transmission amount of fixed-length packets and an allowable maximum burst length are stored for each logical channel, and a bank corresponding to each logical channel is stored within a range in which the continuous transmission amount does not exceed the maximum burst length. The packet processing method according to claim 8, wherein a fixed-length data block is read. 10. A packet processing method for receiving a fixed-length packet composed of a fixed-length data block portion and a header and assembling the data block portions of a plurality of related packets into a variable-length frame, the data block of the received packet. The buffer memory for temporarily storing a part defines a plurality of banks each having a capacity of a plurality of blocks and having a predetermined length, and a new bank that is in an empty state for the first received packet of each frame. When all the data block parts constituting the same frame cannot be accommodated in one bank, the data block part of the received packet is assigned to the bank corresponding to the packet while allocating a new bank structured by the pointer information. Store the data sequentially and the last data block part of each frame When stored, the packet processing method characterized by generating information indicating the completed assembly of the frame. 11. A data block portion of each received packet is stored in a bank corresponding to logical channel information included in a header of the received packet.
The packet processing method described in 0. 12. A bank address corresponding to logical channel information included in a header of a received packet when a correspondence between a bank address for specifying a used bank and logical channel information is stored. 12. The packet processing method according to claim 10, wherein the data block portion of the received packet is stored in a bank specified by the bank address. 13. A bank address indicating completion of the assembling is registered in an address buffer, frame data is sequentially read from one bank in the buffer memory specified by the bank address fetched from the address buffer, When the frame is accommodated in a plurality of banks having a list structure, the remaining data block is read from a subsequent bank specified by a bank address stored as pointer information. Item 10
The packet processing method according to claim 12. 14. A buffer memory in which a plurality of banks of a predetermined length each having a capacity of a plurality of blocks are defined in advance, and an empty bank of a number corresponding to the length of each frame having a variable length is secured. However, when a plurality of banks are secured, a means for writing the variable length frame into an empty bank of the buffer memory while forming a list structure of these banks, and a single means in the buffer memory in which the variable length frame is stored Or, means for reading a fixed-length data block in a predetermined order from a list-structured bank, and means for adding a header to the data block read from the buffer memory and sending it as a fixed-length packet. A communication interface device comprising: 15. A free address buffer for storing a plurality of free addresses for specifying a bank in a free state among the banks defined in the buffer memory, wherein the writing means has the free address buffer. The communication interface device according to claim 14, wherein the bank is secured by extracting an address from the bank. 16. The writing means stores first addressing means for storing an address designating a first bank and addresses of a subsequent bank linked to the bank in correspondence with a variable length frame. Second memory means,
16. The communication interface device according to claim 15, further comprising means for selectively storing the address fetched from the empty address buffer in the first and second memory means. 17. A buffer memory in which a plurality of banks of a predetermined length each having a capacity of a plurality of blocks are defined in advance, and a fixed-length packet including a data block at the beginning of a frame is stored in the buffer memory. If an empty bank is allocated and all the subsequent data blocks of the same frame cannot be accommodated in the same bank, a new empty bank is secured and a plurality of banks of the same frame are structured into a list with pointer information while Means for writing the data block to the bank of the buffer memory, and storing the address indicating the bank including the first data block of the frame as the assembly completion information when the last data block of the frame is stored in the buffer memory And a communication means for Over face equipment. 18. A free address buffer for storing a plurality of free addresses for specifying a bank in a free state among banks defined in the buffer memory, and a bank address stored as the completion information. Data of a frame is sequentially read from one bank in the buffer memory, and when the frame is accommodated in a plurality of banks having a list structure, it is specified by a bank address stored as pointer information. 18. The method according to claim 17, further comprising: a unit for reading the remaining data block from the subsequent bank, and a unit for storing the address of the bank that has completed reading the frame data in the empty address buffer. Communication interface equipment. 19. The first memory means for storing the address designating the first bank and the address of the subsequent bank linked to the bank as the pointer information, the writing means corresponding to the variable length frame. 19. The memory device according to claim 18, further comprising: second memory means for storing; and means for selectively storing the address fetched from the empty address buffer in the first and second memory means. Communication interface equipment. 20. A variable-length frame received from a first transmission path is temporarily stored in a first buffer memory and divided into a plurality of fixed-length data blocks. The first conversion means for transferring the fixed length packet to the second transmission line side, and the data block of the fixed length packet received from the second transmission line side are temporarily stored in the second buffer memory and assembled into a variable length frame. In the interface device having the second conversion means for transferring the variable length frame to the first transmission line side, the first and second buffer memories each have a predetermined length having a capacity of a plurality of data blocks. A plurality of banks are defined in advance, and the first conversion means secures a number of empty banks corresponding to the length of the variable length frame received from the first transmission path side, Means for writing the variable length frame to the empty bank of the first buffer memory while structuring these banks in a list structure, and the first buffer memory storing the variable length frame. Means for reading a fixed-length data block in a predetermined order from a single or a list-structured bank, and a header is added to the data block read from the first buffer memory to form a fixed-length packet. The second conversion means allocates an empty bank in the second buffer memory to a fixed-length packet including the first data block of the frame, and continues the same frame. If all the data blocks cannot be accommodated in the same bank, secure a new empty bank and duplicate the same frame. Means for writing the data block of the received packet into the bank of the second buffer memory while structuring the banks of the list with pointer information, and a time point when the last data block of the frame is stored in the second buffer memory. A memory means for storing an address indicating a bank including the first data block of the frame as assembly completion information. 21. The second conversion means sequentially reads frame data from one bank in the second buffer memory specified by an address stored in the memory means, and the frames have a list structure. If the data is stored in a plurality of banks, the remaining data block is read from the subsequent bank specified by the bank address stored as pointer information, and the first data block is read.
21. The communication interface device according to claim 20, further comprising means for transferring to the transmission path side of the. 22. The communication interface according to claim 20, wherein the first and second conversion means secure the bank or the bank having a list structure corresponding to each logical channel. apparatus.