KR100244776B1 - System bus analyzer - Google Patents

Abstract

The present invention relates to a system bus analysis device that implements a master function on a system bus and provides a logic analyzer port so as to accurately analyze a weak part of a system, a margin part of a signal, and implement a reliable system. A function control module having an arbitration function, a data transfer request, and a data storage function between the modules; A processor module for providing an interface with a user and executing an arbitration request command from a user and a function control module to perform a predetermined function; A responder control module for storing data in an internal memory and transmitting data on a system bus in response to a request of a request control module of another board; A memory module controlled by the request control module and the responder control module to store data, send the data to a desired place through an internal bus, or transmit the data to a system bus; A timing pulse generator module which transmits signals on a system bus to the memory module and a transponder control module, and receives a clock driven on a system bus and a bus interface module for driving a system bus protocol and provides a clock inside a bus analyzer; A performance monitoring control module; In the system bus analysis device comprising a requestor control module and an LA interface control module,

The performance monitoring control module monitors and stores signals for measuring system performance, and transmits data of system boards to a memory module. Periodically transmit data stored in the memory module to the function control module; Receiving a data transfer request from the requester control module and the processor module to a bus to perform a system bus arbitration to obtain a internal memory permission of a function control module, and then perform data transfer; The LA interface control module relates to a system bus analyzer for transmitting all signals of the system bus through a separate internal bus so as to trigger the logic analyzer.

Description

System bus analyzer

The present invention relates to a system bus analysis device, and more particularly, implements a master function on a system bus and provides a logic analyzer port to accurately analyze a weak part of a system, a margin part of a signal, etc. It relates to a system bus analysis device for implementing the.

Since the bus status analyzer of the main computer system III manufactured by Samsung Electronics Co., Ltd. has only performed a bus slave function, that is, a function of monitoring only the bus status and providing information, other boards serving as a master function of the system There must be an action.

In order to solve this problem, by implementing a master function on the conventional bus analyzer board itself, it is possible to independently test whether there is a failure of a bus protocol and a system bus without a board performing the master function, and a system memory board test is also possible.

1 is a block diagram of a conventional bus analysis apparatus.

As shown, the conventional bus analysis apparatus includes a function control module, a processor module, and a responder control module; The memory module includes a memory module, a bus interface module, and a timing pulse generator module.

The function control module may perform an arbitration function between modules and request data transmission according to a desired form to a request control module when accessing a system memory, and store data to an internal memory module when analyzing a bus state. Have the authority to

The processor module provides an interface with a user, receives a function execution command from a user, performs an arbitration request, and provides a trigger condition when analyzing a bus state, thereby causing the function control module to perform a substantial search and storage function.

The responder control module receives a search storage command from a request control module of another board and stores the search storage command in an internal memory.

It also serves to export data onto the system bus when the requester on the other board requests data transfer.

The memory module is controlled by the requestor and the responder to store data, send it to a desired place through an internal bus, or transmit it to a system bus.

The bus interface module receives all signals driven on the system bus and sends them to the memory module and the responder control module.

It also serves to drive the signals to the system bus protocol.

The timing generator module receives a clock driven on a system bus and provides a clock inside the bus analyzer.

As described above, it is difficult to process data for analyzing a system bus state with a conventional bus analyzing apparatus implemented in the main computer III.

Because the bus clock of the conventional bus state analyzer is composed of TTL logic, it is not suitable for high speed operation, and a device suitable for a high speed system must be used for high speed operation of the bus.

In addition, in the conventional bus state analyzer, since the bus state is analyzed in the form of a basic message, it is impossible to analyze a problem about abnormal timing.

To address this, consider the stability aspects of the system more important than system performance, and consider providing a logic analyzer port to reduce development time by reducing the hassle of setting up after a bus condition problem.

The more multi-system, the more difficult it is to analyze whether the processing of the same board or unique functional boards is uneven. If the processing of the boards is skewed to either board, the expansion of the multiboards makes no sense.

For even processing of boards, the ability to check the board workload for a certain amount of time via graphs or LEDs would be a great help in system maintenance and troubleshooting.

Accordingly, an object of the present invention is to provide a system bus analysis apparatus for realizing a reliable system by analyzing the weak part of the system, the margin part of the signal, and the like early and accurately.

1 is an internal block diagram of a conventional bus analyzer.

2 is a schematic diagram of a bus analyzer mounted on a system.

3 is a performance control module block diagram of a bus analyzer.

4 is a bus request control module block diagram of a bus analyzer;

5 is a block diagram of an LA interface control module of the bus analyzer.

6 is an internal block diagram of a bus analyzer of the present invention.

In order to achieve the above object, the present invention provides a mediation function between each module and a function control module for requesting data transfer to a request control module and storing data in an internal memory module; A processor module for providing an interface with a user and executing an arbitration request command from a user and a function control module to perform a predetermined function; A responder control module for storing data in an internal memory and transmitting data on a system bus in response to a request of a requestor control module of another board; A memory module controlled by the requestor control module and the responder control module to store data, send the data to a desired place through an internal bus, or transmit the data to a system bus; A timing pulse generator module which transmits signals on a system bus to the memory module and a transponder control module, and receives a clock driven on a system bus and a bus interface module for driving a system bus protocol and provides a clock inside a bus analyzer; A performance monitoring control module; In the system bus analysis device comprising a requestor control module and an LA interface control module,

The performance monitoring control module monitors and stores the signals that measure the system performance and sends the data of the system boards to the memory module. Periodically transmit data stored in the memory module to the function control module; The requestor control module receives a data transfer request from the processor module to a bus, performs system bus arbitration, receives an internal memory permission of a function control module, and then performs data transfer; The LA interface control module sends all signals on the system bus through a separate internal bus for triggering by a logic analyzer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram showing how the bus analyzer board is mounted and used in a real system.

The dotted line is an internal block diagram of the main computer developed at present.

In the figure, the CPU board is a dual processor with a maximum of eight boards, that is, 16 processors, can be mounted up to Pentium 200MHz.

The MEM board has a capacity of 512Mbytes / sheet. Up to four boards can support 2GB of system memory.

The IOP uses SUN Spark's CPU and mounts various I / O devices such as disk and RAID through the internal SCSI bus. In addition, by connecting VME RACK and supporting various communication protocols, communication between heterogeneous systems is possible.

In addition, the system console is connected through the IOP board to perform system maintenance and various controls.

As described above, the CPU board and the IOP board are connected in a backplane manner through a system bus.

The system bus operates at 33MHz with a data depth of 128 bits and an address size of 32 bits. In addition, several signals used for the rest of the control are combined to communicate with the internal protocol to operate the system.

Hereinafter, each internal block of the bus analysis device will be described in more detail.

2 is a diagram illustrating an internal block diagram of a bus analysis apparatus.

As shown, the control module includes a function control module, a processor module, a responder control module, a memory module, a bus interface module, a timing pulse generator module, a requestor control module, an LA interface module, and a performance monitoring control module.

Each function is explained as follows.

The function control module, the processor module, the responder control module, the memory module, the bus interface module and the timing pulse generator module are the function control module, the processor module, the responder control module, the memory module, the bus of the system bus state analyzer of the prior art described above. Same as the interface module and timing pulse generator module.

Therefore, in the configuration and operation of the present invention, the description of the above modules is omitted, and the requestor control module, the LA interface module, and the performance monitoring control module added in the present invention will be described.

When the requestor control module receives a data transmission request from the processor module to the system bus, the requester control module performs system bus arbitration to receive the permission of the internal memory of the function control module and then perform the data transmission.

The LA interface module transmits the signals through a separate internal bus so that all signals on the system bus can be triggered by the logic analyzer.

The performance monitoring control module monitors and stores signals that measure system performance, and transmits the amount of system board data to the memory module.

In addition, the data stored in the memory module is periodically transmitted to the function control module.

Hereinafter, the performance monitoring control module and the requestor control module and the LA interface module will be described in more detail.

3 is a detailed block diagram of the performance monitoring control module.

This module evaluates the performance of the desired part by receiving all data on the system bus so that the performance of the multiprocessor system can be analyzed.

The module measures and monitors the reading and writing time of the data against the bus clock.

When reading or writing data from the bus, the CPU boards or IOP boards first put the address on the bus and wait for data to come from the memory board.

At this time, the performance monitoring control module checks the time from when the user knows that the desired address is input to the bus and enters data from the memory board and displays the time on the monitor.

This function can adjust the time as you want.

It is possible to detect exactly where the weak point from the system is located.

The display on the monitor can be selected according to histogram or ASCII code format.

It is then possible to check how much of the current system is using the data bus or the address bus, or if the usage of the data bus or address bus is high and which part of the system is affected.

In other words, the performance of the part can be monitored and displayed using control signals other than the data bus and the address bus.

The 128-bit data, 32-bit address and control bus shown in the left part of FIG. 3 are input data coming into the performance monitoring control module.

The performance monitoring control module receives the data, address, and control bus signals of the system bus, operates under conditions of a user's desired condition, generates a result, and transmits the result data to the memory module.

The input data is then displayed on the CRT monitor from the function control module to the memory module.

4 is a detailed block diagram of the requestor control module.

This module adds this module, whereas the conventional bus analyzer only detects and analyzes the signals appearing on the bus. They also try to send and analyze the conditions on the bus when the bus rules are broken.

The function of this module transmits a signal SQRDRDY indicating a state transition to the function control module as the system address bus cycle progresses, so that the function control module can control the data path.

Generates signals such as AACK, SQUITV, SQSHD, etc. according to AACK [1: 0], address snooping result signals DTYI, SNKI, ITVI, LCRI, SHDI, etc. When sent, the function control module will arbitrate the bus right to the bus intermediary as required by the CPU on the current bus.

As a result, once the bus license is acquired, the bus operates according to the protocol.

Because the bus analyzer only tests the function of the simple bus protocol, it is not to test the bus with high load to operate the system, but to check whether the data is transmitted while complying with the specifications on the bus.

5 is a detailed block diagram of an LA interface module.

This module analyzes the data of the conventional bus analysis device by analyzing only the data at the time of detection by the system bus analysis device of the present invention. It is a module that can accurately determine whether the bus analyzer analyzes properly or the timing specifications are properly performed.

Rather than verifying the display with a bus-scanning monitor as described above, a separate bus is provided to provide LA analyzer ports for a more granular view of timing through the logic analyzer.

It accepts the data of the system bus and transmits the data to the logic analyzer. The data of the bus that is input frequently is transmitted to the LA port.

According to the configuration of the present invention as described above, since the contents can be analyzed accurately with respect to the problems caused, the optimum design of the system is possible.

Claims (5)

A function control module for requesting data transfer to the requestor control module and an arbitration function between each module, and storing data to an internal memory module; A processor module for providing an interface with a user and executing an arbitration request command from a user and a function control module to perform a predetermined function; A responder control module for storing data in an internal memory and transmitting data on a system bus in response to a request of a requestor control module of another board; A memory module controlled by the requestor control module and the responder control module to store data, send the data to a desired place through an internal bus, or transmit the data to a system bus; A timing pulse generator module which transmits signals on a system bus to the memory module and a transponder control module, and receives a clock driven on a system bus and a bus interface module for driving a system bus protocol and provides a clock inside a bus analyzer; Performance monitoring control module; A requestor control module; In the system bus analysis device comprising a LA interface control module, The performance monitoring control module monitors and stores signals for measuring system performance, and transmits data of system boards to a memory module. Periodically transmit data stored in the memory module to the function control module; The requestor control module receives a data transfer request from the processor module to a bus and performs system bus arbitration to receive a memory permission of a function control module and then perform data transfer; The LA interface control module transmits all signals on the system bus through a separate internal bus so as to trigger the logic analyzer. System bus analyzer. The apparatus of claim 1, wherein the requestor control module adds a master function to a bus analyzer slave function to enable independent testing during offline testing. The apparatus of claim 1, wherein the performance monitoring control module is capable of performance analysis by adding a system performance check logic. The apparatus of claim 1, wherein the LA interface control module is capable of timing analysis by providing a logic analyzer port. 5. The system bus analysis apparatus according to any one of claims 1 to 4, wherein all of the logic is used by a PLD chip so that the logic can be changed according to the function and system specification of the system bus analysis apparatus.

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