KR100242286B1 - A r/w control circuit of hdd - Google Patents

Abstract

The present invention relates to a read / write channel optimization control circuit of a hard disk driver (HDD), and more particularly, to a circuit in which a noise of a signal picked up and output from a media is reduced to an optimal state by being one-chip.

The read / write channel optimization control circuit of the hard disk driver (HDD) includes a variable gain amplifier 14 which maintains and outputs an analog signal amplified and output from the preamplifier 12 at a predetermined level as a signal having a constant voltage level. And a peak detector 18 for waveform shaping and outputting the analog signal maintained at a constant voltage level from the variable gain amplifier 14 as a digital signal, and synchronizing the output of the peak detector 18 to an internal reference clock. A synchronizing circuit 20 for outputting the data, a synthesizing circuit 22 for outputting a high density recording signal by frequency-modulating the data to be recorded, and outputting one of the synchronizing circuit 20 and the output of the synthesizing circuit 22. A multiplexer 26, an encoder / decoder 24 that decodes and outputs ride data among the outputs of the MUX 26, encodes and outputs write data, and a peak detector 1 8) a hysteresis amplifier 18b for waveform shaping an analog signal and outputting it as a digital signal, a differentiator 18a for differentially outputting the analog signal, and outputs of the hysteresis amplifier 18b and the differentiator 18a. The one-short generator 18c for outputting the one-short pulse is built in one chip.

Description

Lead / Write Control Circuit of Hard Disk Driver

1 is a lead / write control circuit diagram of a hard disk driver according to the present invention.

* Explanation of symbols for main parts of the drawings

12: preamplifier 14: VGA

16: programmable filter 18: peak detector

20: synchronization circuit 22: synthesis circuit

24: encoder / decoder 26: mux

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read / write channel optimization control circuit of a hard disk driver (HDD). In particular, the present invention relates to a circuit in which one-chip is used to reduce noise of signals picked up and output from media to an optimal state. It is about.

Typically, a hard disk driver has a read / write control circuit for recording information into a media and decoding and outputting an analog signal reproduced weakly from the media into a digital signal.

Such a lead / light control circuit includes a circuit for frequency modulating digital information to be recorded, an amplification and filtering circuit for amplifying an output signal of a head picking up the information recorded in the media, and amplifying and then performing low pass filtering with a predetermined gain; A waveform shaper for digitizing the output of the amplification and filtering circuit, a synchronization circuit for synchronizing and outputting the output of the waveform shaper with a reference clock, and encoding and outputting the frequency modulated output, and decoding the output of the synchronization circuit. The circuit which outputs is provided.

However, in the conventional lead / light control circuits, the circuits are separately configured and separately installed on the FPC and PCB of the HDA, so that there is a lot of influence on external and internal noises, so that data recording and leaded data errors are frequent. Occurred.

In addition, the configuration of each circuit individually increases the volume of the hard disk driver, which has been a detrimental factor in the compact system implementation.

Accordingly, an object of the present invention is to provide a lead / write channel optimization circuit of a one-chip hard disk driver.

Another object of the present invention is to provide a read / write control circuit of a hard disk driver which is improved not to be affected by external and internal noise.

Still another object of the present invention is to provide a read / write channel optimization control circuit of a hard disk driver that can be easily installed in an FPC of an HDD system.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a flow chart of a read / write channel optimization control of a hard disk driver according to the present invention.

A preamplifier 12 for amplifying and outputting the signal output from the head to a predetermined level;

A variable gain amplifier 14 which maintains and outputs the analog signal amplified and output from the preamplifier 12 to a predetermined voltage level;

A peak detector 18 for waveform shaping the analog signal maintained at a constant voltage level from the variable gain amplifier 14 and outputting the analog signal as a digital signal;

A synchronization circuit 20 for outputting the output of the peak detector 18 in synchronization with an internal reference clock;

A synthesis circuit 22 for frequency-modulating the data to be recorded and outputting a high density recording signal (Constant Recording Density Singnal);

A multiplexer (26) for outputting one of the synchronization circuit (20) and one of the outputs of the synthesis circuit (22);

The encoder / decoder 24 is configured to decode and output ride data among the outputs of the MUX 26 and to encode and output recording data.

In the configuration of FIG. 1, the peak detector 18 includes: a hysteresis amplifier 18b for waveform shaping the analog signal and outputting it as a digital signal;

A differentiator 18a for differentially outputting the analog signal,

The hysteresis amplifier 18b and the one-short generator 18c which output the one-short pulse by the output of the differentiator 18a are comprised.

The synchronization circuit 20 is composed of a PLL using a mux 20a, a charge pump 20b, a phase detector 20c, and a VCO (Voltage Conrolled Oscilator) 20d, and the synthesis circuit 22 includes a mux ( 22f), divider 22a, 22e, phase detector 22b, charge pump 22c, and VCO 22d.

The operation of FIG. 1 is as follows.

When the analog signal output from the head is input to the preamplifier 12, the preamplifier 12 amplifies the input signal by about 300 times and outputs it to the VGA (Variable Gaim Amplifier) 14. At this time, the VGA 14 maintains the amplified analog signal at a constant voltage level and inputs it to the programmable filter 16. The programmable filter 16 low-pass filters the input signal to remove noise and output the noise. In this case, the programmable filter 16 is configured to program a bandwidth for high sensitivity recording (Constant Recording Density).

The peak detector 18 waveform-forms the filtered and removed noise-reproducing signal to the synchronization circuit 20. The synchronization circuit 20 outputs the inputted reproduction data to the encoder / decoder 24 in synchronization with the reference clock.

At this time, the encoder / decoder 24 which inputs the lead signal synchronized with the reference clock decodes the read data and outputs the read data as reproduction data.

When data to be recorded to the Manyan Synthesizer 22 is input, the Synthesizer 22 modulates the data to be input to the encoder / decoder 24 through the MUX 26. The encoder / decoder 24 which inputs the frequency modulated data encodes the data and supplies it to the head.

At this time, all the circuits of FIG. 1 operating as described above are one-chip in one package and installed in the FPC of the HDA.

As described above, according to the present invention, the control circuit for the lead / right channel is made into a single chip so that the noise can be improved by not being influenced by the noise generated from the outside and the inside, and the miniaturization can be achieved by installing the FPC in the FPC.

Claims (1)

In a lead / write control circuit of a hard disk driver having a preamplifier 12 for amplifying and outputting a signal picked up and outputted from a head to a predetermined level, an analog signal amplified and output from the preamplifier 12 to a predetermined level. A variable gain amplifier 14 for sustaining and outputting the signal as a signal having a constant voltage level, and a peak detector 18 for waveform shaping and outputting the analog signal maintained at the constant voltage level from the variable gain amplifier 14 as a digital signal. And a synchronizing circuit 20 for synchronizing the output of the peak detector 18 to an internal reference clock, a synthesizing circuit 22 for frequency modulating the data to be recorded, and outputting a high density recording signal, and the synchronizing circuit. (20), a multiplexer (26) for outputting one of the outputs of the synthesis circuit (22), and the ride data of the output of the MUX (26) is decoded and outputted, The encoder / decoder 24 for encoding and outputting the lock data, the peak detector 18 has a hysteresis amplifier 18b for waveform-shaping the analog signal and outputting it as a digital signal, and the differential for outputting the analog signal differentially ( 18a), and a one-short generator (18c) for outputting a one-short pulse by the output of the hysteresis amplifier (18b) and the differentiator (18a).