JP3842240B2 - Magnetic recording / reproducing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a magnetic recording / reproducing apparatus, and more particularly to a magnetic recording / reproducing apparatus having a simultaneous reproducing function for reproducing substantially simultaneously with a recording operation.
[0002]
[Prior art]
Since the video tape recorder for broadcasting stations often has difficulty in re-recording, in order to prevent recording failure, a simultaneous playback function for playing back and confirming the recorded content almost simultaneously during recording is required. In order to realize this simultaneous reproduction function, an erasing head, a recording head, and a reproducing head arranged at close distances, and an erasing, recording, and reproducing rotary transformer for transmitting signals to them simultaneously operate. Therefore, it is necessary to suppress the crosstalk interference from the erase signal and the recording signal mixed in the weak reproduction signal to a sufficiently low level. In particular, since the erase signal has a larger amplitude than the recording signal, the crosstalk interference is also large.
[0003]
Further, the error rate is deteriorated by the fact that the erase signal itself is recorded on the tape and mixed into the reproduction signal (residual component of the erase signal).
[0004]
Thus, conventionally, the erasure frequency has been set on the high frequency side outside the reproduction band, and interference has been avoided by removing the crosstalk component contained in the reproduction signal with a trap or a low-pass filter.
[0005]
By the way, in order to perform recording with high image quality, the data rate becomes high, and accordingly, the erasing frequency needs to be shifted toward a high frequency. However, in order to increase the erasing frequency, it is necessary to expand not only the band of the erasing amplifier but also the output dynamic range. This is because as the frequency rises, the amplitude of the output voltage is required, and in addition, a large current is required to reduce the efficiency of the erase head. For this reason, it is necessary to increase the power supply voltage and current capacity for the erasure amplifier in the video tape recorder for broadcasting stations.
[0006]
Therefore, it is desirable to set the erasure frequency as close to a low frequency as possible within a range that does not adversely affect the reproduction signal.
[0007]
Hereinafter, a case where the erasure frequency is set to fb / 2 (fb: bit frequency) in a video tape recorder for broadcasting stations in which the recording encoding method is scrambled interleaved NRZI will be described with reference to the drawings.
[0008]
FIG. 6 shows the relationship between the PR4 equalization characteristics, the reproduction amplifier band, and the erasing frequency in terms of the normalized frequency. In FIG. 6, the solid line A indicates the PR4 equalization characteristic, the alternate long and short dash line B indicates the reproduction amplifier band, and the erasing frequency is set to fb / 2. As shown in FIG. 6, fb / 2 is the minimum point (null frequency) of the PR4 equalization characteristic, and it is possible to completely remove the residual component of the crosstalk and the erase signal.
[0009]
FIG. 7 is a block diagram of the erase circuit. The erase circuit has an oscillation circuit configuration, and the erase amplifier 8 is positively fed back by the feedback resistors 10 and 11 and oscillates. The oscillation frequency is adjusted to fb / 2 by an oscillation frequency adjusting capacitor 9 as a capacitance element. That is, in this erasing circuit, the erasing amplifier has a frequency determined by resonance due to the inductance of the path from the erasing amplifier 8 to the erasing head 7 including the erasing rotary transformer 5 and the capacitance of the variable capacitance diode 37 as the oscillation frequency adjusting capacitance element. The frequency of the erase current is determined by oscillating 8.
[0010]
An erasing signal (erasing current) output from the erasing amplifier is supplied as an erasing current 6 to the erasing head 7 through the erasing rotary transformer 5.
[0011]
FIG. 8 is a simplified version of FIG. The frequency of the erasing signal (erasing current) becomes a resonance frequency by the total inductance 21, the stray capacitance 20, and the oscillation frequency adjusting capacitor 9 including the erasing rotary transformer 5, the erasing head 7, and the wiring. The oscillation circuit configuration is because the circuit scale is small, the power supply utilization rate is good, and a low power supply voltage and low power consumption are possible.
[0012]
However, it is generally known that the inductance values of the erasing head 7 and the erasing rotary transformer 5 vary by about ± 10%. Further, the stray capacitance and the capacitance value of the oscillation frequency adjusting capacitor 9 also vary by about ± 10%. Here, what is dominant in determining the resonance frequency is the inductance value of the erasing head 7 and the capacitance value of the oscillation frequency adjusting capacitor 9.
[0013]
Note that the above-described variations include not only variations in values for each element but also variations due to changes over time, temperature changes, and the like.
[0014]
Therefore, it is necessary to assume the worst ± 10% variation in the erase frequency. That is, in FIG. 6, the erase frequency varies from fb / 2 to f1 to f2. When the erase frequency varies ± 10%, the removal rate of erase crosstalk in the reproducing circuit system and the residual component recorded on the magnetic tape is −∞ to −10 dB as shown in FIG. 6 on the basis of fb / 4. It deteriorates until. This not only makes simultaneous reproduction impossible, but also affects the normal reproduction signal as an in-band residual component, degrading the error rate.
[0015]
Here, in order to eliminate variations in the erase frequency, a configuration as shown in FIG. 9 can be considered. A clock (bit frequency fb) synchronized with the recording data is input to the frequency dividing circuit 2 through the input terminal 1. The erase signal 3 which has been changed to fb / 2 by the frequency divider 2 is supplied to the erase amplifier 4, and its output is supplied to the erase head 7 through the erase rotary transformer 5 as an erase current 6. In this configuration, frequency variation is eliminated, but not the oscillation configuration, but basically the same configuration as the recording amplifier, which reduces the power supply utilization rate and greatly increases the power consumption.
[0016]
[Problems to be solved by the invention]
In the conventional example, it is necessary to provide a circuit for removing the erasure component for each data rate.
[0017]
An object of the present invention is to provide a magnetic recording / reproducing apparatus that is advantageous in terms of circuit scale and power consumption, and that does not require a circuit for removing an erasing component for each data rate.
[0018]
[Means for Solving the Problems]
In order to achieve this object, a magnetic recording / reproducing apparatus according to claim 1 of the present invention comprises an erasing head for erasing a recording data signal on a magnetic recording medium, and an erasing operation by the erasing head simultaneously on the magnetic recording medium. The resonance frequency by the recording head for recording the new recording data signal, the reproducing head for simultaneously reproducing the new recording data signal recorded on the magnetic recording medium, the inductance up to the erasing head and the added capacitance is reproduced. In the case of recording / reproducing at multiple data rates ,in front Input signal to the erase amplifier Depending on the data rate, either the divided signal of the recording clock, the recording clock itself or no input It has a switch circuit for switching.
[0019]
According to this configuration, even when recording at a low data rate, the erasure frequency is maintained near the minimum point of the reproduction equalization characteristic at the highest data rate, that is, outside the band at the low data rate. There is little influence and it is not necessary to provide a circuit for removing the erasure component for each data rate.
[0020]
The magnetic recording / reproducing apparatus according to claim 2 of the present invention has n erasing heads, and n (n is an integer of 2 or more) erasing amplifiers for the n erasing heads. The phase of the recording clock input to the erase amplifier is shifted by a certain amount for each erase head.
[0021]
According to this configuration, since the phase of the erase signal supplied to the n erase heads is shifted by a certain amount, the crosstalk component corresponding to each erase head cancels out, and the erase circuit system regenerates the reproduction circuit system. Crosstalk can be reduced. Other functions are the same as those of the first aspect.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention and a reference magnetic recording / reproducing apparatus will be described below with reference to FIGS.
[0023]
Here, prior to the description of the embodiment, a reference example of the magnetic recording / reproducing apparatus will be described with reference to FIGS.
[0024]
(First reference example)
FIG. 1 is a block diagram of an erasing circuit in the magnetic recording / reproducing apparatus of the first reference example. The blocks having the same functions as those of the conventional example shown in FIGS. 7, 8, and 9 are denoted by the same reference numerals. 7 differs from the conventional example of FIG. 7 in that the oscillation frequency adjusting capacitor (capacitance element) 9 is changed to a variable capacitance diode 37 and a control circuit 101 is newly provided for this, and other configurations are shown in FIG. 7 is the same as the conventional example. . The control circuit 101 controls the erasing frequency of the erasing amplifier 8 to be in the vicinity of the minimum point (fb / 2) of the reproduction equalization characteristic. Specifically, the control unit 101 controls the capacitance of the variable capacitance diode 37 so that the oscillation frequency of the erasing amplifier 8 is in the vicinity of the minimum point of the reproduction equalization characteristic.
[0025]
The erasing circuit of FIG. 1 has an oscillating circuit configuration as in FIG. 7, and the erasing amplifier 8 is positively fed back by the feedback resistors 10 and 11 and oscillates. The oscillation frequency is adjusted to fb / 2 by the variable capacitance diode 37. The erase signal is supplied as an erase current 39 to the erase head 7 through the erase rotary transformer 5.
[0026]
The control circuit 101 that controls the variable capacitance diode 37 will be described in detail. A clock having a frequency fb synchronized with the recording data is input to the frequency dividing circuit 32 that divides the frequency to ½ the frequency via the input terminal 31. The output clock having the frequency fb / 2 of the frequency dividing circuit 32 and the erase signal 38 are input to the phase comparison circuit 33. Here, the clock having the frequency fb / 2 is a reference input signal of the phase comparison circuit 33. The output of the phase comparison circuit 33 is input to a gain adjustment circuit 35 through a low pass filter (LPF) 34 and amplified to a voltage necessary for controlling the variable capacitance diode 37. As a result, the erase frequency is phase-compared using the recording clock as a reference signal, and is therefore accurately set to fb / 2.
[0027]
FIG. 2 is a schematic diagram showing the relationship between the erase oscillation frequency, the signal 36 (the output of the gain adjusting circuit 35, that is, the control voltage of the variable capacitance diode), and the capacitance value of the variable capacitance diode 37.
[0028]
When the oscillation frequency falls below fb / 2, it is detected by the phase comparison circuit 33, the signal 36 (reverse voltage applied to the variable capacitance diode) DC (direct current) value increases, the capacitance decreases, and the oscillation frequency increases. . On the other hand, when the oscillation frequency exceeds fb / 2, it is detected by the phase comparison circuit 33, the signal 36 (reverse voltage applied to the variable capacitance diode) DC value decreases, the capacitance increases, and the oscillation frequency decreases.
[0029]
As described above, in the conventional example, the oscillation frequency varies due to variations in inductance of the erasing head 7 and the erasing rotary transformer 5, but in this reference example, the oscillation frequency is always maintained at fb / 2 by applying feedback. Is done. Therefore, an erasing circuit is realized in which the oscillation frequency is accurately set to fb / 2 with a small-sized and low power consumption resonance configuration.
[0030]
As described above, according to this reference example, since the control means 101 for controlling the oscillation frequency of the erasing amplifier 8 to be near the minimum point of the reproduction equalization characteristic is provided, a resonance configuration that is advantageous in terms of circuit scale and power consumption. Even so, it is possible to accurately set the minimum point (for example, fb / 2) of the reproduction equalization characteristic by suppressing the variation of the erasure frequency, and as a result, it is easy to remove the erasure component in the reproduction circuit system. Can do.
[0031]
Further, the voltage of the capacitance of the variable capacitance diode 37 is controlled so that the oscillation frequency of the erasing amplifier 8 is in the vicinity of the minimum point of the reproduction equalization characteristic, so that the erasing current frequency can be easily adjusted by voltage control. Can be done.
[0032]
Further, since the frequency-divided signal of the clock signal is used as a reference signal for phase comparison, a special reference signal source is unnecessary and the circuit configuration is simple.
[0033]
(Second reference example)
Next, a second reference example of the magnetic recording / reproducing apparatus will be described. FIG. 3 is a block diagram of the erase circuit of this reference example. The blocks having the same functions as those of the reference example of FIG. 1 and the conventional examples shown in FIGS. 7, 8, and 9 are denoted by the same reference numerals.
[0034]
The difference between this reference example and the first reference example is that two erase heads 7 and 90 operate simultaneously, and correspondingly, erase amplifier 84, feedback resistors 82 and 83, variable capacitance diode 85, erase Since only the rotary transformer 88 and the control circuit 102 are provided, only the portion added to the first reference example will be described.
[0035]
The positional relationship between the two erasing heads 7 and 90 is adjacent on the rotating cylinder and operates simultaneously. Accordingly, since erase currents having opposite phases flow from two adjacent erase heads, crosstalk components leaking into the reproducing head cancel each other.
[0036]
In FIG. 3, similarly to the first reference example, the erase circuit has an oscillation circuit configuration, and the erase amplifier 84 is positively fed back by the feedback resistors 82 and 83 and oscillates. The oscillation frequency is adjusted to fb / 2 by the variable capacitance diode 85. The erase signal is supplied as an erase current 89 to the erase head 90 through the erase rotary transformer 88.
[0037]
The control circuit 102 that controls the variable capacitance diode 85 will be described. A clock having a frequency fb synchronized with the recording data is input to the frequency dividing circuit 32 that divides the frequency to ½ the frequency via the input terminal 31. The clock having the frequency fb / 2 of the frequency dividing circuit 32 is inverted by the inverting circuit 80 and input to the phase comparison circuit 81 together with the erase signal 91. Here, the inverted clock of the frequency fb / 2 is the reference input signal of the phase comparison circuit 81. The output of the phase comparison circuit 81 is input to the gain adjustment circuit 87 through the low pass filter 86 and is amplified to a voltage necessary for controlling the variable capacitance diode 85. As a result, the erase frequency is phase-compared using the recording clock as a reference signal, and is therefore accurately set to fb / 2.
[0038]
Next, a description will be given by paying attention to the relationship between the two erasing currents.
[0039]
In FIG. 3, erase signals 38 and 91 of erase heads 7 and 90 operating simultaneously are supplied to phase comparison circuits 33 and 81, respectively. As described in the first reference example, the reference input signal of the phase comparison circuit 33 is obtained by dividing the clock having the frequency fb synchronized with the recording data by ½ the frequency. On the other hand, the reference input signal of the phase comparison circuit 81 is obtained by inverting the reference input signal of the phase comparison circuit 33 by the inverting circuit 80.
[0040]
Therefore, the phase of the erasing current 89 supplied to the erasing head 90 has an inverted relationship compared to the erasing current 39 supplied to the erasing head 7. As a result, crosstalk from the erase circuit system to the reproduction circuit system is reduced because the crosstalk components of the erase heads 7 and 90 cancel each other.
[0041]
In this reference example, two erasing heads are operated simultaneously. However, even if there are n systems (n is an integer of 2 or more), the reference input signal of the phase comparison circuit for each erasing head is, for example, the same angle. The same effect can be obtained if different phases are shifted.
[0042]
(Third reference example)
Next, a third reference example of the magnetic recording / reproducing apparatus will be described. The difference between this reference example and the first and second reference examples is the control method of the variable capacitance diode 37.
[0043]
In the first and second reference examples, the erase frequency is fixed at fb / 2. This is based on the assumption that the minimum point (null point) in the reproduction equalization characteristic of PR4 is always fixed at fb / 2.
[0044]
However, in the case of a reproduction equalization circuit using analog elements, the delay amount may be adjusted while looking at the error rate. In this case, the minimum point of the equalization characteristic is not always fb / 2. Therefore, even in such a case, the erasing frequency of the erasing circuit must be set to be a minimum value of the equalization characteristic.
[0045]
FIG. 4 is a block diagram of the erase circuit of this reference example. The blocks having the same functions as those of the conventional example shown in FIGS. 7, 8, and 9 are denoted by the same reference numerals.
[0046]
The erase circuit has an oscillation circuit configuration, and the erase amplifier 8 is positively fed back by the feedback resistors 10 and 11 and oscillates. The oscillation frequency is adjusted to the minimum value of the reproduction equalization characteristic by the variable capacitance diode 37. The erase signal is supplied as an erase current to the erase head 7 via the erase rotary transformer 5.
[0047]
The control circuit 103 that controls the variable capacitance diode 37 will be described. At the time of simultaneous playback that plays back simultaneously with the erasing and recording operations, the signal played back from the playback head 41 is input to the playback amplifier 43 via the playback rotary transformer 42. At this time, the crosstalk 50 from the erasing system is mixed in the reproduction signal. The frequency characteristic of the output of the reproduction amplifier 43 including the delay amount of the delay element is adjusted so that the error rate is minimized by the reproduction equalization circuit 44. The output of the reproduction equalization circuit 44 is supplied to the detection circuit 45 and converted into a digital signal.
[0048]
On the other hand, the output of the reproduction equalization circuit 44 is supplied to a band pass filter (BPF) 46 having a center frequency of fb / 2. The band pass filter 46 extracts an erasure frequency component mixed as crosstalk in the reproduction signal. The output of the bandpass filter 46 is supplied to the frequency detection circuit 47, and a DC value corresponding to the erasing frequency is output. The output of the frequency detection circuit 47 is supplied to the gain adjustment circuit 49 through the low-pass filter 48 and amplified to a voltage necessary for controlling the variable capacitance diode 37.
[0049]
The band pass filter 46 corresponds to erasure frequency component extraction means for extracting the erasure frequency component mixed as crosstalk in the reproduction signal from the output signal of the reproduction equalization circuit 44 that processes the reproduction signal. Further, the frequency detection circuit 47 changes the capacitance of the variable capacitance diode in accordance with the frequency of the erasure frequency component extracted by the erasure frequency component extraction means, whereby the oscillation frequency of the erasure amplifier becomes near the minimum point of the reproduction equalization characteristic. It corresponds to the frequency detection means to be controlled as described above.
[0050]
In this reference example, the frequency detection circuit 47 uses an FM demodulation circuit, and the characteristics of the bandpass filter 46 are center frequency fb / 2 and cut-off frequency (-3 dB frequency) fb / 2 ± 10%. . As a result, the erase frequency is accurately set to the minimum value even when the minimum value of the reproduction equalization characteristic deviates from fb / 2.
[0051]
Here, when the erase frequency component included in the reproduction signal is detected and the voltage of the variable capacitance diode 37 is controlled in accordance with the frequency, the erase frequency is shifted from the minimum value of the reproduction equalization characteristic from fb / 2. The reason why the minimum value can be accurately set will be described. That is, when the erasure frequency component included in the reproduction signal is shifted, a voltage (DC) value is output from the frequency detection circuit 47 (which converts the frequency variation into a voltage by the FM demodulation circuit) 47. If the erase frequency increases, the output voltage increases, and if the erase frequency decreases, the output voltage decreases. Therefore, if the variable capacitance diode 37 is controlled by this output voltage, the erase frequency can be controlled with high accuracy.
[0052]
As described above, according to this reference example, the oscillation frequency of the erasure amplifier 8 is reproduced by changing the capacitance of the variable capacitance diode 37 in accordance with the frequency of the erasure frequency component mixed in the reproduction signal as crosstalk. Since the control is performed so that it is in the vicinity of the minimum point of the equalization characteristic, even if the minimum value of the reproduction equalization characteristic deviates from fb / 2, the erase current frequency is accurately set to the minimum value of the reproduction equalization characteristic. Therefore, it is possible to easily remove the erasing component in the reproducing circuit system.
[0053]
In the first and third reference examples, the number of erasing heads is one, but the same effect can be obtained even when there are n systems (n is an integer of 2 or more).
[0054]
(Embodiment)
Next, an embodiment of the magnetic recording / reproducing apparatus of the present invention will be described. FIG. 5 is a block diagram of the erase circuit of this embodiment. The same number is attached to the block diagram of the same function as FIG.
[0055]
This embodiment differs from the third reference example in that the variable capacitance diode, the phase comparison circuit that controls the variable capacitance diode, the LPF, and the gain adjustment circuit are eliminated, and the oscillation frequency adjustment of the fixed capacitance is performed instead of the variable capacitance diode. This is a point where a capacitor is provided and a point where a switch circuit 204 is provided. Therefore, only functions different from the third reference example will be described.
[0056]
In the present embodiment, it is assumed that reproduction equalization is performed by digital signal processing, and in addition to normal data rate recording, 1/2 data rate recording and 1/4 data rate recording are possible.
[0057]
In FIG. 5, similarly to the third reference example, the erase circuit has an oscillation circuit configuration, and the erase amplifiers 8 and 84 are positively fed back by the feedback resistors 10 and 11 and the feedback resistors 82 and 83, respectively, and oscillate. The oscillation frequency is adjusted to approximately fb / 2 by the oscillation frequency adjusting capacitors 202 and 203.
[0058]
A clock having a frequency fb synchronized with the recording data is input to the frequency dividing circuit 201 that divides the frequency to ½ frequency via the input terminal 200. The clock having the frequency fb / 2 of the frequency dividing circuit 201 is input to the erasing amplifier 8 and the inverting circuit 80 through the switch circuit 204.
[0059]
The switch circuit 204 selects the output of the frequency dividing circuit 201 during normal data rate recording, and selects the recording clock itself during normal data rate recording, according to the control signal supplied from the input terminal 205. However, this is a three-state switch circuit that is controlled so that no output is produced at the time of recording an appropriate quarter data rate.
[0060]
The clock having the frequency fb / 2 inverted by the inverting circuit 80 is input to the erasing amplifier 84. Erase amplifiers 8 and 84 whose oscillation frequency is adjusted to approximately fb / 2 accurately supply an erase current having a frequency fb / 2 in response to a clock input having a frequency fb / 2. At this time, the phases of the erase current 39 supplied to the erase head 7 and the erase current 89 supplied to the erase head 90 are in an inverted relationship. As a result, the crosstalk from the erase circuit system to the reproduction circuit system is reduced because the crosstalk components of the erase heads 7 and 90 cancel each other.
[0061]
In this embodiment, there are two erasing heads operating simultaneously. However, even if there are n systems (n is an integer of 2 or more), the input clocks of the erasing amplifiers have different phases shifted by, for example, the same angle. If so, the same effect can be obtained.
[0062]
As described above, according to this embodiment, the erase current can be set to a specific phase relationship at a frequency of fb / 2 with a simpler circuit configuration, and the erase component can be removed in the reproduction system. Can be made easier.
[0063]
Even when recording at three data rates of 1/2 and 1/4 in addition to the normal data rate, the erase frequency is accurately fb / 2 at the normal data rate, that is, reproduction equalization at the data rate. It is set at the minimum point of the characteristic, and is set at the same erasure frequency as that at the normal data rate at the 1/2 data rate, that is, outside the band of the reproduction equalization characteristic, and at the normal data rate at the 1/4 data rate recording. Substantially the same erasure frequency, that is, outside the band of the reproduction equalization characteristic is set. At the time of 1/4 data rate recording, there is no input to the erasing amplifier, and therefore the erasing frequency is the oscillation frequency of the erasing circuit system itself, that is, the frequency near fb / 2 at the normal data rate. Thereby, even at the time of low data rate recording, the erase frequency is maintained near the minimum point of the reproduction equalization characteristic at the normal data rate, that is, outside the band at the time of the low data rate, so there is little influence on the reproduction circuit system, In addition, it is not necessary to provide a circuit for removing the erasure component for each data rate.
[0064]
In this embodiment, it is possible to correct not only variations in values for each element but also variations in erase frequency due to variations due to changes over time or temperature.
[0065]
In each of the reference examples and the embodiments described above, the frequency dividing circuit halves the frequency. However, the frequency dividing ratio of the frequency dividing circuit is not limited to this, and 1 / k (k is an integer of 1 or more). )
[0066]
【The invention's effect】
The magnetic recording / reproducing apparatus according to claim 1 of the present invention has a reproducing equalization characteristic at the highest data rate even at a low data rate recording even in a resonance configuration advantageous in circuit scale and power consumption. Therefore, there is little influence on the reproduction circuit system, and there is no need to provide a circuit for removing the erasure component for each data rate.
[0067]
According to the magnetic recording / reproducing apparatus of the second aspect of the present invention, the phase of the recording clock applied to the n erase amplifiers is shifted by a certain amount for each erase head, and is supplied to the n erase heads. Since the phase of the erase signal is shifted by a certain amount, the crosstalk components corresponding to the respective erase heads cancel each other, and the crosstalk from the erase circuit system to the reproduction circuit system can be reduced. Other effects are the same as those of the first aspect.
[Brief description of the drawings]
FIG. 1 is a block diagram of an erase circuit of a first reference example of a magnetic recording / reproducing apparatus.
FIG. 2 is a schematic diagram showing a relationship between an erase oscillation frequency, a control voltage of a variable capacitance diode 37, and a capacitance value of the variable capacitance diode 37 according to a first reference example;
FIG. 3 is a block diagram of an erase circuit of a second reference example of the magnetic recording / reproducing apparatus.
FIG. 4 is a block diagram of an erase circuit of a third reference example of the magnetic recording / reproducing apparatus.
FIG. 5 is a block diagram of an erasing circuit of the magnetic recording / reproducing apparatus according to the embodiment of the present invention.
FIG. 6 is a schematic diagram showing the relationship among PR4 equalization characteristics, a reproduction amplifier band, and an erasing frequency in terms of normalized frequencies.
FIG. 7 is a block diagram of an erasing circuit of a conventional magnetic recording / reproducing apparatus.
FIG. 8 is a simplified schematic block diagram of an erase circuit of a conventional magnetic recording / reproducing apparatus.
FIG. 9 is a block diagram of another erasing circuit of the conventional magnetic recording / reproducing apparatus.
[Explanation of symbols]
5,88 Erase rotary transformer
7,90 Erase head
8,84 Erase amplifier
37,85 Variable capacitance diode
32 divider circuit
33, 81 Phase comparison circuit
34, 86, 48 Low-pass filter
35, 49, 87 Gain adjustment circuit
41 Playback head
42 Rotary transformer for playback
43 Playback amplifier
44 Reproduction equalization circuit
45 Detection circuit
46 Bandpass filter
47 Frequency detection circuit
50 Crosstalk
80 Inversion circuit
101-103 control circuit

Claims (2)

An erasing head for erasing a recording data signal on the magnetic recording medium, a recording head for recording a new recording data signal on the magnetic recording medium simultaneously with an erasing operation by the erasing head, and a new recorded on the magnetic recording medium A reproducing head that simultaneously reproduces a recorded data signal, and an erasing amplifier that supplies an erasing current in which the resonance frequency due to the inductance up to the erasing head and the added capacitance is near the minimum point of the reproduction equalization characteristic,
In case of recording reproducing a plurality of data rates, an input signal for the previous SL erase amplifier, to one of the divided signal or recording clock itself or no input of the recording clock, to have a switching circuit for switching in response to the data rate A magnetic recording / reproducing apparatus.   There are n erase heads, and there are n (n is an integer of 2 or more) erase amplifiers for the n erase heads, and the phase of the recording clock input to the n erase amplifiers is set to each erase head. 2. The magnetic recording / reproducing apparatus according to claim 1, wherein the magnetic recording / reproducing apparatus is shifted by a predetermined amount.

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