JPH06325308A - Reproducing device for digital information - Google Patents

Abstract

PURPOSE:To cope with even plural digital information signals having different bands with simple constitution by flatting a delay characteristic of an equalizer circuit, raising the prescribed band with 12dB/octave, and realizing a sharp high band emphasizing characteristic. CONSTITUTION:In an equalizer circuit 5, the prescribed band is raised by 6dB/ octave, and the circuit 5 is constituted with first and second CR type filters 10, 20 of which a low band side phase characteristic is an inverse characteristic and a CR type active LPF 30 which attenuates component of outside of the band, time constant of these CR type filters can be switched in accordance with plural digital information signals having different quantity of information. Also, for a loop filter 40 in a clock reproducing circuit 7, only capacitors constituting the filter 40 are switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital information signal reproducing apparatus using a partial response detection method, and more particularly to a digital information reproducing apparatus suitable for selecting and reproducing a plurality of signals having different information amounts. .

[0002]

2. Description of the Related Art In recent years, a partial response (hereinafter abbreviated as PR) method has attracted attention as a signal detection method for a reproducing system in a high density digital magnetic recording system. Above all, it is close to the transmission frequency characteristic of the magnetic recording and reproducing system,
The PR class 4 method, which has excellent low-frequency blocking characteristics, is receiving attention. Regarding the PR detection method, see, for example, "Journal of the Television Society", Vol. 42, No. 4 (April 1988) p.
p. 330-337.

On the other hand, a digital image signal is an example of a plurality of digital information signals having different amounts of information. That is, one is a digital image signal of the 525 line / 60 field system or the 625 line / 50 field system (hereinafter referred to as the current digital image signal).
The other is a high-quality digital image signal (hereinafter referred to as an HD digital image signal) of 1125 line / 60 field system or the like.

At present, so-called D1-VTRs, D2-VTRs and the like have been put to practical use as recording devices for current digital image signals. These D1-VTR D
1 format and D2 format for D2-VTR, see, for example, "Journal of Television Society", Vol. 42, N.
o.4 (April 1988) pp. 338-346. Also, as a recording device for HD digital image signals, a digital VTR using a 1-inch tape has been put to practical use.

However, there is no digital VTR capable of recording and reproducing both the current digital image signal and the HD digital image signal with one machine. Here, considering a future home digital VTR, it is naturally desirable that both the current digital image signal and the HD digital image signal can be recorded and reproduced by a common cassette and a common scanner (drum, head).

Now, using the image band compression technique, the information amount of the current digital image signal is set to about 25 to 50 Mb / s, and the information amount of the HD digital image signal is doubled to 50.
Assuming that the data can be compressed to about 100 Mb / s, and if two digital image signals whose information amounts are doubled are recorded and reproduced by one machine, the ratio of the information amount of the two digital image signals becomes Depending on the tape feed speed and drum rotation speed, the recording wavelength and track pitch are kept constant.
That is, a method of keeping the recording density constant can be considered. However, the recording time differs between the current digital image signal and the HD digital image signal.

FIG. 6 is a block diagram showing an example of a reproducing apparatus in the recording / reproducing method. In the figure, 1 is a magnetic tape, 2 is a rotating drum, 3a and 3b are magnetic heads, 4 is an amplifier, 5 is an equalizing circuit, 6 is a (1 + D) arithmetic circuit, 7 is a clock reproducing circuit, and 8 is a three-value discrimination. Circuits, 9 are output terminals, 51a and 51b are equalizer circuits for current and HD digital image signals, 61a and 61b are delay devices, and 65
Is an adder, 71 is a quadratic circuit, 72 is a phase detector, 73
a and 73b are low-pass filters (LP)
F), 74 is a voltage controlled oscillator (Voltage Controlled)
Oscilator; VCO), 75 is a 1/2 divider, S ₅₁ , S
₆₁ , S ₇₁ and S ₇₂ are changeover switches. The operation will be described below.

It is now assumed that the current digital image signal is recorded on the magnetic tape 1. At this time, the changeover switches S ₅₁ , S ₆₁ , S ₇₁ and S ₇₂ are all connected to the side a. The current digital image signal reproduced by the magnetic heads 3a and 3b is amplified to an appropriate level by the amplifier 4 and equalized by the equalizing circuit 51a in the PR (1, -1) system. The characteristic (A) shown in FIG. 7 is an example of the overall frequency characteristic of the recording / reproducing system at this time. Incidentally, T is the bit period of the recorded current digital image signal. Next, the signal equalized by the PR (1, -1) system is composed of a 1-bit delay device 61a and an adder 65 (1+
D) Calculated by the calculation circuit 6 and finally PR class 4
Equalized to the scheme. The characteristic (B) in FIG. 7 is (1 + D)
The frequency characteristic of the arithmetic circuit 6, and the characteristic (C) is the final P
It is an example of the total frequency characteristic after R class 4 system equalization. Needless to say, the characteristic (C) is obtained by multiplying the characteristic (A) by the characteristic (B).

FIG. 8 is a waveform diagram showing this equalization process. Assuming an isolated bit recording signal as shown in (A), the signals reproduced by the magnetic heads 3a and 3b are
As is well known, the waveform becomes as shown in (B) due to various losses. The equalization circuit 51a compensates for these losses, and (C)
Are equalized to a PR (1, -1) system waveform as shown in FIG.
Then, the (1 + D) arithmetic circuit 6 equalizes the PR (1,0, -1) as shown in (D), that is, the waveform of the class 4 system. The signal after this PR class 4 system equalization is 3
It becomes a value signal.

The ternary identification circuit 8 outputs the ternary signal to 4
Multiplier circuit 71, phase detector 72, LPF 73a, VCO 7
The code is discriminated according to the timing of the clock signal regenerated by the clock regenerating circuit 7 including the 4 and 1/2 frequency dividers 75, and the binary original digital information signal is regenerated. Then, the reproduced original digital information signal is output from the output terminal 9.

Next, when reproducing the HD digital image signal recorded on the magnetic tape 1, both the feed speed of the magnetic tape 1 and the number of rotations of the rotary drum 2 are set to double the current digital image, and the changeover switch S ₅₁ , S ₆₁ , S ₇₁ and S ₇₂ are all connected to the side of b, and the HD digital image signal reproduced by the magnetic heads 3a and 3b is similarly amplified by the amplifier 4
Is amplified to an appropriate level by the equalizer circuit 51b, equalized by the equalization circuit 51b by the PR (1, -1) method, and further, a 1-bit delay device 61b (the bit period of the HD digital image signal is T
(1 + D) arithmetic circuit 6 composed of a / 2) and an adder 65
And is finally equalized to the PR class 4 system. Then, the ternary discrimination circuit 8 discriminates the code according to the timing of the clock signal from the clock recovery circuit 7 composed of the quadratic circuit 71, the phase detector 72, the LPF 73b, and the VCO 74, and outputs from the output terminal 9.

[0012]

However, in the above-mentioned prior art, the equalizer circuits 51a and 51b, the 1-bit delay units 61a and 61b, and the LPFs 73a and 73b are used.
Circuits corresponding to the current and HD digital image signals are required. In particular, the equalization circuits 51a and 51b are required to have steep high-frequency emphasis characteristics, and if these are configured by conventional transversal filters, there is a problem that the circuit scale becomes enormous.

The object of the present invention is to solve the above problems,
An object of the present invention is to provide a digital information reproducing apparatus capable of reproducing both the current digital image signal and the HD digital image signal with a simple structure.

[0014]

In order to achieve the above object, in the present invention, a circuit for equalizing by the PR (1, -1) system is raised within a predetermined band by 6 dB / octave, and at the low frequency side. First and second CR type filters having opposite phase characteristics, and CR type active L for attenuating out-of-band components
The time constant of the CR type filter is switched between the current digital image signal and the HD digital image signal. Also, for the loop filter in the clock recovery circuit, only the capacitors that compose it are switched.

Further, the 1-bit delay unit is also composed of a CR type active circuit, and its time constant is switched between the current digital image signal and the HD digital image signal.

[0016]

In the circuit for equalization by the PR (1, -1) system, the phase characteristic is linear (the delay characteristic is flat) and the predetermined band can be raised by 12 dB / octave. Not only the enhancement characteristics can be realized, but also current digital image signals and HD digital image signals having different bands can be easily dealt with by switching the time constants of these filters. Also, regarding the loop filter in the clock recovery circuit, the loop band can be switched corresponding to those signals while the loop gain remains constant by switching only the capacitors that form the loop filter.

Further, by constructing the 1-bit delay device also by the CR type active circuit, the delay time corresponding to 1 bit of each of the current digital image signal and the HD digital image signal can be easily achieved only by switching the time constant. Obtainable.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital information reproducing apparatus according to the present invention, and the same reference numerals as those in FIG. 6 denote the same components. In the figure, the feature of the present invention is that the equalizing circuit 5 is raised within a predetermined band by 6 dB / octave, and the phase characteristics on the low frequency side are opposite characteristics of the first and second C's.
The R-type filters 10 and 20 and the CR-type active LPF 30 that attenuates out-of-band components, and the current digital image signal and the HD digital image signal form capacitors C _11a , C _11b , and C _{21 That is} , _a and C _21b , C _31a and C _31b , and C _32a and C _32b are switched by switching switches S ₁₁ , S ₂₁ , S ₃₁ and S ₃₂ , respectively. Also, regarding the loop filter 40 in the clock recovery circuit 7, only the capacitors C _41a and C _41b forming the loop filter 40 are switched to the switching switch path S _41.
This is because it was switched by. The operation will be described below.

Now, it is assumed that the current digital image signal is recorded on the magnetic tape 1 as in the conventional case. At this time, the changeover switches S ₁₁ , S ₂₁ , S ₃₁ , S ₃₂ and S ₄₁ are closed, the changeover switches S ₆₁ and S ₇₂ are connected to the side of a, and the equalization circuit 5, (1 + D) arithmetic circuit 6, The conditions of each clock recovery circuit 7 are set to the conditions corresponding to the current digital image signal. The current digital image signal reproduced by the magnetic heads 3a, 3b is amplified to an appropriate level by the amplifier 4, and the first, second and third CRs are used.
The equalization circuit 5 including the mold filters 10, 20 and 30 equalizes the PR (1, -1) method. Next, this PR
The signal equalized by the (1, -1) system is equalized by the (1 + D) arithmetic circuit 6 into the PR class 4 system, and coded in accordance with the timing of the clock signal reproduced by the clock reproduction circuit 7 by the ternary discrimination circuit 8. It is identified and output from the output terminal 9.

FIG. 2A is a diagram showing an example of the frequency characteristic of the equalizing circuit 5 at this time, and FIG. 2A shows the first and second C's.
The frequency characteristics of the R-type filters 10 and 20 are shown, and (B) shows the total frequency characteristics including the third CR-type filter 30. That is, the transfer characteristics H _10a (S) and H _20a (S) of the first and second CR filters 10 and 20, respectively.
Is given by the following equation.

[0022]

## EQU1 ## H _10a (S) = A ₁₁ × R ₁₂ / (R ₁₁ + R ₁₂ ) × (1+
ST _10a ) / (1 + ST _20a ), where A ₁₁ is the gain of the buffer amplifier 11, T _10a = (C _11a + C _11b ) × R ₁₁ T _20a = (C _11a + C _11b ) × R ₁₁ × R ₁₂ / (R ₁₁ + R ₁₂ ) <T _10a

[0023]

[Formula 2] H _20a (S) = A ₂₁ × R ₂₃ / (R ₂₂ + R ₂₃ ) × (1-
ST _30a ) / (1 + ST _40a ), where A ₂₁ is the gain of the differential amplifier 21, T _30a = (C _21a + C _21b ) × R ₂₁ × R ₂₃ / R ₂₂ T _40a = (C _21a + C _21b ) × R ₂₁ <T _30a Here, in the present invention, the time constants T _10a and T _30a , and T _20a and T _40a are made approximately equal, whereby CR
Transfer Characteristics H _1a (S) Combining Type Filters 10 and 20
Is given by the following equation.

[0024]

## _EQU3 ## H _1a (S) = K × (1- (ST _1a ) ² ) / (1 + ST _2a ) ² , where K = A ₁₁ × A ₂₁ × R ₁₂ / (R ₁₁ + R ₁₂ ) × R ₂₃ /
(R ₂₂ + R ₂₃ ) T _1a = T _10a = T _30a T _2a = T _20a = T _40a The characteristic (A) in FIG.
The amplitude characteristic | H _1a (f) | of _1a (S) is shown. Thus, from the frequency f _1a (= 1 / 2πT _1a ) to the frequency f
_It has a characteristic of increasing with an inclination of 12 dB / octave in the region of _2a (= 1 / 2πT _2a ). Moreover, the frequency f _1a
Since the imaginary term is canceled in the vicinity of, the phase characteristic is linearized, that is, the delay characteristic is flattened.

The LPF 30 is for attenuating the components outside the required band raised by the CR filters 10 and 20, and its transfer characteristic H _30a (S) is expressed by the following equation.

[0026]

## EQU4 ## H _30a (S) = 1 / (1 + ST _33a + S ² T _31a T _32a ) where 31 is a buffer amplifier with a gain of 1, T _31a = (C _31a + C _31b ) × R ₃₁ T _32a = ( C _32a + C _32b ) × R ₃₂ T _33a = (C _32a + C _32b ) × (R ₃₁ + R ₃₂ ) The characteristic (B) in FIG.
_The total amplitude characteristic of the equalizing circuit 5 including the LPF 30 of _30a (S) is shown. By thus attenuating the noise component outside the required band, the signal-to-noise ratio (S / N) of the reproduced signal is shown. ) Is being improved.

The basic structure of the equalizing circuit composed of the CR type filter and the LPF is first described by the present inventor in Japanese Patent Laid-Open No.
No. 97105, the present invention relates to the frequency of the reproduction signal in such an equalizing circuit,
It is characterized in that the capacitors that are its constituent elements are switched. This will be described below.

When reproducing the HD digital image signal recorded on the magnetic tape 1, the magnetic tape 1 is reproduced as in the conventional example.
The feed speed of the rotary drum 2 and the number of rotations of the rotary drum 2 are twice as high as those of the current digital image, and the switching switches S ₁₁ , S ₂₁ , S ₃₁ ,
S ₃₂ and S ₄₁ are opened, and the changeover switches S ₆₁ and S ₇₂ are connected to the side of b. As a result, the equalization circuit 5, (1+
D) The arithmetic circuit 6 and the clock reproducing circuit 7 are set to the conditions corresponding to the HD digital image signal. The HD digital image signal reproduced by the magnetic heads 3a and 3b and amplified to an appropriate level by the amplifier 4 is equalized by the equalization circuit 5 in the PR (1, -1) system, and further the (1 + D) arithmetic circuit 6 is provided. Is equalized to the PR class 4 system. Then, the ternary identification circuit 8 causes the clock recovery circuit 7
The code is discriminated according to the timing of the clock signal from and output from the output terminal 9.

At this time, the transfer characteristics H _10b (S) and H _20b (S) of the CR filters 10 and 20 and the transfer characteristics H _1b (S) obtained by combining them are expressed by the following equations.

[0030]

[Equation 5] H _10b (S) = A ₁₁ × R ₁₂ / (R ₁₁ + R ₁₂ ) × (1+
ST _10b ) / (1 + ST _20b ), where T _10b = C _11b × R ₁₁ T _20b = C _11b × R ₁₁ × R ₁₂ / (R ₁₁ + R ₁₂ ) <T _10b

[0031]

## _EQU6 ## H _20b (S) = A ₂₁ × R ₂₃ / (R ₂₂ + R ₂₃ ) × (1-
ST _30b ) / (1 + ST _40b ), where T _30b = C _21b × R ₂₁ × R ₂₃ / R ₂₂ T _40b = C _21b × R ₂₁ <T _30b

[0032]

H _1b (S) = K × (1- (ST _1b ) ² ) / (1 + ST _2b ) ² where T _1b = T _10b = T _30b T _2b = T _20b = T _40b FIG. 2B (A) is the transfer characteristic H shown in Equation 7 above.
₂ shows the amplitude characteristic | H _1b (f) | of _1b (S). Here, by setting C _11a and C _11b and C _21a and C _21b to the same value, the frequency bands are all doubled, and the frequency f _1b (= 1 / 2πT _1b =) corresponding to the HD digital image signal is obtained.
A desired equalization characteristic that rises with a slope of 12 dB / octave in the region from 2f _1a ) to the frequency f _2b (= ½πT _2b = 2f _2a ) is realized. Further, the flattening of the delay characteristic in the vicinity of the frequency f _1b is the same as in the reproduction of the current digital image signal.

Similarly, the transfer characteristic H _30b (S) of the LPF 30 is obtained.
Is given by the following equation.

[0034]

H _30b (S) = 1 / (1 + ST _33b + S ² T _31b T _32b ) where T _31b = C _31b × R ₃₁ T _32b = C _32b × R ₃₂ T _33b = C _32b × (R ₃₁ + R ₃₂ ) The characteristic (B) of FIG. 2 (b) is the transfer characteristic H shown in the above equation 8.
_It shows the total amplitude characteristic of the equalization circuit 5 including the LPF 30 of _30b (S). Also here, by setting C _31a and C _31b and C _32a and C _32b to the same value, the noise component outside the required band corresponding to the HD digital image signal is attenuated and the S / N of the reproduced signal is improved. be able to.

Thus, in the equalizing circuit according to the present invention,
Since the delay characteristic is flat and the predetermined band can be raised by 12 dB / octave, not only can a sharp high-frequency emphasis characteristic be realized, but also for a current digital image signal and an HD digital image signal having different bands. The feature is that it can be easily dealt with by switching the capacitors (C) that configure these filters.

Further, in the present invention, as for the loop filter 40 in the clock recovery circuit 7, only the capacitors C _41a and C _41b are switched by the switching switch S ₄₁ . Setting C _41a and C _41b to the same value is the same as that of the equalization circuit 5, so that the loop band can be made to correspond to the current digital image signal and the HD digital image signal respectively while keeping the loop gain constant. You can

FIG. 3 is a block diagram showing another embodiment of the equalization circuit 5 according to the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same things, and 16 and 26 are differential amplifiers. The CR type filters 10 and 20 and the transfer characteristics combining them in the present embodiment are the transfer characteristics H _10a (S), H _20a (S), and H _1a (shown in Expressions 1 to 3 and 5 to 7). S) and H
_It is basically the same as _10b (S), H _20b (S), and H _1b (S), and like the embodiment of FIG.
It goes without saying that desired equalization characteristics corresponding to each D digital image signal can be obtained. The feature of this embodiment is that both terminals of the switching switches S ₁₆ and S ₂₆ are grounded as shown in FIG. As a result, including the switching switch S ₃₂ in the LPF 30,
The feature is that these switching switches can be realized with simple transistors.

FIG. 4 shows a (1 + D) arithmetic circuit 6 according to the present invention.
It is a block diagram which shows the other Example of this. In the figure, 8
Numerals 0 and 85 are delay units constituted by CR type active circuits, so that the total delay time of the delay units 80 and 85 becomes the delay time corresponding to 1 bit of each of the current digital image signal and the HD digital image signal. It is set. Reference numerals 90 and 95 denote active circuits having the same gains as the delay units 80 and 85, and resistors R ₈₃ and R ₉₃ , R ₈₄ and R ₉₄ , R ₈₈ and R ₉₈ , R ₈₉ and R _99, and R ₆₈ and R _69. They are set to the same value. Incidentally, 66, 81, 86,
Reference numerals 91 and 96 are differential amplifiers. The feature of this embodiment is that
As described above, the 1-bit delay device is also composed of the CR type active circuits 80 and 85, and the capacitors are switched between the current digital image signal and the HD digital image signal. This operation will be described below.

First, the operation of the delay devices 80 and 85 will be described. During reproduction of the current digital image signal, the switching switches S ₈₁ , S ₈₂ , S ₈₆ and S ₈₇ are closed, and the transfer characteristics H _80a (S) and H _85a (S) of the delay devices ₈₀ and _{85 at} this time are as follows. It is shown by the formula.

[0040]

[ _Equation 9] H _80a (S) = G ₈₀ × (1-ST _80a + S ² T _81a T _82a ) / (1 + ST _80a + S ² T _81a T _82a ), where G ₈₀ = R ₈₄ / (R ₈₃ + R ₈₄ ). _{(C 82a + C 82b) /} (C 81a + C 81b) = R 83/2 / R 84 × R
₈₂ / (R ₈₁ + R ₈₂ ) T _80a = (C _82a + C _82b ) × (R ₈₁ + R ₈₂ ) T _81a = (C _81a + C _81b ) × R ₈₁ T _82a = (C _82a + C _82b ) × R ₈₂

[0041]

[ _Equation 10] H _85a (S) = G ₈₅ × (1-ST _85a + S ² T _86a T _87a ) / (1 + ST _85a + S ² T _86a T _87a ) However, G ₈₅ = R ₈₉ / (R ₈₈ + R ₈₉ ) _{(C 87a + C 87b) /} (C 86a + C 86b) = R 88/2 / R 89 × R
_{87 / (R 86 + R 87} ) T 85a = (C 87a + C 87b) × (R 86 + R 87) T 86a = (C 86a + C 86b) × R 86 T 87a = (C 87a + C 87b) × R 87 above number 9, transfer characteristics H _80a (S), H shown in _equation 10
The amplitude characteristics | H _80a (f) | and | H _85a (f) | of _85a (S) are constant at the gains G ₈₀ and G ₈₅ , respectively, over the entire band. By selecting them, the delay flatness characteristics of the delay times T _80a and T _85a can be realized respectively.
Therefore, if the total delay time obtained by adding T _80a and T _85a is matched with the 1-bit period of the current digital image signal, a 1-bit delay device corresponding to the current digital image signal can be realized.

The signals thus obtained are passed through the delay devices 80 and 85 having a delay time corresponding to 1 bit of the current digital image signal in total, and the delay devices 80 and 8
Active circuits 90 and 9 in which the gain is set equal to 5
The signal passed through 5 is added by the adder 65, and the operation of (1 + D) is performed.

On the other hand, when the HD digital image signal is reproduced, the switching switches S ₈₁ , S ₈₂ , S ₈₆ and S ₈₇ are opened,
C _81a and C _81b , C _82a and C _82b , C _86a and C _86b and C _87a
Since C _87b and C _87b are set equal to each other, the total delay time of the delay units 80 and 85 is halved. Therefore, a 1-bit delay device corresponding to the HD digital image signal can be realized, and a predetermined (1 + D) operation can be performed.

The transfer characteristics H _80b (S) and H _85b (S) of the delay devices ₈₀ and _{85 at} this time are expressed by the following equations.

[0045]

Equation 11] _{H 80b (S) = G 80} × (1-ST 80b + S 2 T 81b T 82b) / (1 + ST 80b + S 2 T 81b T 82b) _{However, C 82b / C 81b = R} 83/2 / R ₈₄ x R ₈₂ / (R ₈₁
+ R ₈₂ ) T _80b = C _82b × (R ₈₁ + R ₈₂ ) T _81b = C _81b × R ₈₁ T _82b = C _82b × R ₈₂

[0046]

Equation 12] _{H 85b (S) = G 85} × (1-ST 85b + S 2 T 86b T 87b) / (1 + ST 85b + S 2 T 86b T 87b) _{However, C 87b / C 86b = R} 88/2 / R ₈₉ x R ₈₇ / (R ₈₆
+ R ₈₇ ) T _85b = C _87b × (R ₈₆ + R ₈₇ ) T _86b = C _86b × R ₈₆ T _87b = C _87b × R ₈₇ Thus, the 1-bit delay unit is also configured by the CR-type active circuit. Thus, the delay time corresponding to 1 bit of each of the current digital image signal and the HD digital image signal can be easily obtained only by switching the capacitor, and as a result, the delay time of (1+
D) An arithmetic circuit can be realized.

FIG. 5 is a block diagram showing another embodiment of the digital information reproducing apparatus according to the present invention. In the figure, 1
00 is an A / D converter, 110 is a digital adder, 11
Reference numeral 1 denotes a digital delay device, 120 denotes a Viterbi decoding circuit, and the same reference numerals as those in FIG. 1 denote the same components. The feature of this embodiment is that the output signal of the equalization circuit 5 is
A / D converter 100 performs analog-digital conversion,
(1 + D) operation is performed digitally, PR class 4
The point is that the signal equalized by the method is subjected to maximum likelihood decoding by the Viterbi decoding circuit 120. The processes of the A / D converter 100, the digital adder 110, the digital delay unit 111, and the Viterbi decoding circuit 120 are performed by the clock recovery circuit 7. Is performed in accordance with the timing of the clock signal. This allows
The digital delay device 111 has a feature that only one simple latch circuit is required and the operation of switching the delay time is also unnecessary. Further, since the maximum likelihood decoding is performed by the Viterbi decoding circuit 120, the code error rate can be improved as compared with the normal decoding for each bit.

By the way, in the above embodiment, the magnetic tape 1 is used.
The signal recorded in the current digital image signal or HD
Although the means for detecting whether it is a digital image signal is not particularly described, it may be detected, for example, by the running speed of the magnetic tape 1 or the number of rotations of the rotating drum 2, or the frequency band of the reproduction signal may be detected. . The present invention is characterized in that the time constant of the circuit composed of CR is switched by using the result of such detecting means, and is not limited to such detecting means.

In the above embodiments, the application of the present invention to a digital magnetic recording / reproducing system using a magnetic tape has been described, but the present invention is not limited to this, and PR class 4 system or It can be applied to any system as long as it uses an extended detection method, for example, a digital recording / reproducing system using a magnetic disk or an optical disk.

[0050]

As described above, according to the present invention, it is suitable for detecting a plurality of digital information signals recorded on a recording medium and having different amounts of information by using the partial response class 4 system, and It is possible to realize a digital information reproducing device having a simple structure.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital information reproducing apparatus according to the present invention.

FIG. 2 is a diagram showing frequency characteristics of an equalizing circuit according to the present invention.

FIG. 3 is a configuration diagram showing another embodiment of the equalization circuit according to the present invention.

FIG. 4 is a configuration diagram showing another embodiment of a (1 + D) arithmetic circuit according to the present invention.

FIG. 5 is a configuration diagram showing another embodiment of the digital information reproducing apparatus according to the present invention.

FIG. 6 is a block diagram showing an example of a conventional digital information reproducing apparatus.

FIG. 7 is a diagram showing frequency characteristics of a partial response class 4 system.

FIG. 8 is a waveform diagram showing the equalization process of the partial response class 4 system.

[Explanation of symbols]

5 ... Equalization circuit, 6 ... (1 + D) arithmetic circuit, 7 ... Clock recovery circuit, 8 ... Tri-level identification circuit, 10, 20 ... CR type filter, 30 ... CR type active LPF, 40 ... Loop
Filter, 80, 85 ... CR type delay circuit.

Claims (5)

[Claims] 1. A reproducing means for reproducing a digital information signal recorded on a recording medium, and an output signal of the reproducing means for a partial response PR.
Operation for performing (1 + D) operation by adding equalization means for performing equalization so as to obtain a (1, -1) type signal, and an output signal of the equalization means and a signal obtained by delaying the output signal by 1 bit. Means, a decoding means for identifying and decoding the original digital information signal from the output signal of the computing means, and a clock signal for identifying and decoding the original digital information signal from the output signal of the equalizing means. A digital information reproducing apparatus for detecting the digital information signal recorded on the recording medium by using a partial response method, the clock reproducing means for supplying the clock signal to the decoding means, and the equalizing means. Is a proportional constant (K), a first time constant (T ₁ ), a second time constant (T ₂ ) smaller than the first time constant, and a third time value substantially equal to the first time constant. time constant constant (T _3), when said third The smaller the fourth time constant (T ₄₎ Ri, H (S) = K × (1 + ST 1) / (1 + ST 2) × (1-ST 3)
A circuit network having a transfer characteristic (H (S)) defined by the expression / (1 + ST ₄ ) is provided, and the computing means includes delay means for delaying the output signal of the equalizing means by 1 bit, and the like. The clock regenerating means comprises a voltage controlled oscillating means for outputting the clock signal, and an adding means for adding the output signal of the equalizing means and the output signal of the delaying means, and the digital information from the output signal of the equalizing means. A clock component extracting means for extracting a bit frequency component of the signal; a phase detecting means for detecting a phase difference between the output signal of the voltage controlled oscillating means and the output signal of the clock component extracting means; and an output signal of the phase detecting means. A first time constant (T ₁ ) and a second time constant according to the bandwidth of the reproduced digital information signal. (T _2), the 3
Of the time constant (T ₃ ), the fourth time constant (T ₄ ), the oscillation frequency of the voltage controlled oscillation means, the time constant of the filter means, and the delay time of the delay means. And a digital information reproducing device. 2. The delay unit according to claim 1, wherein the delay means includes a second proportional constant (K ₂ ), a fifth time constant (T ₅ ), a sixth time constant (T ₆ ), and a seventh time constant (T ₆ ). And the time constant (T ₇ ) of H ₂ (S) = K ₂ × (1-ST ₅ + S ² T ₆ T ₇ ) / (1 + ST ₅ +
S ² T ₆ T ₇ ) A circuit network having a _second transfer characteristic (H ₂ (S)) defined by the formula S ² T ₆ T ₇ ) is provided, and according to the bandwidth of the reproduced digital information signal,
A digital information reproducing apparatus characterized in that the fifth time constant (T ₅ ), the sixth time constant (T ₆ ) and the seventh time constant (T ₇ ) are switched. 3. A first digital information signal having a first information amount recorded on a recording medium or a second digital information signal having an information amount twice as large as the first information amount is reproduced. Partial response PR of the reproducing means and the output signal of the reproducing means
Operation for performing (1 + D) operation by adding equalization means for performing equalization so as to obtain a (1, -1) type signal, and an output signal of the equalization means and a signal obtained by delaying the output signal by 1 bit. Means, identifying means for identifying and decoding the original first digital information signal or second digital information signal from the output signal of the computing means, and the original first digital information from the output signal of the equalizing means. A clock signal for reproducing a clock signal for identifying and decoding the signal or the second digital information signal and supplying the clock signal to the identifying means; and a signal recorded on the recording medium for the first digital signal. An information signal or a second digital information signal is detected, and the first digital information signal or the second digital information signal recorded on the recording medium is used in a partial response system. A digital information reproducing apparatus which detects and, equalized means includes a proportional constant (K), a first time constant (T _1), the time constant is smaller than the second time of the first constant ( by the T _2), and generally in the case of the first constant equal third time constant (T _3), the time constant is smaller than a fourth time constant of said _{3 (T 4), H (} S) = K × (1 + ST ₁ ) / (1 + ST ₂ ) × (1-ST ₃ )
A circuit network having a transfer characteristic (H (S)) defined by the expression / (1 + ST ₄ ) is provided, and the computing means includes delay means for delaying the output signal of the equalizing means by 1 bit, and the like. The clock regenerating means comprises a voltage controlled oscillating means for outputting the clock signal and an output signal of the equalizing means to the fourth power. Means, a phase detection means for detecting a phase difference between the output signal of the voltage controlled oscillation means and the output signal of the fourth power means, and an output signal of the phase detection means for outputting a control signal of the voltage controlled oscillation means Filter means for performing the first time constant (T ₁ ), the second time constant (T ₂ ), and the third time constant (T ₂ ) according to the output signal of the detection means.
₃ ) and the fourth time constant (T ₄ ), the oscillation frequency of the voltage controlled oscillation means, the time constant of the filter means, and the delay time of the delay means are switched. apparatus. 4. The delay unit according to claim 3, wherein the delay unit includes a second proportional constant (K ₂ ), a fifth time constant (T ₅ ), a sixth time constant (T ₆ ), and a seventh time constant (T ₆ ). And the time constant (T ₇ ) of H ₂ (S) = K ₂ × (1-ST ₅ + S ² T ₆ T ₇ ) / (1 + ST ₅ +
S ² T ₆ T ₇ ) A circuit network having a _second transfer characteristic (H ₂ (S)) defined by the equation: S ² T ₆ T ₇ ) is provided, and the fifth time constant (T ₅ ), The sixth time constant (T ₆ ) and the seventh time constant (T ₇ ) are switched. 5. The image information signal according to claim 3 or 4, wherein the first digital information signal is an image information signal of 525 line / 60 field system or 625 line / 50 field system, and the second digital information signal is 1125 line. A digital information reproducing apparatus characterized by being a high-quality image information signal of a / 60 field system or the like.