KR940012106A - Lead / Write Control Circuit of Hard Disk Driver - Google Patents

Lead / Write Control Circuit of Hard Disk Driver Download PDF

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Publication number
KR940012106A
KR940012106A KR1019920021812A KR920021812A KR940012106A KR 940012106 A KR940012106 A KR 940012106A KR 1019920021812 A KR1019920021812 A KR 1019920021812A KR 920021812 A KR920021812 A KR 920021812A KR 940012106 A KR940012106 A KR 940012106A
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KR
South Korea
Prior art keywords
outputting
output
signal
circuit
peak detector
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KR1019920021812A
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Korean (ko)
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KR100242286B1 (en
Inventor
오흥민
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정용문
삼성전자 주식회사
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Priority to KR1019920021812A priority Critical patent/KR100242286B1/en
Publication of KR940012106A publication Critical patent/KR940012106A/en
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Publication of KR100242286B1 publication Critical patent/KR100242286B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Digital Magnetic Recording (AREA)

Abstract

하드디스크 드라이버(HDD)의 리이드/파이트 채널 최적화 제어회로에 관한 것으로, 특히 원칩(One-chip)화하여 미디어(Media)로 부터 픽업 출력되는 신호의 노이즈를 최적 상태로 감소하도록 한 회로에 관한 것이다.The present invention relates to a lead / fight channel optimization control circuit of a hard disk driver (HDD), and more particularly to a circuit in which one-chip is used to reduce noise of a signal picked up and output from media to an optimal state. .

상기의 하드디스크 드라이버(HDD)의 리이드/라이트 채널 최적화 제어회로는 상기 프리 앰프(12)에서 소정레벨로 증폭 출력되는 아나로그 신호를 일정한 전압레벨의 신호로 유지 출력하는 가변 이득 증폭기(14)와, 상기 가변 이득 증폭기(14)로 부터 일정 전압레벨로 유지 출력되는 아나로그 신호를 파형 정형하여 디지탈 신호를 출력하는 피이크 검출기(18)와, 상기 피이크 검출기(18)의 출력을 내부의 기준 클럭에 동기화하여 출력하는 동기화회로(20)와, 기록되어질 데이터를 주파수 변조하여 고밀도 기록 신호를 출력하는 합성회로(22)와, 상기 동기화회로(20)와, 상기 합성회로(22)의 출력중 하나를 출력하는 멀티플랙서(26)와, 상기,MUX(26)의 출력중 라이드데이터를 디코딩하여 출력하고, 기록 데이터를 엔코딩하여 출력하는 엔코더/디코더(24)와, 피이크 검출기(18)는 아나로그 신호를 파형 정형하여 디지탈 신호로 출력하는 히스테리스시 증록기(18b)와 비분기(18a)의 출력에 의한 원-쇼트 펄슬르 출력하는 원-쇼트발생기(18c)가 하나의 칩에 내장되어진다.The lead / right channel optimization control circuit of the hard disk driver (HDD) includes a variable gain amplifier 14 which maintains and outputs an analog signal amplified and output from the preamplifier 12 to a predetermined level as a signal having a constant voltage level. And a peak detector 18 for waveform shaping the analog signal maintained at a constant voltage level from the variable gain amplifier 14 and outputting a digital signal, and outputting the output of the peak detector 18 to an internal reference clock. A synchronizing circuit 20 for synchronizing and outputting, a synthesizing circuit 22 for outputting a high density recording signal by frequency-modulating the data to be recorded, one of the synchronizing circuit 20 and an output of the synthesizing circuit 22 A multiplexer 26 for outputting, an encoder / decoder 24 for decoding and outputting ride data of the output of the MUX 26, and encoding and outputting recording data, and a peak detector 1 8) shows that the hysteresis amplifier 18b for waveform shaping the analog signal and outputting it as a digital signal and the one-short generator 18c for outputting one-short pulses by the output of the non-branch 18a are one chip. Is built in.

Description

하드디스크 드라이버의 리이드/라이트 제어회로Lead / Write Control Circuit of Hard Disk Driver

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 하드디스크 드라이버의 리이드/라이트 제어회로도.1 is a lead / write control circuit diagram of a hard disk driver according to the present invention.

Claims (1)

헤드로 부터 픽업 출력된느 신호를 소정의 레벨로 증폭 출력하는 프리 앰트(12)를 구비한 하드디스크 드라이버의 리이드/라이트 제어회로에 있어서, 상기 프리 앰프(12)에서 소정 레벨로 증폭 출력되는 아나로그 신호를 일정한 전압레벨의 신호로 유지 출력하는 가변 이득 증폭기(14)와, 상기 가변 이득 증폭기(14)로 부터 일정 전압레벨로 유지 출력되는 아나로그 신홀르 파형 정형하여 디지탈 신호로 출력하는 피이크 검출기(18)와, 상기 피이크 검출기(18)의 출력을 내부의 기준 클럭에 동기화하여 출력하는 동기화회로(20)와, 기록되어질 데이터를 주파수 변조하여 고밀도 기록 신호를 출력하는 합성회로(22)와, 상기 동기화회로(20)와, 상기 합성회로 (22)의 출력중하나를 출렵하는 멀티플렉서(260와, 상기 MUX(26)의 출력중 라이드 데이터를 디코딩하여 출력하고, 기록 데이터를 엔코딩하여 출력하는 엔코더/디코더(24)와, 피이크 검출기(18)는 아나로그 신호를 파형 정형하여 디지탈 신호로 출력하는 히스테리시스 증폭기(18b)와, 상기 아나로그 신호를 미분 출력하는 미분기(18a)와, 상기 히스테리시스 증폭기(18b)와 미분기(18a)의 출력에 의한 원-쇼트 펄스를 출력하는 원-쇼트발생기(18c)로 구성됨을 특징으로 하는 하드디스크 드라이버의 리이드/라이트 제어회로A read / write control circuit of a hard disk driver having a preamplifier 12 for amplifying and outputting a signal picked up and outputted from a head to a predetermined level, wherein the amplifier is amplified and output at a predetermined level by the preamplifier 12. A variable gain amplifier 14 for holding and outputting a log signal as a signal having a constant voltage level, and a peak detector for shaping and outputting an analog sinhol waveform maintained at a constant voltage level from the variable gain amplifier 14 and outputting it as a digital signal. 18, a synchronizing circuit 20 for synchronizing the output of the peak detector 18 with an internal reference clock, and a synthesizing circuit 22 for frequency-modulating the data to be recorded to output a high density recording signal; A multiplexer 260 for outputting one of the synchronization circuit 20 and one of the outputs of the synthesis circuit 22, and decodes and outputs ride data among the outputs of the MUX 26; The encoder / decoder 24 for encoding and outputting recording data, the peak detector 18 waveform-forms a hysteresis amplifier 18b for waveform-shaping the analog signal and outputting it as a digital signal, and a differential for outputting the analog signal differentially. 18a), and a one-short generator 18c for outputting a one-short pulse by the output of the hysteresis amplifier 18b and the differentiator 18a. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920021812A 1992-11-19 1992-11-19 A r/w control circuit of hdd KR100242286B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920021812A KR100242286B1 (en) 1992-11-19 1992-11-19 A r/w control circuit of hdd

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920021812A KR100242286B1 (en) 1992-11-19 1992-11-19 A r/w control circuit of hdd

Publications (2)

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KR940012106A true KR940012106A (en) 1994-06-22
KR100242286B1 KR100242286B1 (en) 2000-02-01

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KR1019920021812A KR100242286B1 (en) 1992-11-19 1992-11-19 A r/w control circuit of hdd

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970071201A (en) * 1996-04-04 1997-11-07 윌리엄 비. 켐플러 Data Synchronization Method and Circuit Using Timeout Counter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970071201A (en) * 1996-04-04 1997-11-07 윌리엄 비. 켐플러 Data Synchronization Method and Circuit Using Timeout Counter

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KR100242286B1 (en) 2000-02-01

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