KR100239283B1 - Process for depositing highly doped polysilicon layer on stepped surface of semiconductor wafer resulting in enhanced step coverage - Google Patents

Process for depositing highly doped polysilicon layer on stepped surface of semiconductor wafer resulting in enhanced step coverage Download PDF

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Publication number
KR100239283B1
KR100239283B1 KR1019910012097A KR910012097A KR100239283B1 KR 100239283 B1 KR100239283 B1 KR 100239283B1 KR 1019910012097 A KR1019910012097 A KR 1019910012097A KR 910012097 A KR910012097 A KR 910012097A KR 100239283 B1 KR100239283 B1 KR 100239283B1
Authority
KR
South Korea
Prior art keywords
semiconductor wafer
polysilicon layer
doped polysilicon
highly doped
stepped surface
Prior art date
Application number
KR1019910012097A
Other languages
English (en)
Other versions
KR920003413A (ko
Inventor
Beinglass Sirael
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of KR920003413A publication Critical patent/KR920003413A/ko
Application granted granted Critical
Publication of KR100239283B1 publication Critical patent/KR100239283B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019910012097A 1990-07-16 1991-07-16 Process for depositing highly doped polysilicon layer on stepped surface of semiconductor wafer resulting in enhanced step coverage KR100239283B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57228090A 1990-07-16 1990-07-16
US07/572,280 1990-07-16

Publications (2)

Publication Number Publication Date
KR920003413A KR920003413A (ko) 1992-02-29
KR100239283B1 true KR100239283B1 (en) 2000-01-15

Family

ID=24287122

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910012097A KR100239283B1 (en) 1990-07-16 1991-07-16 Process for depositing highly doped polysilicon layer on stepped surface of semiconductor wafer resulting in enhanced step coverage

Country Status (4)

Country Link
EP (1) EP0467190B1 (ko)
JP (1) JP2602375B2 (ko)
KR (1) KR100239283B1 (ko)
DE (1) DE69125215T2 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0639856A1 (en) * 1993-08-20 1995-02-22 Texas Instruments Incorporated Method of doping a polysilicon layer and semiconductor device obtained
KR100250744B1 (ko) * 1996-06-21 2000-05-01 김영환 반도체 소자의 폴리사이드층 형성 방법
DE69739202D1 (de) 1997-11-14 2009-02-26 St Microelectronics Srl Verfahren zur Abscheidung von in-situ dotierten Polysilizium-Schichten
US6905963B2 (en) 2001-10-05 2005-06-14 Hitachi Kokusai Electric, Inc. Fabrication of B-doped silicon film by LPCVD method using BCI3 and SiH4 gases
FI124354B (fi) 2011-04-04 2014-07-15 Okmetic Oyj Menetelmä yhden tai useamman polykiteisen piikerroksen pinnoittamiseksi substraatille
CN110416322A (zh) * 2019-06-21 2019-11-05 天津爱旭太阳能科技有限公司 一种叠层钝化结构及其制备方法和太阳能电池

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4977104A (en) * 1988-06-01 1990-12-11 Matsushita Electric Industrial Co., Ltd. Method for producing a semiconductor device by filling hollows with thermally decomposed doped and undoped polysilicon

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59138332A (ja) * 1983-01-28 1984-08-08 Seiko Instr & Electronics Ltd 半導体装置の製造方法
US4626317A (en) * 1985-04-03 1986-12-02 Advanced Micro Devices, Inc. Method for planarizing an isolation slot in an integrated circuit structure
US4650696A (en) * 1985-10-01 1987-03-17 Harris Corporation Process using tungsten for multilevel metallization
JPS6425424A (en) * 1987-07-21 1989-01-27 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH0234917A (ja) * 1988-07-25 1990-02-05 Kokusai Electric Co Ltd 低濃度リンドープポリシリコン膜形成法
JPH02165663A (ja) * 1988-12-20 1990-06-26 Sharp Corp 半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4977104A (en) * 1988-06-01 1990-12-11 Matsushita Electric Industrial Co., Ltd. Method for producing a semiconductor device by filling hollows with thermally decomposed doped and undoped polysilicon

Also Published As

Publication number Publication date
EP0467190A3 (en) 1992-11-19
DE69125215T2 (de) 1997-08-28
EP0467190A2 (en) 1992-01-22
JP2602375B2 (ja) 1997-04-23
EP0467190B1 (en) 1997-03-19
DE69125215D1 (de) 1997-04-24
KR920003413A (ko) 1992-02-29
JPH0562904A (ja) 1993-03-12

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