KR100238308B1 - Panorama acting apparatus using a digital filer and method for producting the tendency constant of horizontal pixel - Google Patents

Abstract

Disclosed are a panorama realization apparatus using a digital filter and a method of calculating a horizontal pixel deflection coefficient according to the present invention.

함수의 특성에 따라, 상기 제1라인메모리에 저장된 각각의 수평픽셀에 대한 편향속도를 산출하여, 현재 수평픽셀과 이전수평픽셀에 대한 편향속도를 가산한 후, 정수의 차에 해당하는 픽셀의 화소값에 소수의 비율을 승산한 값과 이전화소값에 1-소수의 비율을 승산한 값을 가산하는 방식으로, 새로운 화소값을 산출하는 디지털 수평픽셀 편향속도 조정필터를 포함한다.A first line memory for storing respective pixel values of horizontal pixels of one line of the digital image signal; And a predetermined pixel of the center portion of the screen is horizontally compressed so that a predetermined number of pixels on the left and right corners of the screen are horizontally stretched for each horizontal pixel stored in the first line memory. To make it faster,

According to the characteristic of the function, the deflection speed for each horizontal pixel stored in the first line memory is calculated, the deflection speed for the current horizontal pixel and the previous horizontal pixel is added, and then the pixel of the pixel corresponding to the difference of integers is added. And a digital horizontal pixel deflection speed adjustment filter that calculates a new pixel value by adding a value obtained by multiplying a value by a fractional ratio and a previous pixel value by a multiplier of a ratio of 1 to a decimal number.

Therefore, as described above, according to the present invention, by adjusting the horizontal compression and extension section and the deflection coefficient of the horizontal pixel accordingly, various panorama modes can be realized.

Description

Panoramic acting apparatus using a digital filer and method for producting the tendency constant of horizontal pixel}

The present invention relates to a panorama realization apparatus for displaying a general video signal having a 4: 3 aspect ratio to a wide screen having a 16: 9 aspect ratio, and a horizontal deflection coefficient calculation method according thereto, in particular a panorama implementation apparatus that is digitally processed and Accordingly, the present invention relates to a horizontal deflection coefficient calculation method.

When a general video signal is inputted to a video reproducing apparatus having a wide screen, since the horizontal synchronization time is the same and the screen size is long, the displayed image is spread out and displayed in the horizontal direction. Therefore, the phenomenon of spreading laterally than the normal screen occurs.

The panorama implementer is a means for solving a phenomenon in which a screen spreads in a horizontal direction when providing a general video signal having a 4: 3 aspect ratio to a wide screen having a 16: 9 aspect ratio. That is, by slowing down the deflection speed of the pixels scattered on the left and right corners of the screen and increasing the deflection speed of the pixels scattered on the central portion, the screen is prevented from spreading in the horizontal direction and displayed like the original screen. 1A shows a screen before application to a panorama implementation, and FIG. 1B shows a screen after application to the panorama implementation. When the panorama implementer is used to display a general video signal on a wide screen, the screen may be prevented from spreading horizontally. In this case, increasing the deflection speed means compressing the original video signal, and slowing the deflection speed means extending the original video signal.

Conventional panorama implementer has a problem that it is difficult to implement and difficult to realize various modes because the deflection speed is adjusted by the analog method.

The present invention was created to solve the above-mentioned problem, and has a effect of varying the deflection speed with respect to horizontal pixels using a digital filter for implementing a panorama function, thereby preventing the screen from spreading sideways. The second object is to provide a method for providing a method for calculating a deflection coefficient of the horizontal pixel according to the first object.

1 is a diagram illustrating a screen before application and a screen after application to a panorama implementation.

2 is a view illustrating a panorama implementation apparatus using a panorama implementation filter according to the present invention.

3 is a detailed view of the digital horizontal pixel deflection speed adjustment filter shown in FIG.

4 is a diagram illustrating a detailed configuration of the panorama implementation shown in FIG.

FIG. 5 is a diagram illustrating a characteristic curve of a deflection coefficient calculation unit shown in FIG. 3.

FIG. 6 is a diagram illustrating a hardware configuration of the first deflection coefficient calculation unit illustrated in FIG. 4.

FIG. 7 is a diagram illustrating a hardware configuration of the second deflection coefficient calculation unit illustrated in FIG. 4.

8 is a view for explaining a method of calculating a deflection coefficient for a horizontal pixel in a digital filter for a panoramic function according to the present invention.

The panorama realization device according to the present invention for achieving the first object is

함수의 특성에 따라, 상기 제1라인메모리에 저장된 각각의 수평픽셀에 대한 편향속도를 산출하여, 현재 수평픽셀과 이전수평픽셀에 대한 편향속도를 가산한 후, 정수의 차에 해당하는 픽셀의 화소값에 소수의 비율을 승산한 값과 이전화소값에 1-소수의 비율을 승산한 값을 가산하는 방식으로, 새로운 화소값을 산출하는 디지털 수평픽셀 편향속도 조정필터를 포함하는 것이 바람직하다.A first line memory for storing respective pixel values of horizontal pixels of one line of the digital image signal; And

According to the characteristic of the function, the deflection speed for each horizontal pixel stored in the first line memory is calculated, the deflection speed for the current horizontal pixel and the previous horizontal pixel is added, and then the pixel of the pixel corresponding to the difference of integers is added. It is preferable to include a digital horizontal pixel deflection speed adjustment filter that calculates a new pixel value by adding a value obtained by multiplying a value by a fractional ratio and a previous pixel value by a multiplier of a ratio of 1-number.

The digital horizontal pixel deflection speed adjustment filter includes: a deflection coefficient calculation unit configured to determine respective deflection speeds with respect to the horizontal pixel; A first calculation unit which calculates an integer part and a decimal part by adding a deflection speed with respect to a current horizontal pixel and a previous horizontal pixel output from the deflection coefficient calculation part, and extracts a difference between the integer parts; And a pixel value of a pixel corresponding to the difference of the integer part extracted by the first operation unit from the first line memory, and multiplies the read pixel value by a predetermined ratio of the fractional part to the horizontal pixel of the input image signal. And a second operation unit for determining a new pixel value.

The deflection coefficient calculation unit comprises: a first deflection coefficient calculation unit calculating a rising curve deflection coefficient of the X ² function; A second deflection coefficient calculation unit for calculating a falling curve deflection coefficient of the X ² function; A selection unit for selecting output values of the first deflection coefficient calculating unit and the second deflection coefficient calculating unit according to a predetermined selection signal (sel signal); And an adder for summing output values of the selection unit and the deflection coefficients interpolated at a predetermined ratio.

에 의해 산출되며, 제2편향계수산출부는

에 의해 산출된다.When the first deflection coefficient calculation unit is the deflection velocity of X _K = K th pixel,

Calculated by the second deflection coefficient calculation unit

Calculated by

The first deflection coefficient calculation unit comprises: first delay means for delaying the input signal by one clock; Second delay means for delaying the output of the first delay means by one clock; Third delay means for delaying the output of the second delay means by one clock; A first adder for adding an output of said first delay means and a deflection speed coefficient (X); A logical AND gate which ANDs the output of the first adder and the pixel start signal PSTART; A second adder for adding the output of the first delay means and the output of the second delay means; A third adder for adding the output of the second delay means and the output of the third delay means; And a flip-flop for holding the output signal of the third adder by a predetermined hold signal, wherein the second deflection coefficient calculating unit sequentially down counts the final value of the first deflection coefficient calculating unit; A subtractor for subtracting "1" from the output value of the down counter; A multiplier for multiplying " 2 " by the output value of the subtractor; An adder for adding the X ² of the output value of the multiplier 1 and X ² or a conservative value that a given lowering of the cost hold the rising portion of the curve; And a deflip-flop for holding an output value of the adder.

The first operation unit comprises: an adder for adding the output value of the deflection coefficient calculation unit and a previous value delayed by one clock through a predetermined delay unit; An integer / fraction separator separating the integer part and the fractional part by inputting the addition result of the adder; And a difference extracting unit extracting a difference by subtracting a previous value and an integer part separated from the positive / fraction separator and outputting a read signal for reading a pixel value corresponding to the extracted pixel position, the second calculating unit A first multiplier that multiplies the pixel value of the pixel read from the first line memory by the read signal of the first operator and the ratio of the fractional part output from the integer / fraction separator of the first operator; A second multiplier for multiplying the ratio of the one-decimal portion by the pixel value of the previous pixel position by which the input pixel of the first multiplier delayed by the predetermined delayer is delayed by one clock; And an adder for adding output pixel values of the first multiplier and the second multiplier.

According to an aspect of the present invention, there is provided a method of calculating a deflection coefficient for a horizontal pixel, the method comprising: setting a compression and interpolation interval for a horizontal pixel in consideration of the horizontal pixel of a screen to be displayed; And calculating a deflection coefficient of the set compression and interpolation section.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

2 is a view illustrating a panorama implementation apparatus using a panorama implementation filter according to the present invention.

In the apparatus shown in FIG. 2, each pixel value for a horizontal pixel of an image signal of one line output from an analog / digital converter 20 and an analog / digital converter 20 for converting an input analog video signal into a digital signal The first line memory 22, which stores the first line memory 22 and the horizontal pixels stored in the first line memory 22, expands horizontally to slow down the deflection speed. The second horizontal line 26 stores the pixel value output from the digital horizontal pixel deflection rate adjustment filter 24 and the digital horizontal pixel deflection rate adjustment filter 24 for calculating a new pixel value so as to increase the speed. It includes.

3 is a detailed view of the digital horizontal pixel deflection speed adjustment filter shown in FIG.

The apparatus shown in FIG. 3 includes a deflection coefficient calculation unit 240 for determining respective deflection speeds for the horizontal pixels, a deflection coefficient of the current horizontal pixel output from the deflection coefficient calculation unit 240, and a deflection coefficient for the previous horizontal pixel. The pixel values of pixels corresponding to the difference between the first operation unit 242 and the integer unit extracted from the first operation unit 242 and the first operation unit 242 are calculated by adding coefficients to calculate the integer unit and the decimal unit. And a second operation unit 244 for determining a new pixel value for the horizontal pixel of the input image signal by multiplying the pixel value of the read pixel by a predetermined ratio. Here, the deflection coefficient calculation unit 240 calculates a deflection coefficient for the horizontal pixel through compression and interpolation so that each horizontal pixel of one line has a different deflection speed. The deflection coefficient calculation unit 240 has a characteristic of an X ² function as shown in FIG. 5 for each horizontal pixel.

4 is a diagram illustrating a detailed configuration of the panorama implementation shown in FIG.

In the apparatus shown in FIG. 4, the deflection coefficient calculation unit 240 calculates the first deflection coefficient calculation unit 240a for calculating the deflection coefficient of the rising curve shown in FIG. 5, and the second deflection coefficient of the falling curve. Selection unit 240c and a selection unit for selecting output values of the first deflection coefficient calculation unit 240a and the second deflection coefficient calculation unit 240b according to the deflection coefficient calculation unit 240b and the predetermined selection signal (sel signal). And an adder 240d for summing up the output value of 240c and the interpolation speed interpolated at a predetermined ratio. In addition, the first operator 242 inputs the addition result of the adder 242a and the adder 242a to add the output value of the adder 240d and the previous value delayed by one clock through the delayer 242b, and then the integer part and the decimal part. A lead signal for extracting a difference by subtracting the integer and the previous value separated from the integer / fraction separator 242c and the integer / fraction separator 242c separated by a value and reading the pixel value corresponding to the extracted pixel position. It consists of a differential extraction unit 242d for outputting. In addition, the second operation unit 244 is a pixel value of the pixel read from the first line memory 22 by the read signal of the difference extraction unit 242d and the integer / fraction separator 242c of the first operation unit 242. The ratio of the pixel value of the first pixel position where the input pixel of the first multiplier 244a, which is delayed by the delayer 244b, to which the input pixel of the first multiplier 244a is delayed by one clock, And a second multiplier 244c for multiplying and an adder 244d for adding output pixel values of the first multiplier 244a and the second multiplier 244c.

The rising curve of the X ² function calculated by the first deflection coefficient calculation unit 240a is calculated by Equation 1 below.

X _K is a deflection coefficient of the K th pixel.

For example, the pixel's deflection coefficients X _0, X _1, X _2, X _3, X _4, X _5, X _{6, ...} are 1, 2, 3, 4, 5, 6, 7, ..., the results of the equation (1) is shown in Table 1 below.

K = 0 K = 1 K = 2 K = 3 K = 4 K = 5 K = 6

의 결과One)

Result of One 1 + 2 1 + 2 + 3 1 + 2 + 3 + 4 1 + 2 + 3 + 4 + 5 1 + 2 + 3 + 4 + 5 + 6 1 + 2 + 3 + 4 + 5 + 6 + 7 2)

Result of One 1 + 2 1 + 2 + 3 1 + 2 + 3 + 4 1 + 2 + 3 + 4 + 5 1 + 2 + 3 + 4 + 5 + 6 3) = 1) +2) One 4 9 16 25 36 49

Equation 1 is achieved by the configuration of the hardware shown in FIG. FIG. 6 is a block diagram illustrating the hardware configuration of the first deflection coefficient calculation unit 240a, and is a circuit for calculating the deflection coefficient of the rising curve shown in FIG. 5. The circuit shown in FIG. 6 includes a first delay means 600 for delaying the input signal by one clock, a second delay means 602 for delaying the output of the first delay means 600, and a second delay means 602. Output value of the third delay means 604 for delaying the output of the first delay means 604, the first adder 606 for adding the output of the first delay means 600 and the deflection speed coefficient X, and the first adder 606. And a logical multiplication gate 608 for ANDing the pixel start signal PSTART, a second adder 608 for adding an output value of the first delay means 600 and an output of the second delay means 602, and a second delay means. A third adder 610 which adds the output value of 602 and the output of the third delay means 604, and a deflip-flop 612 which holds the output value of the third adder 610 by a predetermined hold signal. .

The output values of the delay means of the circuit shown in FIG. 6 are shown in Table 2 below.

1) output value of the first delay means X, 2X, 3X, 4X, 5X, 6X, 7X, 8X, 9X, ... 2) output value of the second delay means X, 3X, 6X, 10X, 15X, 21X, 28X, 36X, ... 3) output value of the third delay means X, 3X, 6X, 10X, 15X, 21X, 28X, ... 4) Output value of the third adder (2) +3)) X ² , 4X ² , 9X ² , 16X ² , 25X ² , 36X ² , 49X ² , 64X ² , ...

In the flip-flop 612, when a hold signal is input, the deflip-flop 612 maintains the final value of the input rising curve and uses the starting point value of the falling curve.

In addition, the falling curve of the X ² function calculated by the second deflection coefficient calculation unit 240b is calculated by the following equation (2).

X ^2- [2 (X-1) +1] = (X-1) ²

Down counting from the final value calculated by Equation 1 to calculate the deflection coefficient of the falling curve, the value is shown in Table 3 below.

X ² ..., 49, 36, 25, 16, 9, 4, 1 -[2 (X-1) +1] ..., -13, -11, -9, -7, -5, -3, -1 (X-1) ² ..., 36, 25, 16, 9, 4, 1 0

7 is a hardware block diagram of the second deflection coefficient calculation unit 240b.

The circuit shown in FIG. 7 includes the down counter 700 which sequentially down counts at the final value of the rising curve, and the output values of the subtractor 702 and subtractor 702 which subtract "1" from the output values of the down counter 700. To multiply " 2 " means to multiply the output value of multiplier 704, multiplier 704 by 1 (return 708) and input 1 of adder 710, and to hold X ² or a predetermined rise portion. The adder 710 adds the value of X ² of the lower portion of the lower portion, and the flip-flop 712 holds the output value of the adder 710. That is, the down counter 700 counts the final value of the rising part to calculate X-1, multiplies the calculated value by 2, and adds 1 to the multiplied value to obtain the value of 2 (X-1). have. The value of 2 (X-1) is subtracted from the output value of the deflip-flop 612 of the first deflection coefficient calculation unit 240a shown in FIG.

Various panorama modes can be implemented by changing the interpolation periods k1 and k2 and the deflection speed coefficient B of the interpolation period and the input X of the adder 606 shown in FIG.

8 is a view for explaining a method of calculating a deflection coefficient for a horizontal pixel in a digital filter for a panoramic function according to the present invention.

The compression and interpolation intervals for the horizontal pixels are set in consideration of the horizontal pixels of the screen to be displayed (S80). Each deflection coefficient for the horizontal pixels of the compression and interpolation intervals set in S80 is calculated.

As described above, according to the panorama realization apparatus using the digital filter and the horizontal coefficient deflection coefficient calculation method according to the present invention, various panorama modes can be realized by adjusting the compression and interpolation intervals and the horizontal pixel deflection coefficient. Has the effect.

Claims (10)

A panorama realization apparatus for displaying a general video signal having a 4: 3 aspect ratio on a wide screen having a 16: 9 aspect ratio, A first line memory for storing respective pixel values of horizontal pixels of one line of the digital image signal; And

According to the characteristic of the function, the deflection speed for each horizontal pixel stored in the first line memory is calculated, the deflection speed for the current horizontal pixel and the previous horizontal pixel is added, and then the pixel of the pixel corresponding to the difference of integers is added. And a digital horizontal pixel deflection speed adjustment filter that calculates a new pixel value by adding a value multiplied by a fractional ratio to a value and a value obtained by multiplying a previous pixel value by a ratio of 1-minus. The filter of claim 1, wherein the digital horizontal pixel deflection speed adjustment filter A deflection coefficient calculation unit configured to determine respective deflection speeds with respect to the horizontal pixel; A first calculation unit which calculates an integer part and a decimal part by adding a deflection speed with respect to a current horizontal pixel and a previous horizontal pixel output from the deflection coefficient calculation part, and extracts a difference between the integer parts; And The pixel value of the pixel corresponding to the difference of the integer part extracted by the first calculation unit is read from the first line memory, and the pixel value immediately multiplied by a predetermined ratio of the fractional part by the read pixel value and the pixel immediately preceding the read pixel value. And a second operation unit configured to determine a new pixel value for a horizontal pixel of an image signal by adding a value multiplied by a predetermined ratio of the 1-decimal unit to a value. The method of claim 2, wherein the deflection coefficient calculation unit A first deflection coefficient calculation unit for calculating an upward curve deflection coefficient of the X ² function; A second deflection coefficient calculation unit for calculating a falling curve deflection coefficient of the X ² function; A selection unit for selecting output values of the first deflection coefficient calculating unit and the second deflection coefficient calculating unit according to a predetermined selection signal (sel signal); And And an adder configured to add an output value of the selection unit and a deflection coefficient interpolated at a predetermined ratio. The method of claim 3, wherein the first deflection coefficient calculation unit is a deflection speed of X _K = K-th pixel.

A panoramic implementor, characterized in that calculated by. The method of claim 3, wherein the second deflection coefficient calculation unit

A panoramic implementor, characterized in that calculated by. The method of claim 4, wherein the first deflection coefficient calculation unit First delay means for delaying the input signal by one clock; Second delay means for delaying the output of the first delay means by one clock; Third delay means for delaying the output of the second delay means by one clock; A first adder for adding an output of said first delay means and a deflection speed coefficient (X); A logical AND gate which ANDs the output of the first adder and the pixel start signal PSTART; A second adder for adding the output of the first delay means and the output of the second delay means; A third adder for adding the output of the second delay means and the output of the third delay means; And And a flip-flop for holding the output signal of the third adder to a predetermined hold signal. The method of claim 3, wherein the second deflection coefficient calculation unit A down counter sequentially down counting the final value of the first deflection coefficient calculation unit; A subtractor for subtracting "1" from the output value of the down counter; A multiplier for multiplying " 2 " by the output value of the subtractor; An adder for adding the X ² of the output value of the multiplier 1 and X ² or a conservative value that a given lowering of the cost hold the rising portion of the curve; And And a flip-flop for maintaining an output value of the adder. The method of claim 2, wherein the first operation unit An adder for adding an output value of the deflection coefficient calculating unit and a previous value delayed by one clock through a predetermined delay unit; An integer / fraction separator separating the integer part and the fractional part by inputting the addition result of the adder; And And a difference extracting unit extracting a difference by subtracting the integer value and the previous value separated by the integer / fraction separator and outputting a read signal for reading a pixel value corresponding to the extracted pixel position. Device. 3. The method of claim 2, wherein the second operation unit multiplies the pixel value of the pixel read from the first line memory by the read signal of the first operation unit and the ratio of the decimal unit output from the integer / fraction separator of the first operation unit. A first multiplier; A second multiplier for multiplying the ratio of the one-decimal portion by the pixel value of the previous pixel position by which the input pixel of the first multiplier delayed by the predetermined delayer is delayed by one clock; And And an adder for adding output pixel values of the first multiplier and the second multiplier. A method for calculating a deflection coefficient for a horizontal pixel for displaying a general video signal having a 4: 3 aspect ratio on a wide screen having a 16: 9 aspect ratio, Setting a compression and interpolation section for the horizontal pixels in consideration of the horizontal pixels of the screen to be displayed; And And calculating a deflection coefficient of the set compression and interpolation section.

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