JPS6011873B2 - Chroma key tracking device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a chromakey tracking device that purely electronically reduces a television screen to a specified position and dimension on the television screen.

A method of constructing a new screen by inserting a portion of one television screen into another screen is currently often used in television image production.

For example, there is a technique of specifying a part of a screen using a chromakey signal and inserting this part into another screen. However, since the position and dimensions of the chroma key signal change every moment as the television camera moves, it is necessary to change the television camera angle accordingly. This is a very difficult task, and recently a method has been considered in which the screen to be inserted is reduced and inserted in response to the chroma key signal. Therefore, the position and dimensions are measured by comparing the chromakey signal with a standard screen, and the results are used to reduce the height of the screen to the designated position and dimensions. For example, in FIG. 1, there is a case where screen B is reduced to the size of chroma key signal C, and screen E is created by inserting screen ○, which is a little taller, into screen A.

At this time, the chromakey signal C is a reference signal that specifies which position and which dimension of the screen B should be reduced. In general, the chromakey signal C is created by mixing the various color components (red component, green component, and growth component) that make up the image A with the growth component as the king and the other two components in an appropriate ratio. Therefore, when attempting to create a chroma key signal, it is customary to configure the screen by making the shaded areas of screen A blue. As will be described later, the temporal relationship between the chromakey signal and the corresponding image with reduced fringes is such that the reduced image lags behind the chroma key signal.

Therefore, when the chroma key signal moves, the movement of the reduced image cannot completely follow the movement of the chroma key signal, which may cause problems. That is, FIG. 2A shows an output image in a steady state, and FIG. 2B shows an output image immediately after the chromakey signal moves to the right of the screen. Since the reduced image to be inserted into the chromakey signal frame has a time delay, it cannot change rapidly, and unnecessary portions as shown by the hatched area in FIG. 2B appear. Therefore, the object of the present invention is to
To obtain a chroma key tracking device that does not generate unnecessary parts even when a chroma key frame moves. Next, the present invention will be explained in detail with reference to the drawings. Referring to FIG. 3, in one embodiment of the present invention, a first video signal A is input to input terminal 1, and a second video signal B is input to input terminal 2.
However, control signals are also supplied to the input terminals 3, respectively. The chromakey signal generator 11 receives the first video signal from the input terminal 1 and generates a chromakey signal. This chromakey signal is supplied to a gate circuit 12 via a switch 19, and is gated by the output of a frame signal generator 15 to remove noise components. The output of the gate circuit 12 is supplied to the frame signal detection circuit 13, which detects four values: the leftmost point in the horizontal direction, the rightmost point, the topmost point in the vertical direction, and the bottommost point in the vertical direction of the chromakey signal. be measured. An example of the frame signal detection circuit 13 is shown in FIG.

The chromakey signal 31 from which noise components have been removed by the gate circuit 12 is shaped by a waveform shaping circuit 33 and sent to counters 35 and 42. The counter 35 is driven by a clock pulse 34 and is configured to increment by 1 every clock pulse, and is cleared to 0 by a clear pulse 32 every horizontal TV cycle. Further counter 35
sends the counter value to the maximum value detection circuit 36 and the minimum value detection circuit 37 at the timing of the rise and fall of the chromakey signal. The maximum value detection circuit 36 receives various values corresponding to the waveform of the chromakey signal from the counter 35, and detects the maximum value among them, and this value becomes a value representing the rightmost position of the chromakey signal. . In this machine, the output value of the minimum value detection circuit 37 is a value representing the leftmost falsification of the chroma key signal. Here, the maximum value of the counter 35 is the value immediately before being cleared by the clear pulse 32, and this value indicates the maximum value in the horizontal direction of the television screen. Since this value can be calculated from the frequency of the clock pulse 34 and is a known value, knowing the minimum and maximum values of the chromakey signal makes it possible to measure the horizontal position and dimension of the chromakey signal with respect to the standard screen. can. Hysteresis circuits 38 and 39 are for removing jitter present at the rising and falling edges of the chromakey signal.

A chromakey signal usually has some jitter at its rising and falling points, even if the original image for producing the chromakey signal is stationary. Therefore, the output values of the maximum value detection circuit 36 and the minimum value detection circuit 37 always vary slightly. The hysteresis circuits 38 and 39 are constructed so that the output value does not change even if the input changes by a minute value, and is very useful for stabilizing the operation of the device. regulated output 40 and 4
1 is sent to the arithmetic circuit 14. The counter 42 is driven by a horizontal synchronizing pulse 49 and is configured to increase by 1 for each horizontal period, is reset to 0 for each TV field by a clear pulse 32, and is transferred to the next value at the time of generation of the chromakey signal. It is sent to the maximum value detection circuit 43 and minimum value detection circuit 44 of the stage.

The outputs of detection circuits 43 and 44 are supplied to hysteresis circuits 45 and 46, respectively. Circuits 42, 43, 4
4, 45, and 46 are circuits for determining the vertical position and size of the chromakey signal, and the operating principle is the same as the horizontal circuit described above. Hysteresis circuits 45 and 4
The output of 6 is sent to an arithmetic circuit 14. ′ i.e. output 4
0, 41, 47, and 48 indicate the size and position of a rectangle circumscribing the input chromakey signal. The four types of values obtained here represent the size and position of the quadrilateral circumscribing the input key signal.

That is, in FIG. 5, 21 indicates the standard screen size, 25 indicates the input chroma key signal frame, and the measured numerical values correspond to the four corner points of the frame signal 24. These four types of values are sent to the arithmetic circuit 14 and corrected to increase the size of the frame. In FIG. 5, 22 and 23 indicate two frames corresponding to the four corrected values. An example of the relationship in size between the original frame and the corrected frame is shown in FIG.
In FIG. 6, the machine axis shows the dimensions of the frame 24 based on the input chroma key frame 25 (hereinafter referred to as chroma key dimensions),
The vertical axis is the dimension of the output frame 22 or 23. The amount of increase in frame size and chromakey size are based on the following idea. In other words, even if the Kuromaki dimension becomes a slight vine, the amount of increase is not 0 but a certain constant value. When inserting a vertically shortened screen into another screen using a chroma key signal, it is better to keep this value small in order to minimize the portion cut out by the key signal, but on the other hand, if the key signal moves Considering this, a certain amount of size is required, and it would be a good idea to have a structure that allows this amount to be varied from the outside. Next, when the chroma key signal size is close to the maximum size, the amount of increase is reduced, so that the sum of the chroma key signal size and the amount of increase does not exceed the maximum size in any case.
This is because the vertical ratio is always less than 1 and never exceeds 1. Further, when the chroma key signal size is medium, the amount of increase is set to be maximum. This is because in general use, the dimensions are often medium and the movement is large. The relationship between the chroma key signal size and the amount of increase is determined based on the above idea, but it can also be operated by making the amount of increase simply a constant, proportional to the chroma key signal size, or a mixture of both. Needless to say, it is. An example of the arithmetic circuit 14 will be explained using FIG. 7.

Since the concept is the same for both the horizontal and vertical directions, an example for the horizontal direction will be shown. The minimum value 40 and maximum value 41 in the horizontal direction from the key signal detection circuit 13 are input to the arithmetic circuit 14. A subtraction circuit 71 subtracts the minimum value from the maximum value.
The output of the subtraction circuit 71 indicates the length of the key signal in the horizontal direction. This value becomes the input to the next coefficient unit 72 and is multiplied by a certain coefficient. This is to include a proportional component of the input key signal size in the increase amount of the frame size. Next, an adder 73 adds a constant. This output is then led to a limiter 74 and is limited to a certain value. This is to prevent the amount of increase in the time frame in which the input key signal size is large from becoming too large. limiter
The output of 74 is led to a subtracter 75 and subtracted from the minimum value 40 of the input key signal. The subtracted answer is guided to a minimum value limiter 76. The minimum value limiter 76 is constructed so that if the input is a negative number, it is replaced with zero, and if it is a positive number, it is passed through as is. On the other hand, the output of the limiter 74 is also led to an adder 77 and added to the input key signal maximum value 41.

The added result is led to a maximum value limiter 78, and when the input value exceeds the maximum value that can be considered as a key signal, it is replaced by this value, and when it is less than that, it is configured to pass through as is. As described above, since the minimum value 40 of the input key signal is calculated to be smaller and the maximum value 41 is larger, the key signal frame size is equivalently corrected to be larger. Although the correction in the horizontal direction has been described above, the correction in the vertical direction is also performed in exactly the same manner, so a description thereof will be omitted.

The four corrected values are sent to the frame signal generator 15 (FIG. 3), which generates a frame signal corresponding to the frame 22 (FIG. 5).

This frame signal is supplied to a gate circuit 12, which gates the chromakey signal to remove noise components. That is, frame 22
Noise components outside of are removed. On the other hand, the arithmetic circuit 14 supplies various values necessary for reducing the second video signal to a size corresponding to the frame 23 to the image fringe reduction circuit 16.

The output of the reduction circuit 16 is fed to the input of a mixing amplifier 17. The first video signal A and the chromakey signal are also supplied to the mixing amplifier 17 at the same time, and the second video signal B, which has been vertically reduced, is inserted into the first video signal A and mixed to produce a predetermined output signal. Outputs 4. The size of the image whose stripes are reduced by the vertical reduction circuit 16 corresponds to the frame 23, which is the size of the actual image. It is larger than the McKee signal frame 25. This is because signal processing when reducing an image takes time, and this causes a discrepancy between the movement of the chromakey signal and the movement of the reduced image, and as mentioned earlier, as shown in Figure 2B. In order to prevent unnecessary portions from appearing in the output signal as shown by diagonal lines, the second video signal 8 is vertically reduced in advance to a size larger than the key signal. FIG. 8 is a system diagram of the image height reduction circuit 16. The second video signal B from the input terminal 3 is supplied to an analog/digital converter 81 and converted into a PCM (pulse code modulation) signal.

At this time, the signal B is also supplied to the write clock generator 82, which oscillates a continuous wave phase-locked to the color burst signal. This continuous wave is multiplied and sent as a clock to the analog-to-digital converter 81, and the input is sampled and divided into pixels every clock pulse, and each pixel is converted into a digital quantity and output. The analog to digital converter output is supplied to an interpolation circuit 83. The interpolation circuit 83 has a function of converting the number of pixels in the horizontal direction and the number of scanning lines in the vertical direction. For example, when reducing an image to 1'1.5 in the horizontal direction, the first The pixel corresponding to the center is created by interpolation from the second and third pixel and becomes the second output pixel, and the next fourth pixel is passed through as is and the output pixel is It will be the third.

By repeating this operation, the number of output pixels will be reduced to 1/of the number of input pixels.
It can be set to 1.5. In other words, the sample gap in the analog-to-digital converter is equivalently increased by 1.30%, and this is written into the memory 84 at the next stage.
Therefore, a reduced image is already written into the memory 84. These controls are performed by output signals 93 and 94 from the arithmetic circuit 14. signal 93
The signal 94 controls the gap between newly created pixels in the interpolation circuit 84, and the signal 94 controls the write address generator 85, which generates an address when writing a signal to the memory 84, when a pixel arrives in the memory. The address value is 1 for each
control so that it increases by one. Read address generator 86 generates read addresses used when outputting signals from memory 84.

The switch 87 is for selecting a write address when writing a signal and selecting a read address when writing a signal.
Read clock generator 9 receives reference synchronization signal 92 and generates a read clock for driving read address generator 86 and digital-to-analog converter 88. Digital to analog converter 88 takes the digital signal from memory 84 and converts it to an analog signal. This analog signal is sent to the next stage process amplifier 89, amplified, and output as a signal 91. This output signal is a surface image signal reduced to a predetermined orientation and size, and is supplied as one of the inputs of the mixing amplifier 17. As explained above, if the present apparatus is used, it is possible to automatically reduce the input image to the size of the chroma key signal that is combined from the outside, and is therefore very effective in producing television programs.

In the explanation, an example of a chromakey signal as a key signal has been described, but it goes without saying that the present invention can also be applied directly to a wipe key etc. from the waveform generator 18. In particular, this device operates stably even if there is noise in the key signal, which is a feature not found in conventional devices.

[Brief explanation of the drawing]

FIGS. 1A to 2B and 2A to 2B are diagrams showing the operating state of the conventional device. FIG. 3 is a block diagram of an embodiment of the present invention, FIG. 4 is a block diagram of a key signal detection circuit, and FIG. 5 is a diagram showing the relationship on the screen of each frame obtained by an embodiment of the present invention. FIG. 6 is a diagram showing the size relationship between the input key frame and the output frame, FIG. 7 is a block diagram of the arithmetic circuit, and FIG. 8 is a block diagram of the image height reduction circuit. Hair 'Diagram Brother Z Ticket 3 Figure 4 Hair 5 Figure Toru Ticket F Diagram 8

Claims (1)

[Claims] 1. In a chromakey tracking device that compresses and inserts a video screen related to a second video signal into a chromakey frame related to a first video signal to obtain a special effect screen, means for obtaining a chromakey signal from the first video signal; , means for detecting a circumscribing frame address of the chroma key signal, means for determining a frame with a larger size than the detected circumscribing frame address, and a video screen related to the second video signal is compressed into the larger frame. A chromakey tracking device characterized by comprising: means for chroma key tracking.