KR100237027B1 - Fabrication method of semiconductor device - Google Patents

Fabrication method of semiconductor device Download PDF

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KR100237027B1
KR100237027B1 KR1019970030114A KR19970030114A KR100237027B1 KR 100237027 B1 KR100237027 B1 KR 100237027B1 KR 1019970030114 A KR1019970030114 A KR 1019970030114A KR 19970030114 A KR19970030114 A KR 19970030114A KR 100237027 B1 KR100237027 B1 KR 100237027B1
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tungsten
silicide layer
semiconductor device
gate
rich
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KR1019970030114A
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KR19990005896A (en
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정성희
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 스플릿 게이트(split gate) 형성 방법에 관한 것임.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a split gate of a semiconductor device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

텅스텐 폴리사이드 구조의 스플릿 게이트를 적용하는 플래쉬 메모리 소자에서 텅스텐 실리사이드층이 게이트의 측면과 하부면에서 빈약하게 형성되어 크랙(crack)이 발생하는 문제점이 발생함.In a flash memory device using a split gate having a tungsten polyside structure, a tungsten silicide layer is poorly formed at side and bottom surfaces of the gate, causing cracks.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

스플릿 게이트 형성시 텅스텐 실리사이드층을 증착함에 있어서 모노사일렌 가스의 조성 비율을 순차적으로 변화시켜가며 삼중으로 증착하여 소자의 스텝 커버리지와 속도 향상을 개선함.When depositing the tungsten silicide layer during the split gate formation, the composition ratio of monosilylene gas is sequentially changed and triple deposition is used to improve the step coverage and speed improvement of the device.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 소자의 스플릿 게이트 형성 공정.Split gate formation process of a semiconductor device.

Description

반도체 소자의 제조 방법Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 스플릿 게이트 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a split gate of a semiconductor device.

텅스텐 실리사이드는 반도체 소자의 고집적화에 따른 속도 개선의 측면에서 종래의 폴리실리콘를 대체하여 사용되고 있다. 플래쉬 메모리(flash memory) 소자에서도 폴리실리콘에 의한 높은 저항 특성을 개선 시키기 위하여 텅스텐 실리사이드를 적용하고 있다. 플래쉬 메모리 소자의 제품에 따라서는 도 1과 같이 스플릿 게이트(split gate)를 적용하는 구조를 사용하는데, 실리콘 기판(11)상에 적층구조 게이트(16)를 형성하고 산화막(13)을 증착한 다음 셀렉트 게이트(20)를 형성한다. 적층구조 게이트(16)는 터널 산화막(12) 상부에 제 1 폴리실리콘(13)을 사용하여 플로팅 게이트를 형성하고, 유전체막(14)과 콘트롤 게이트용 제 2 폴리실리콘층(15)을 순차로 증착한 구조이고, 셀렉트 게이트(20)는 텅스텐 폴리사이드 구조로써 제 3 폴리실리콘층(18) 상부에 텅스텐 실리사이드층(WSix;19)를 증착한다. 일반적으로 텅스텐 실리사이드층(19)은 모노사일렌(SiH4) 가스를 텅스텐 플르오린(WF6) 가스로 환원시켜 증착하는 MS공정으로 형성 하는데, 이러한 스플릿 게이트 소자에서는 게이트와 게이트 사이의 깊은 콘택 라인 때문에 콘택 내부의 깊은 영역에서 텅스텐플르오린(WF6) 가스의 공급이 원활하지 못하게 된다. 따라서 텅스텐 성분이 부족한 콘택 하부의 코너(corner)와 같은 부분에서는 텅스텐 실리사이드(19)가 얇게 증착된다. 이러한 부분에서는 낮은 스텝 커버리지 및 열처리 과정 중의 스트레스(stress) 집중에 의한 크래킹(cracking)으로 전류가 제 3 폴리실리콘층(18)으로 이동하게 됨에 따라 상호연결 라인(interconnection line)의 저항이 증가하게 된다. 이러한 결과로 소자의 속도를 개선시키기 위하여 채택된 텅스텐 실리사이드층(19)의 역할을 충분히 수행하지 못하는 문제점을 유발하게 된다.Tungsten silicide has been used in place of conventional polysilicon in view of speed improvement due to high integration of semiconductor devices. In flash memory devices, tungsten silicide is applied to improve the high resistance characteristics caused by polysilicon. According to a product of a flash memory device, a structure in which a split gate is applied as shown in FIG. 1 is used. A stacked gate 16 is formed on a silicon substrate 11 and an oxide film 13 is deposited. The select gate 20 is formed. The stacked gate 16 forms a floating gate using the first polysilicon 13 on the tunnel oxide layer 12, and sequentially the dielectric layer 14 and the second polysilicon layer 15 for the control gate are sequentially formed. The select gate 20 is a tungsten polyside structure, and the tungsten silicide layer WSi x 19 is deposited on the third polysilicon layer 18. In general, the tungsten silicide layer 19 is formed by an MS process in which monosilylene (SiH 4 ) gas is reduced and deposited by tungsten fluorine (WF 6 ) gas. In the split gate device, a deep contact line between the gate and the gate As a result, the supply of tungsten fluorine (WF 6 ) gas in the deep region inside the contact is not smooth. Therefore, a thin layer of tungsten silicide 19 is deposited at a portion such as a corner of a contact portion lacking in tungsten. In this area, the resistance of the interconnect line increases as the current moves to the third polysilicon layer 18 due to cracking due to stress concentration during the low step coverage and heat treatment process. . This results in a problem that the role of the tungsten silicide layer 19 adopted to improve the speed of the device is not sufficient.

따라서 본 발명은 스플릿 게이트를 사용하는 플래쉬 메모리소자의 형성 공정에서 스텝 코너에서의 텅스텐 조성 부족과 텅스텐 실리사이드층의 증착이 열악해짐을 방지하여 스텝커버리지의 향상 및 소자의 속도를 개선시키는데 그 목적이 있다.Therefore, an object of the present invention is to improve the step coverage and speed of the device by preventing the lack of tungsten composition and the deposition of the tungsten silicide layer at the step corner in the formation process of the flash memory device using the split gate. .

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은, 실리콘 기판상의 선택된 영역에 터널 산화막, 플로팅 게이트용 제 1 폴리실리콘, 유전체막 및 콘트롤 게이트용 제 2 폴리실리콘을 순차로 증착하여 적층구조 게이트를 형성하는 단계와, 상기 적층구조 게이트를 포함한 전체 구조 상부에 산화막을 증착하고, 셀렉트 게이트용 텅스텐 폴리사이드 구조로써 폴리실리콘층, 텡스텐 실리사이드층, 텅스텐-리치(W-rich) 실리사이드층 및 실리콘-리치(Si-rich) 텅스텐 실리사이드층을 순차로 형성하여 열처리하는 단계로 이루어진 것을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object, by sequentially depositing a tunnel oxide film, a first polysilicon for the floating gate, a dielectric film and a second polysilicon for the control gate in a selected region on the silicon substrate Forming a stacked gate, and depositing an oxide film over the entire structure including the stacked gate, and using a tungsten polyside structure for the select gate, a polysilicon layer, a tungsten silicide layer, and a tungsten-rich silicide Forming a layer and a silicon-rich (Si-rich) tungsten silicide layer sequentially characterized in that the step of heat treatment.

도 1은 종래의 방법에 의한 반도체 소자의 스플릿 게이트 형성 방법을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a split gate forming method of a semiconductor device by a conventional method.

도 2(a) 내지 도 2(c)는 본 발명에 의한 반도체 소자의 스플릿 게이트 형성 방법을 설명하기 위한 단면도.2 (a) to 2 (c) are cross-sectional views for explaining a split gate forming method of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 및 21 : 실리콘 기판(11) 12 및 22 : 터널 산화막11 and 21: silicon substrate 11 12 and 22: tunnel oxide film

13 및 23 : 제 1 폴리실리콘층 14, 24 : 유전체막13 and 23: first polysilicon layer 14, 24: dielectric film

15 및 25 : 제 2 폴리실리콘층 16 및 26 : 적층구조 게이트15 and 25: second polysilicon layer 16 and 26: laminated gate

17 및 27 : 산화막 18 및 28 : 제 3 폴리실리콘층17 and 27: oxide film 18 and 28: third polysilicon layer

19, 29, 29A, 29B 및 29C : 텅스텐 실리사이드Tungsten silicide: 19, 29, 29A, 29B and 29C

20 및 30 : 셀렉트 게이트20 and 30: Select gate

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 2(a) 내지 도 2(c)는 본 발명에 의한 반도체 소자의 스플릿 게이트 형성 방법을 설명하기 위한 단면도.이다.2 (a) to 2 (c) are cross-sectional views for explaining a split gate forming method of a semiconductor device according to the present invention.

도 2(a)는 종래의 스플릿 게이트 형성방법과 같이 실리콘 기판(21)상의 선택된 영역에 적층구조 게이트(26)를 형성하고 적층구조 게이트(26)를 포함한 전체 구조 상부에 산화막(27)을 증착한 후 셀렉트 게이트(30)를 형성한 단면도이다. 적층구조 게이트(26)는 터널 산화막(22), 플로팅 게이트용 제 1 폴리실리콘(23), 유전체막(24) 및 콘트롤 게이트용 제 2 폴리실리콘(25)을 순차로 증착하고, 셀렉트 게이트(30)는 텅스텐 폴리사이드 구조로써 폴리실리콘층(27) 상부에 텅스텐 실리사이드층(29A)을 증착한다. 텅스텐 실리사이드층(29A)은 380 ℃ 내지 400 ℃의 온도범위에서 모노사일렌 가스를 텅스텐 플르오린 가스로 환원시켜 증착한다.FIG. 2 (a) shows a stacked gate 26 in a selected region on a silicon substrate 21 and a deposition of an oxide film 27 over the entire structure including the stacked gate 26, as in the conventional split gate forming method. After that, the sectional view of the select gate 30 is formed. The stacked structure gate 26 sequentially deposits the tunnel oxide film 22, the first polysilicon 23 for the floating gate, the dielectric film 24, and the second polysilicon 25 for the control gate, and then selects the gate 30. ) Deposits a tungsten silicide layer 29A on top of the polysilicon layer 27 as a tungsten polyside structure. The tungsten silicide layer 29A is deposited by reducing monosilylene gas to tungsten fluorine gas in a temperature range of 380 ° C to 400 ° C.

도 2(b)는 550 ℃ 이상의 온도에서 텅스텐 플르오린 가스를 모노사일렌 가스보다 더 많이 흐르도록 하거나 텅스텐 플르오린 가스만을 흘려 주어 텅스텐-리치(W-rich) 화합물이 형성되게 하여 텅스텐-리치 실리사이드층(29B)을 증착함을 나타낸다. 일반적으로 텅스텐 플르오르 소오스(source) 가스는 고온에서 확산이 활발하여 이동성이 증가하므로 콘택 홀의 하부면까지 공급이 원활히 이루어지고, 실리콘 성분과 반응하여 텅스텐-리치의 실리사이드층이 증착된다. 이 때 텅스텐 플르오린 가스와 반응할 실리콘의 성분이 적기 때문에 증착이 천천히 이루어지므로, 텅스텐 플르오린 가스가 콘택 홀 하부면까지 공급될 시간이 충분하게 확보된다. 따라서 높은 스텝 커버리지의 특성을 보여 전체 구조가 일정한 두께로 증착된다.FIG. 2 (b) shows that tungsten fluorine gas flows more than monosilylene gas at a temperature of 550 ° C. or higher, or only tungsten fluorine gas flows to form a tungsten-rich (W-rich) compound to form tungsten-rich silicide Deposition layer 29B. In general, tungsten fluoride source gas (diffusion) is active at a high temperature, the mobility is increased, so that the supply is smoothly supplied to the bottom surface of the contact hole, and the tungsten-rich silicide layer is deposited by reacting with the silicon component. At this time, since the deposition is performed slowly because there are few components of silicon to react with the tungsten fluorine gas, sufficient time for supplying the tungsten fluorine gas to the contact hole lower surface is ensured. Therefore, the high structure of the step coverage shows that the entire structure is deposited with a constant thickness.

도 2(c)는 도 2(b)의 공정과 반대로 함유 비율이 높은 모노사일렌 가스를 흘려주어 실리콘-리치(Si-sich) 텅스텐 실리사이드층(29C)을 증착함을 나타낸다. 이어 후속 공정에서 열처리하여 상층부와 하층부의 텅스텐 실리사이드로부터 실리콘이 이동하여 안정된 텅스텐 실리사이드 구조를 형성하게 된다. 따라서 콘택 하부의 코너에서 텅스텐 조성이 풍부해져 스텝 커버리지의 향상과 소자의 속도를 개선할 수 있다.FIG. 2 (c) shows that the Si-sich tungsten silicide layer 29C is deposited by flowing a monoxylene gas having a high content ratio as opposed to the process of FIG. 2 (b). Subsequently, heat treatment is performed in a subsequent process to move silicon from the upper and lower tungsten silicides to form a stable tungsten silicide structure. Therefore, the composition of tungsten is enriched at the corners of the bottom of the contact, thereby improving step coverage and device speed.

상술한 바와 같이 본 발명에 의하면, 스플릿 게이트를 채택하는 플래쉬 메모리 소자의 스텝 코너에서 텅스텐 실리사이드 일부분을 텅스텐-리치화 함으로써 전류의 이동 특성을 향상 시키고 스트레스가 코너에 집중되어 크랙이 발생하는 현상을 감소 할 수 있다. 따라서 스텝 커버리지의 개선과 소자의 속도 향상을 기대할 수 있다.As described above, according to the present invention, by tungsten-riching a part of tungsten silicide at a step corner of a flash memory device employing a split gate, it is possible to improve current transfer characteristics and reduce stress caused by concentration at the corner. can do. Therefore, the step coverage and the speed of the device can be improved.

Claims (6)

실리콘 기판상의 선택된 영역에 터널 산화막, 플로팅 게이트용 제 1 폴리실리콘, 유전체막 및 콘트롤 게이트용 제 2 폴리실리콘을 순차로 증착하여 적층구조 게이트를 형성하는 단계와,Sequentially depositing a tunnel oxide film, a first polysilicon for a floating gate, a dielectric film, and a second polysilicon for a control gate in a selected region on a silicon substrate to form a stacked structure gate; 상기 적층구조 게이트를 포함한 전체 구조 상부에 산화막을 증착하고, 셀렉트 게이트용 텅스텐 폴리사이드 구조로써 폴리실리콘층, 텅스텐 실리사이드층, 텅스텐-리치(W-rich) 실리사이드층 및 실리콘-리치(Si-sich) 텅스텐 실리사이드층을 순차로 형성하여 열처리 하는 단계로 이루어진 것을 특징으로 하는 반도체 소자의 제조 방법.An oxide film is deposited on the entire structure including the stacked gate, and a polysilicon layer, a tungsten silicide layer, a tungsten-rich silicide layer, and a silicon-rich (Si-sich) are used as the tungsten polyside structure for the select gate. A method of manufacturing a semiconductor device, comprising the step of forming a tungsten silicide layer sequentially and performing heat treatment. 제 1 항에 있어서,The method of claim 1, 상기 텅스텐 실리사이드층은 380 ℃ 내지 400 ℃의 온도 범위에서 모노사일렌 가스를 텅스텐 플르오린 가스로 환원시켜 증착하는 것을 특징으로 하는 반도체 소자의 제조 방법.The tungsten silicide layer is a method of manufacturing a semiconductor device, characterized in that the deposition by reducing the monosilylene gas to tungsten fluorine gas in the temperature range of 380 ℃ to 400 ℃. 제 1 항에 있어서,The method of claim 1, 상기 텅스텐-리치 실리사이드층은 550 ℃ 내지 600 ℃의 온도에서 텅스텐 플르오린 가스를 모노사일렌 가스보다 더 많이 흐르게 하거나 텅스텐 플르오린 가스만을 흘려주어 증착하는 것을 특징으로 반도체 소자의 제조 방법.The tungsten-rich silicide layer is a method of manufacturing a semiconductor device, characterized in that the deposition of more tungsten fluorine gas than the monosilylene gas flows at a temperature of 550 ℃ to 600 ℃ only flowing the tungsten fluorine gas. 제 1 항에 있어서,The method of claim 1, 상기 실리콘-리치 텅스텐 실리사이드층은 550 ℃ 내지 600 ℃의 온도에서 모노사일렌 가스를 텅스텐 플르오린 가스보다 더 많이 흘려주어 증착하는 것을 특징으로 반도체 소자의 제조 방법.The silicon-rich tungsten silicide layer is a method of manufacturing a semiconductor device, characterized in that the deposition of more mono-styrene gas than tungsten fluorine gas at a temperature of 550 ℃ to 600 ℃. 제 1 항에 있어서,The method of claim 1, 상기 텅스텐-리치 실리사이드층은 실리콘 조성비가 2 이하인 것을 특징으로 하는 반도체 소자의 제조 방법.And the tungsten-rich silicide layer has a silicon composition ratio of 2 or less. 제 1 항에 있어서,The method of claim 1, 상기 실리콘-리치 텅스텐 실리사이드층은 실리콘 조성비가 2 이상인 것을 특징으로 하는 반도체 소자의 제조 방법.The silicon-rich tungsten silicide layer has a silicon composition ratio of 2 or more.
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KR102087520B1 (en) 2018-11-29 2020-03-10 농업회사법인 델텍스 주식회사 Two toned blackout curtain together with keeping warm for cultivating Ginseng plant and manufacturing method thereof
KR102141338B1 (en) 2020-06-02 2020-08-05 농업회사법인 델텍스 주식회사 Light shielding film f or both lagging for cultivating ginseng

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KR100390953B1 (en) * 2000-12-27 2003-07-10 주식회사 하이닉스반도체 Method of manufacturing a flash memory device

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KR102087520B1 (en) 2018-11-29 2020-03-10 농업회사법인 델텍스 주식회사 Two toned blackout curtain together with keeping warm for cultivating Ginseng plant and manufacturing method thereof
KR102141338B1 (en) 2020-06-02 2020-08-05 농업회사법인 델텍스 주식회사 Light shielding film f or both lagging for cultivating ginseng

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