KR100228775B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100228775B1 KR100228775B1 KR1019960080272A KR19960080272A KR100228775B1 KR 100228775 B1 KR100228775 B1 KR 100228775B1 KR 1019960080272 A KR1019960080272 A KR 1019960080272A KR 19960080272 A KR19960080272 A KR 19960080272A KR 100228775 B1 KR100228775 B1 KR 100228775B1
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- bit line
- line contact
- semiconductor device
- contact junction
- well
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 15
- 150000002500 ions Chemical class 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 6
- 239000010408 film Substances 0.000 description 15
- 238000002955 isolation Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로서, 반도체기판에서 센스엠프와 연결되는 비트라인 콘택 접합과 웰의 경계 부분에 상기 웰보다는 낮은 농도의 n 또는 p형의 불순물을 이온주입하여 공핍영역을 형성함으로서 공핍영역의 폭을 증가시켜 비트라인 콘택 접합에서의 전기장의 세기를 감소시켰으므로, 비트라인 콘택접합의 정전용량이 감소되어 센싱 마진이 증가되며, 비트라인 콘택 접합의 누설전류가 감소되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a depletion region is formed by ion implanting impurities of n or p type at a concentration lower than that of a well at a boundary between a bit line contact junction and a well connected to a sense amplifier in a semiconductor substrate By increasing the width of the depletion region, the electric field strength of the bit line contact junction is reduced. Therefore, the capacitance of the bit line contact junction is reduced, the sensing margin is increased, and the leakage current of the bit line contact junction is reduced. And reliability of device operation can be improved.
Description
본 발명은 센스 엠프의 센싱마진을 향상시킨 반도체소자의 제조방법에 관한 것으로서, 특히 비트라인 콘택 접합과 웰의 사이에서의 공핍영역 폭을 증가시켜 비트라인 콘택 접합의 정전용량을 감소시키고, 그 부분에 전계가 약하게 걸리도록 하여 충돌이온화에 의한 누설전류를 감소시켜 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device with improved sensing margin of a sense amplifier. In particular, the width of the depletion region between the bit line contact junction and the well is increased to reduce the capacitance of the bit line contact junction, and the portion thereof. The present invention relates to a method for manufacturing a semiconductor device capable of weakly applying an electric field to reduce leakage current due to collision ionization, thereby improving process yield and reliability of device operation.
최근의 반도체 장치 고집적화 추세는 미세패턴 형성기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of micropattern forming technology, and miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, is essential in the manufacturing process of semiconductor devices.
종래 감광막 패턴의 제조 공정은, 피식각층상에 감광제와 수지(resin) 등이 용재인 솔밴트에 일정 비율로 용해되어 있는 감광막을 형성한 후, 투명기판 상에 광차단막 패턴이 형성되어 있는 노광마스크를 사용하여 빛을 선택적으로 조사하여 패턴 또는 비패턴으로 예정된 부분의 폴리머를 중합시키고, 약알칼리성 현상액을 사용하여 상기 감광막의 노광/비노광 영역들을 선택적으로 제거하여 감광막 패턴을 형성한다.In the conventional manufacturing process of the photosensitive film pattern, an exposure mask in which a photoresist film is dissolved on a layer to be etched in a solvent containing a photoresist, a resin, and the like at a predetermined ratio, and then a light blocking film pattern is formed on a transparent substrate. The polymer is selectively irradiated with light to polymerize a predetermined portion of the polymer in a pattern or a non-pattern, and a weakly alkaline developer is used to selectively remove the exposed / non-exposed areas of the photosensitive film to form a photosensitive film pattern.
상기 감광막 패턴의 분해능(R)은 노광 공정에 사용되는 축소노광장치의 광원의 파장(λ) 및 공정변수(k)에 비례하고, 렌즈구경(numerical aperture;NA)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength [lambda] and the process variable k of the light source of the reduction exposure apparatus used in the exposure process, and inversely proportional to the numerical aperture NA.
따라서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키거나, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; CEL) 방법 또는 위상반전 마스크를 사용하기도 한다.Therefore, the C. method of forming a separate thin film on the wafer to reduce the wavelength of the light source or to improve the image contrast in order to improve the light resolution of the reduction exposure apparatus. Phase inversion masks are also used.
이러한 집적도의 증가로 인하여 셀의 정전용량(Cs)을 확보하기가 어려워지고 있으며, 그에 비하여 비트라인 콘택 접합의 정전용량(Cb)도 감소하기는 하나 감소비율이 셀의 정전용량보다는 그 폭이 적다. 따라서 센스 엠프의 센싱마진(Cs/Cb)이 감소되어, 차세대 소자의 특성을 향상시키기 위해서는 집적도의 증가뿐만 아니라 비트라인 콘택 접합의 정전용량(Cb)을 감소시키는 것이 소자의 특성 향상에 중요한 요인이 된다.Due to this increase in density, it is difficult to secure the cell capacitance (Cs), while the capacitance (Cb) of the bit line contact junction is reduced, but the reduction ratio is smaller than that of the cell. . Therefore, the sensing margin (Cs / Cb) of the sense amplifier is reduced, and in order to improve the characteristics of the next-generation devices, it is important not only to increase the integration but also to reduce the capacitance (Cb) of the bit line contact junction. do.
제1도는 종래 기술에 따른 반도체소자의 단면도로서, 비트라인 형성 전단계의 예이다.1 is a cross-sectional view of a semiconductor device according to the prior art, which is an example of a previous step of forming a bit line.
먼저, 반도체기판(10)상에 소정 도전형, 예를들어 P형 웰(12)과 소자분리 산화막(14)과 게이트산화막(16)과 게이트전극(18) 및 절연 스페이서(20)가 형성되어 있으며, 상기 구조의 전표면에는 콘택홀(22)을 구비하는 평탄화막(24)이 형성되어 있다. 이때 상기 콘택홀(22)에 의해 노출되어 있는 반도체기판(1)에는 비트라인 콘택 접합(26)이 상기 웰과는 다른 도전형의 불순물, 예를들어 N형 불순물로 형성되어 있다.First, a predetermined conductive type, for example, a P type well 12, an isolation layer 14, a gate oxide layer 16, a gate electrode 18, and an insulating spacer 20 are formed on the semiconductor substrate 10. The planarization film 24 including the contact holes 22 is formed on the entire surface of the structure. In the semiconductor substrate 1 exposed by the contact hole 22, the bit line contact junction 26 is formed of an impurity of a conductivity type different from that of the well, for example, an N-type impurity.
상기와 같은 종래 기술에 따른 비트라인 콘택 접합과 연결되는 센스 엠프를 구비하는 반도체소자는 비트라인 콘택 접합 부분에 인가되는 전기장을 감소시킬 수 없어 강한 전기장에 의한 충돌이온화에 의해 누설전류가 증가되고, 정전용량이 감소되지 않아 센스 엠프의 센싱마진을 저하시키는 문제점이 있다.In the semiconductor device having a sense amplifier connected to the bit line contact junction according to the prior art as described above, the electric field applied to the bit line contact junction may not be reduced, and the leakage current is increased by collision ionization by a strong electric field. Since the capacitance is not reduced, there is a problem of lowering the sensing margin of the sense amplifier.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 웰과 비트라인 콘택 접합 사이의 공핍영역의 폭을 증가시켜 이 부분에서의 전장을 감소시켜 비트라인 콘택 접합에서의 누설전류를 감소시키고, 정전용량을 감소시켜 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to increase the width of the depletion region between the well and the bitline contact junction, thereby reducing the electric field at this portion, thereby reducing the leakage current at the bitline contact junction. It is to provide a method for manufacturing a semiconductor device that can reduce the capacitance, improve the process yield and the reliability of device operation.
제1도는 종래 기술에 따른 반도체소자의 단면도.1 is a cross-sectional view of a semiconductor device according to the prior art.
제2도는 본 발명의 제1실시예에 따른 반도체소자의 단면도.2 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
제3도는 본 발명의 제2실시예에 따른 반도체소자의 단면도.3 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.
제4도는 본 발명의 제3실시예에 따른 반도체소자의 단면도.4 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체기판 12 : p웰10: semiconductor substrate 12: p well
14 : 소자분리 산화막 16 : 게이트산화막14 device isolation oxide film 16 gate oxide film
18 : 게이트전극 20 : 절연 스페이서18 gate electrode 20 insulating spacer
22 : 콘택홀 24 : 평탄화막22 contact hole 24 planarization film
26 : 비트라인 콘택 접합 28 : 공핍영역26 bit line contact junction 28 depletion region
30 : 감광막 패턴30: photosensitive film pattern
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법의 특징은, 소정 도전형의 웰과 비트라인 콘택 접합을 구비하는 반도체소자의 제조방법에 있어서, 상기 웰과 비트라인 콘택 접합의 경계에 불순물 이온을 상기 웰의 농도 보다 저농도로 주입하여 불순물영역을 형성하여 공핍영역의 폭을 증가시킴에 있다.A feature of the semiconductor device manufacturing method according to the present invention for achieving the above object is a method of manufacturing a semiconductor device having a well and bit line contact junction of a predetermined conductivity type, wherein the well and bit line contact junction Impurity ions are implanted at the boundary at a lower concentration than the well concentration to form an impurity region to increase the width of the depletion region.
이하, 본 발명에 따른 반도체소자의 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제2도는 본 발명의 제1실시예에 따른 반도체소자의 단면도로서, 게이트전극을 형성한 후에 공핍영역을 형성한 경우의 예이다.FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, in which a depletion region is formed after the gate electrode is formed.
먼저, 반도체기판(10)상에 제1도전형, 예를들어 p형 웰(12)을 형성하고, 소자분리 영역으로 예정되어 있는 부분 상에 소자분리 산화막(14)을 형성한 후에 게이트산화막(16)과 게이트전극(18) 및 절연 스페이서(20)를 형성하고, 상기 구조의 전표면에 비트라인 콘택홀(22)을 구비하는 평탄화막(24)을 형성한다.First, a first conductive type, for example a p-type well 12, is formed on the semiconductor substrate 10, and the device isolation oxide film 14 is formed on the portion intended as the device isolation region. 16, a gate electrode 18 and an insulating spacer 20 are formed, and a planarization film 24 having bit line contact holes 22 is formed on the entire surface of the structure.
그다음 상기 게이트전극(18) 양측의 반도체기판(10)에 상기 웰과는 반대 도전형인 N형 불순물로 비트라인 콘택 접합(24)을 형성한 후에 상기 비트라인 콘택 접합(26)과 p웰(12)의 경계 부분에 제1 또는 제2도전형인 P 또는 N형 불순물로 공핍영역(28)을 형성한다.Then, the bit line contact junction 24 and the p well 12 are formed on the semiconductor substrate 10 on both sides of the gate electrode 18 with N-type impurities of the opposite conductivity type to the wells. The depletion region 28 is formed of a P or N type impurity of the first or second conductivity type at the boundary between
여기서 상기 공핍영역(28)은 상기 p웰(12)이나 비트라인 콘택 접합(26)의 불순물 농도 보다 낮은 불순물 농도를 가지는데, 예를들어 p웰(12)과 비트라인 콘택접합(24)의 불순물 농도가 각각 약 10E13 ion/㎤, 10E14 ion/㎤ 일 때 p형의 인(P)을 주입하는 경우에는 1.0E12∼7.0E12 ion/㎤의 농도로 50∼300KeV의 주입 에너지로 주입하여 p웰(12) 부분의 불순물 농도를 감소시켜 공핍영역(28)의 폭을 증가시키고, n형인 붕소(B)를 이온주입하는 경우에는 1.0E11∼7.0E11 ion/㎤의 농도로 30∼100KeV의 주입 에너지로 주입하여 비트라인 콘택 접합(26)의 경계 부분의 공핍영역(28)을 증가시킨다.The depletion region 28 has an impurity concentration lower than that of the p well 12 or the bit line contact junction 26. For example, the depletion region 28 of the p well 12 and the bit line contact junction 24 may be formed. When p-type phosphorus (P) is injected at impurity concentrations of about 10E13 ions / cm 3 and 10E14 ions / cm 3, respectively, the p-well is injected at a concentration of 50-300 KeV at a concentration of 1.0E12 to 7.0E12 ion / cm 3. In the case of reducing the impurity concentration in the portion (12) to increase the width of the depletion region 28, and implanting the n-type boron (B) ion implantation energy of 30 to 100 KeV at a concentration of 1.0E11 to 7.0E11 ion / cm 3. Injection to increase the depletion region 28 of the boundary portion of the bit line contact junction 26.
제3도는 본 발명의 제2실시예에 따른 반도체소자의 단면도로서, 소자분리 후에 감광막 패턴을 이온주입 마스크로 하여 공핍영역을 형성한 경우의 예이다.3 is a cross-sectional view of a semiconductor device according to a second exemplary embodiment of the present invention, in which a depletion region is formed by using a photoresist pattern as an ion implantation mask after device isolation.
먼저, 반도체기판(10)상에 P웰(12)을 형성하고, 소자분리 영역으로 예정되어 있는 부분 상에 소자분리 산화막(14)을 형성한 후에 상기 반도체기판(10)에서 비트라인 콘택 접합으로 예정되어 있는 부분을 노출시키는 감광막 패턴(30)을 형성하고, 상기 감광막 패턴(30)에 의해 노출되어 있는 반도체기판(10) 하부의 p웰(12)에서 비트라인 콘택 접합과의 경계로 예정되어 있는 부분에 공핍영역(28)을 불순물 이온주입으로도 2의 방법과 같은 방법으로 형성한다.First, the P well 12 is formed on the semiconductor substrate 10, and the device isolation oxide film 14 is formed on the portion intended as the device isolation region. Then, the semiconductor substrate 10 is connected to the bit line contact junction. A photoresist pattern 30 is formed to expose a predetermined portion, and the p well 12 under the semiconductor substrate 10 exposed by the photoresist pattern 30 is defined as a boundary with a bit line contact junction. The depletion region 28 is formed in the same part as the method of 2 also by impurity ion implantation.
제4도는 본 발명의 제3실시예에 따른 반도체소자의 단면도로서, 게이트전극을 형성한 후, 감광막 패턴을 이온주입 마스크로 사용하여 공핍영역을 형성한 예로서, 게이트전극(18)까지를 형성한 후에 비트라인 콘택 접합으로 예정되어 있는 부분을 노출시키는 감광막 패턴(30)을 형성하고, 이를 마스크로 제2도와 같은 불순물 이온주입으로 공핍영역(28)을 형성하였다.4 is a cross-sectional view of a semiconductor device according to a third exemplary embodiment of the present invention, in which a depletion region is formed by using a photoresist pattern as an ion implantation mask after forming a gate electrode. The gate electrode 18 is formed. Thereafter, a photosensitive film pattern 30 exposing a portion intended for bit line contact bonding was formed, and a depletion region 28 was formed by implanting impurity ions as shown in FIG. 2 as a mask.
상기 제2 및 제3실시예에서처럼 본 발명에 의한 공핍영역 형성공정은 웰 형성이나 소자분리 산화막 형성과 같은 고온 열처리 공정 후에는 어느 단계에서나 형성할 수 있으며, 이는 고온 열처리에 따른 불순물 확산에 의한 농도 변화를 고려한 것이다.As in the second and third embodiments, the depletion region forming process according to the present invention may be formed at any stage after a high temperature heat treatment process such as well formation or device isolation oxide film formation. Change is taken into account.
또한 상기에서는 p형 웰에 n형 비트라인 콘택 접합을 예로 들었으나, 반대로 n형 웰에 p형 비트라인 콘택 접합을 형성하는 경우에도 본 발명의 상상을 적용할 수 있음은 물론이다.In addition, although the n-type bitline contact junction is exemplified in the p-type well, the imagination of the present invention can be applied to the case where the p-type bitline contact junction is formed in the n-type well.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조방법은 반도체기판에서 센스엠프와 연결되는 비트라인 콘택 접합과 웰의 경계 부분에 상기 웰보다는 낮은 농도의 n 또는 p형의 불순물을 이온주입하여 공핍영역을 형성함으로서 공핍영역의 폭을 증가시켜 비트라인 콘택 접합에서의 전기장의 세기를 감소시켰으므로, 비트라인 콘택 접합의 정전용량이 감소되여 센싱 마진이 증가되며, 비트라인 콘택 접합의 누설전류가 감소되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, by implanting an impurity of n or p type having a lower concentration than that of the well at a boundary between a bit line contact junction and a well connected to a sense amplifier in a semiconductor substrate, By forming the depletion region, the width of the depletion region is increased to decrease the strength of the electric field at the bit line contact junction. Therefore, the capacitance of the bit line contact junction is reduced, the sensing margin is increased, and the leakage current of the bit line contact junction is increased. There is an advantage that can be reduced to improve the process yield and the reliability of device operation.
Claims (5)
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