KR100226793B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR100226793B1
KR100226793B1 KR1019960039727A KR19960039727A KR100226793B1 KR 100226793 B1 KR100226793 B1 KR 100226793B1 KR 1019960039727 A KR1019960039727 A KR 1019960039727A KR 19960039727 A KR19960039727 A KR 19960039727A KR 100226793 B1 KR100226793 B1 KR 100226793B1
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titanium nitride
semiconductor device
nitride film
manufacturing
gas
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KR1019960039727A
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Korean (ko)
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KR19980021003A (en
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안재영
최상준
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 콘택홀을 형성하기 위해서 질화 티타늄막을 건식 식각할 때에 폴리머가 발생하지 않는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which no polymer is generated when dry etching a titanium nitride film to form a contact hole.

본 발명의 반도체 소자의 제조 방법은 기판상에 질화 티타늄막을 형성하는 단계와, 상기 질화 티타늄막상에 절연막을 형성하는 단게와, 상기 절연막과 질화 티타늄막을 C3F8와 CO 및 Ar가스 중 적어도 C3F8가스를 이용하여 선택적으로 제거하여 홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention includes the steps of forming a titanium nitride film on a substrate, forming an insulating film on the titanium nitride film, and forming the insulating film and the titanium nitride film at least C of C 3 F 8 , CO, and Ar gas. And selectively removing the 3 F 8 gas to form a hole.

Description

반도체 소자의 제조 방법Manufacturing Method of Semiconductor Device

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 콘택홀을 형성하기 위해서 질화 티타늄막을 건식 식각할 때에 폴리머가 발생하지 않는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which no polymer is generated when dry etching a titanium nitride film to form a contact hole.

금속 배선의 구조에 금속선을 정의하기 위한 사진 현상 공정을 할 때, 금속층이 빛을 반사하여 상기 금속선의 정의가 어려우므로 이를 방지하기 위해 상기 금속층상에 반사 방지막을 증착한다. 상기 반사 방지막으로는 질화 티타늄막이 일반적으로 많이 사용된다.When performing a photodevelopment process for defining a metal line in the structure of the metal wiring, since the metal layer reflects light and it is difficult to define the metal line, an anti-reflection film is deposited on the metal layer to prevent this. As the anti-reflection film, a titanium nitride film is generally used.

이하, 첨부된 도면을 참고하여 반도체 소자의 제조 방법을 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device will be described with reference to the accompanying drawings.

도1a 내지 도1c는 종래의 비아(Via)콘택홀 형성 방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a conventional method for forming a via contact hole.

도1a에서와 같이, 반도체 기판(11)상에 금속층(12)과, 질화 티타늄(TiN)막(13)과, 제1TEOS(Tetrs Ethyl Ortho Silicate)층/USG(Undoped Silicate Glass)층/제2TEOS층으로 이루어진 절연막(14)과, 감광막(15)을 차례로 형성한다.As shown in FIG. 1A, the metal layer 12, the titanium nitride (TiN) film 13, the first TETS (Tetrs Ethyl Ortho Silicate) layer / USG (Undoped Silicate Glass) layer / second TEOS on the semiconductor substrate 11 The insulating film 14 which consists of layers, and the photosensitive film 15 are formed in order.

여기서 상기 질화 티타늄막(13)은 반사 방지막으로 사용하며 건식 식각시 폴리머의 유발이 크다.In this case, the titanium nitride film 13 is used as an anti-reflection film and has a high induction of polymer during dry etching.

도1b에서와 같이, 상기 감광막(15)을 상기 반도체 기판(11)상의 소정 부위에 제거되도록 선택적으로 노광 및 현상한다. 이어 상기 선택적으로 노광 및 현상된 감광막(15)을 마스크로 이용하여 상기 절연막(14) 선택적으로 식각한다.As shown in FIG. 1B, the photosensitive film 15 is selectively exposed and developed to be removed at a predetermined portion on the semiconductor substrate 11. Subsequently, the insulating layer 14 is selectively etched using the selectively exposed and developed photosensitive layer 15 as a mask.

여기서 상기 절연막(14)을 RIE(Reactive Ion Etching) 또는 ECR(Electron Cyclotron Resonance) 및 MERIE(Magnetic Enhancement Reactive Ion Etching)에 사용되는 Ar/CHF3/CF4계열의 가스로 식각하기 때문에 전면에 금속성 폴리머(Polymer)(16)가 발생하게 된다.Here, the insulating film 14 is etched with Ar / CHF 3 / CF 4 series of gases used for RIE (Reactive Ion Etching) or ECR (Electron Cyclotron Resonance) and MERIE (Magnetic Enhancement Reactive Ion Etching). (Polymer) 16 is generated.

도1c에서와 같이, 상기 감광막(15)을 제거하고, 상기 폴리머(16)를 제거하기 위해 화학 처리와, O3처리 및 스퍼터 에치(Sputter Etch)공정을 하여 상기 폴리머(16)를 제거한다.As shown in FIG. 1C, the polymer 16 is removed by chemical treatment, an O 3 treatment, and a sputter etch process to remove the photosensitive film 15 and remove the polymer 16.

여기서 상기 폴리머(16)는 금속성 폴리머이기 때문에 저항 문제가 있고, 이후 제2금속층 증착시 상기 폴리머(16)가 많으므로 상기 스퍼터 에치량이 증가 하게된다.Since the polymer 16 is a metallic polymer, there is a resistance problem, and since the polymer 16 is large when the second metal layer is deposited, the amount of sputter etch is increased.

종래의 반도체 소자의 제조 방법은 다음과 같은 문제점이 있었다.The conventional method for manufacturing a semiconductor device has the following problems.

첫째, 질화 티타늄막 식각시 다량의 폴리머가 발생하기 때문에 장비 관리 및 공정 관리가 어렵다.First, since a large amount of polymer is generated when the titanium nitride film is etched, equipment management and process management are difficult.

둘째, 폴리머 제거를 위해 특수 화학 처리 및 스퍼터 에치(Sputter Etch)량을 늘려야 한다.Second, the amount of special chemical treatment and sputter etch must be increased to remove the polymer.

셋째, 폴리머가 많이 발생하기 때문에 질화 티타늄막을 식각하지 않고 금속배선을 형성하므로 상기 질화 티타늄막에 의해 저항이 증가하게 된다.Third, since a large amount of polymer is formed, metal wiring is formed without etching the titanium nitride film, thereby increasing resistance by the titanium nitride film.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 C3F8와 CO 및 Ar가스를 사용하여 질화 티타늄막을 식각하므로 폴리머가 발생하지 않는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems is to provide a method for manufacturing a semiconductor device that does not generate a polymer because the titanium nitride film is etched using C 3 F 8 and CO and Ar gas.

제1a도 내지 제1c도는 종래의 비아 콘택홀 형성 방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a conventional method for forming a via contact hole.

제2a도 내지 제2b도는 본 발명의 실시예에 따른 비아 콘택홀 형성 방법을 나타낸 공정 단면도2A through 2B are cross-sectional views illustrating a method of forming a via contact hole according to an exemplary embodiment of the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

31 : 반도체 기판 32 : 금속층31 semiconductor substrate 32 metal layer

33 : 질화 티타늄막 34 : 절연막33 titanium nitride film 34 insulating film

35 : 감광막35 photosensitive film

본 발명이 반도체 소자의 제조 방법은 기판상에 질화 티타늄막을 형성하는 단계와, 상기 질화 티타늄막상에 절연막을 형성하는 단계와, 상기 절연막과 질화 티타늄막을 C3F8와 CO 및 Ar가스 중 적어도 C3F8가스를 이용하여 선택적으로 제거하여 홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention includes forming a titanium nitride film on a substrate, forming an insulating film on the titanium nitride film, and forming the insulating film and the titanium nitride film at least C of C 3 F 8 , CO, and Ar gas. And selectively removing the 3 F 8 gas to form a hole.

상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.

도2a 내지 도2b는 본 발명의 실시예에 따른 비아 콘택홀 형성 방법을 나타낸 공정 단면도이다.2A through 2B are cross-sectional views illustrating a method of forming a via contact hole according to an exemplary embodiment of the present invention.

도2a에서와 같이, 반도체 기판(31)상에 금속층(32)과, 질화 티타늄(TiN)막(33)과, 제1TEOS층/USG층/제2TEOS층으로 이루어진 절연막(34)과, 감광막(35)을 차례로 형성한다.As shown in FIG. 2A, an insulating film 34 composed of a metal layer 32, a titanium nitride (TiN) film 33, a first TEOS layer, a USG layer, and a second TEOS layer is formed on the semiconductor substrate 31, and a photosensitive film ( 35) are formed in sequence.

여기서 상기 질화 티타늄막(33)은 반사 방지막으로 사용하며 건식 식각시 폴리머의 유발이 크다.In this case, the titanium nitride film 33 is used as an anti-reflection film and has a high induction of polymer during dry etching.

도2b에서와 같이, 상기 감광막(35)을 상기 반도체 기판(31)상의 소정 부위에 제거되도록 선택적으로 노광 및 현상한다. 이어 상기 선택적으로 노광 및 현상된 감광막(35)을 마스크로 이용하여 상기 절연막(34)과 질화 티타늄막(33)을 선택적으로 식각하여 홀을 형성한다.As shown in FIG. 2B, the photosensitive film 35 is selectively exposed and developed to be removed to a predetermined portion on the semiconductor substrate 31. FIG. Subsequently, the insulating layer 34 and the titanium nitride layer 33 are selectively etched using the selectively exposed and developed photosensitive layer 35 as a mask to form holes.

여기서 상기 절연막(34) 및 질화 티탄늄막(33)은 고농도 플라즈마 장치(High Density Plasma Machine)를 이용하여 식각한다. 이때 식각 방법은 질화 티타늄막(33)에 대해 고선택비를 갖는 C3F8와 Ar 및 CO가스를 주입하여 10mTorr 이하의 저압 공정으로 식각한 후, O2에 의해 클리닝(Cleaning)한다.In this case, the insulating film 34 and the titanium nitride film 33 are etched using a high density plasma machine. At this time, the etching method injects C 3 F 8 , Ar, and CO gas having a high selectivity to the titanium nitride film 33 and etches it in a low pressure process of 10 mTorr or less, followed by cleaning by O 2 .

상기 고농도 플라즈마 장치는 플라즈마 소스(Source)를 ICP(Inductively CouThe high concentration plasma apparatus uses an ICP (Inductively Cou) for a plasma source.

pled Plasma)로 하며, 상부 전극의 온도를 240℃∼280℃으로, 라디오 주파수 전력을 2000W∼3000W로 하고, 전부 전극의 온도를 -10℃이상으로, 라디오 주파수 전력을 700W∼1600W로 한다.pled plasma), the temperature of the upper electrode is 240 ° C to 280 ° C, the radio frequency power is 2000W to 3000W, the temperature of all the electrodes is -10 ° C or more, and the radio frequency power is 700W to 1600W.

그리고 상기 C3F8은 15∼28sccm의 유량을 갖고, CO는 5∼70sccm의 유량을 갖으며, Ar은 20∼300sccm의 유량을 갖는다.The C 3 F 8 has a flow rate of 15 to 28 sccm, CO has a flow rate of 5 to 70 sccm, and Ar has a flow rate of 20 to 300 sccm.

한편, 상기 홀을 형성함에 있어서, 상기 절연막(34)만을 C3F8가스를 이용하여 선택적으로 제거하여 홀을 형성할 수도 있다.Meanwhile, in forming the hole, only the insulating layer 34 may be selectively removed using a C 3 F 8 gas to form a hole.

이와 같이, C3F8와 CO 및 Ar에 의해 상기 절연막(34)과 질화 티탄늄막(33)을 식각하므로 금속성 폴리머도 발생하지 않는다.As described above, since the insulating film 34 and the titanium nitride film 33 are etched by C 3 F 8 , CO, and Ar, no metallic polymer is generated.

그리고 상기 감광막(35)을 제거한다.Then, the photosensitive film 35 is removed.

본 발명에 따른 반도체 소자의 제조 방법은 ICP플라즈마 소스와 C3F8, CO, Ar 가스를 사용하여 질화 티타늄막을 식각하므로 폴리머가 발생하지 않아 폴리머를 제거하기 위한 후 공정이 필요없고, 저항이 낮아 신호 전달 속도가 향상되는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention, since the titanium nitride film is etched by using an ICP plasma source and C 3 F 8 , CO, and Ar gas, no polymer is generated, and thus a post-process for removing the polymer is not required and the resistance is low. The signal transmission speed is improved.

Claims (6)

기판상에 질화 티타늄막을 형성하는 단계; 상기 질화 티타늄막상에 절연막을 형성하는 단계; 상기 절연막과 질화 티타늄막을 C3F8와 CO 및 Ar가스 중 적어도 C3F8가스를 이용하여 선택적으로 제거하여 홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 제조 방법.Forming a titanium nitride film on the substrate; Forming an insulating film on the titanium nitride film; And selectively removing the insulating film and the titanium nitride film using at least C 3 F 8 gas among C 3 F 8 , CO, and Ar gas to form holes. 제1항에 있어서, 절연막은 제1TEOS층/USG층/제2TEOS층을 차례로 증착하여 형성함을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the insulating layer is formed by sequentially depositing a first TEOS layer, a USG layer, and a second TEOS layer. 제1항에 있어서, 절연막 및 질화 티타늄막의 식각은 고농도 플라즈마 장치를 이용하고, 상기 고농도 플라즈마 장치는 플라즈마 소스를 ICP로 하여, 상부 전극의 온도를 240℃∼280℃으로, 라디오 주파수 전력을 200W∼3000W로 하고, 하부 전극의 온도를 -10℃이상으로, 라디오 주파수 전력을 700W∼1600W로 하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1, wherein the insulating film and the titanium nitride film are etched using a high concentration plasma apparatus, the high concentration plasma apparatus using a plasma source as an ICP, the temperature of the upper electrode at 240 ° C to 280 ° C, and the radio frequency power of 200 W to The method for manufacturing a semiconductor device, wherein the temperature of the lower electrode is -10 ° C or higher and the radio frequency power is 700W-1600W. 제1항에 있어서, C3F8가스를 15∼28sccm의 유량으로 하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method for manufacturing a semiconductor device according to claim 1, wherein the C 3 F 8 gas is set at a flow rate of 15 to 28 sccm. 제1항에 있어서, CO가스를 5∼70sccm의 유량으로 하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method for manufacturing a semiconductor device according to claim 1, wherein the CO gas is set at a flow rate of 5 to 70 sccm. 제1항에 있어서, Ar 가스를 20∼300sccm의 유량으로 하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method for manufacturing a semiconductor device according to claim 1, wherein the Ar gas is set at a flow rate of 20 to 300 sccm.
KR1019960039727A 1996-09-13 1996-09-13 Method of manufacturing semiconductor device KR100226793B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
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US7309652B2 (en) 2004-12-09 2007-12-18 Magnachip Semiconductor, Ltd. Method for removing photoresist layer and method for forming metal line in semiconductor device using the same

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KR100526574B1 (en) * 1998-06-30 2006-01-12 주식회사 하이닉스반도체 Contact hole formation method of semiconductor device
KR100546142B1 (en) * 1998-12-28 2006-04-12 주식회사 하이닉스반도체 Method for Manufacturing Contact Hole in Semiconductor Device_
KR100452421B1 (en) * 2001-12-27 2004-10-12 동부전자 주식회사 an extraneous matter removing method during metalization of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7309652B2 (en) 2004-12-09 2007-12-18 Magnachip Semiconductor, Ltd. Method for removing photoresist layer and method for forming metal line in semiconductor device using the same

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