KR100218349B1 - Isolation layer of semiconductor device and manufacturing method thereof - Google Patents
Isolation layer of semiconductor device and manufacturing method thereof Download PDFInfo
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- KR100218349B1 KR100218349B1 KR1019960077488A KR19960077488A KR100218349B1 KR 100218349 B1 KR100218349 B1 KR 100218349B1 KR 1019960077488 A KR1019960077488 A KR 1019960077488A KR 19960077488 A KR19960077488 A KR 19960077488A KR 100218349 B1 KR100218349 B1 KR 100218349B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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Abstract
본 발명은 저 유전상수를 가지는 반도체 소자의 층간 절연막 및 그 제조 방법에 관한 것으로, 그 구조는 반도체 기판의 상면에 패터닝된 배선금속층과, 상기 배선금속층을 둘러싸는 제1보호막과, 상기 제1보호막 및 상기 반도체 기판 상면에 형성된 에어로젤 층간 절연막과, 상기 에어로젤 층간절연막 상면에 형성된 제2보호막으로 구성된다. 본 발명에 따른 층간 절연막은 초임계건조공정으로 인해 부피 수축이 전혀 일어나지 않기 때문에, 초기의 도포 두께를 그대로 유지할 수 있는 효과가 있고, 또한 디자인 룰(design rule)이 0.2㎛이하의 반도체 소자의 층간 절연막의 제조에 응용할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlayer insulating film of a semiconductor device having a low dielectric constant and a manufacturing method thereof, the structure of which includes a wiring metal layer patterned on an upper surface of a semiconductor substrate, a first protective film surrounding the wiring metal layer, and the first protective film. And an airgel interlayer insulating film formed on an upper surface of the semiconductor substrate, and a second passivation film formed on an upper surface of the airgel interlayer insulating film. Since the interlayer insulating film according to the present invention has no volume shrinkage due to the supercritical drying process, there is an effect of maintaining the initial coating thickness as it is, and also the design rule (interlayer) of the semiconductor device having a design rule of 0.2 μm or less There is an effect applicable to the manufacture of an insulating film.
Description
제1a도∼제1d도는 종래 반도체 소자의 층간절연막을 제조하기 위한 순차적인 공정단면도.1A to 1D are sequential process cross-sectional views for manufacturing an interlayer insulating film of a conventional semiconductor device.
제2a도∼제2f도는 본 발명에 따른 반도체 소자의 층간 절연막을 제조하기 위한 순차적인 공정단면도.2A to 2F are sequential process cross-sectional views for producing an interlayer insulating film of a semiconductor device according to the present invention.
제3도는 본 발명에 따른 초임계 건조 조건 특성도.Figure 3 is a supercritical drying conditions characteristic diagram according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 배선 금속1: semiconductor substrate 2: wiring metal
3 : 제1 보호막 4 : 유기졸(Polymeric Sol)3: first protective film 4: organic sol
7 : 에어로젤(Aerogel) 층간 절연막 8 : 제2 보호막7: Aerogel interlayer insulating film 8: Second protective film
본 발명은 반도체 소자의 층간 절연막에 관한 것으로, 특히 저 유전상수(low dieletric constant)를 가지는 반도체 소자의 층간 절연막 및 그 제조 방법에 관한 것이다.The present invention relates to an interlayer insulating film of a semiconductor device, and more particularly, to an interlayer insulating film of a semiconductor device having a low dieletric constant and a method of manufacturing the same.
제1a도∼제1d도는 종래 반도체 소자의 층간절연막 및 그 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.1A to 1D illustrate a conventional interlayer insulating film and a method of manufacturing the same according to the accompanying drawings.
제1d도에 도시한 바와 같이, 종래 반도체 소자의 층간절연막은 반도체 기판(1)의 상면에 패터닝된 배선금속(2)층과, 상기 배선금속(2)층을 둘러싸는 플라즈마-테오스(이하 PE-TEOS라 한다) 산화막으로된 제1 보호막(3)과, 사이 제1 보호막(3) 및 반도체 기판(1) 상면에 형성된 O3-테오스 유에스지(이하 O3-TEOS USE라 한다)산화막(4)과, 상기 O3-TEOS USG 산화막(4) 상면에 형성된 제2 보호막(상기 제1 보호막과 같은)(5)으로 구성된다.As shown in FIG. 1D, an interlayer insulating film of a conventional semiconductor device has a wiring metal (2) layer patterned on the upper surface of the semiconductor substrate (1), and a plasma-theos (around the wiring metal (2) layer) A first protective film 3 made of an oxide film, and an O3-theus U.S. oxide (hereinafter referred to as O3-TEOS USE) formed on the upper surface of the first protective film 3 and the semiconductor substrate 1 (hereinafter referred to as PE-TEOS). 4) and a second protective film (such as the first protective film) 5 formed on the upper surface of the O3-TEOS USG oxide film 4.
이하, 종래 반도체 소자의 층간 절연막 제조방법을 설명한다.Hereinafter, a method for manufacturing an interlayer insulating film of a conventional semiconductor device will be described.
제1a도에 도시한 바와 같이, 반도체 기판(1)의 상면에 알루미늄(Al), 구리(Cu), 티타늄(Titanum), 폴리 실리콘(Poly-Si)중 어느 하나의 성분으로 된 배선금속(2)을 증착하고 패터닝하여 배선금속(2)층을 형성한다.As shown in FIG. 1A, a wiring metal 2 composed of any one of aluminum (Al), copper (Cu), titanium (Titanum), and polysilicon (Poly-Si) on the upper surface of the semiconductor substrate 1 ) Is deposited and patterned to form a wiring metal (2) layer.
제1b도에 도시한 바와 같이, 상기 1a의 공정후, 상기 배선금속(2)층과 반도체 기판(1)상면에 보호막의 역할을 하는 PE-TEOS 산화막(3)을 증착한 후 상기 배선금속(2)층 상에만 상기 PE-TEOS 산화막(3)이 남도록 하고, 나머지 부분은 제거한다.As shown in FIG. 1B, after the process of 1a, a PE-TEOS oxide film 3 serving as a protective film is deposited on the wiring metal 2 layer and the upper surface of the semiconductor substrate 1, and then the wiring metal ( 2) The PE-TEOS oxide film 3 remains only on the layer, and the rest is removed.
제1c도에 도시한 바와 같이, 상기 1b의 공정후, 상기 보호막(3) 및 반도체 기판(1)상에 O3-TEOS USG 산화막(4)을 400℃이하에서 증착한다. 증착된 상기 O3-TEOS USG 산화막(4)의 상면은 평탄하지 않고 울퉁불퉁하지만, 저온에서 평탄화가 가능하다. 상기 1c의 공정후, 상기 O3-TEOS 산화막(4)을 반응성이온 에칭백(RIE ETCHBACK)함으로써, 제1c도에 도시된 바와 같이, 상기 O3-TEOS USG 산화막(4)의 상면이 평탄하게 된다.As shown in FIG. 1C, after the process of 1b, an O 3 -TEOS USG oxide film 4 is deposited on the protective film 3 and the semiconductor substrate 1 at 400 ° C. or lower. The top surface of the deposited O 3 -TEOS USG oxide film 4 is not flat and uneven, but can be planarized at a low temperature. After the process of 1c, the O 3 -TEOS oxide film 4 is RIE ETCHBACK, so that the top surface of the O 3 -TEOS USG oxide film 4 is flat as shown in FIG. 1c. do.
제1c도의 공정 후, 상기 O3-TEOS USG 산화막(4)의 상면에 제2 보호막(제1 보호막과 같은)(5)을 형성함으로써, 제1d도에 도시된 바와 같이, 종래 반도체 소자의 층간 절연막이 완성된다.After the process of FIG. 1C, by forming a second protective film (such as the first protective film) 5 on the upper surface of the O 3 -TEOS USG oxide film 4, as shown in FIG. 1D, the interlayer of the conventional semiconductor device The insulating film is completed.
상기와 같이 형성된 반도체 소자의 층간절연막이외에도 여러 가지 방법에 의해 형성되는데, O3를 촉매로 사용하여 상압 화학 기상 증착(atm-pressure chemical vapor deposition:이하 APCVD라 칭함)법에 의해 형성된 테트라에틸 올소실리케이트(tetra ethyl ortho silicate: 이하 TEOS라 칭함)산화막과, 플라즈마 화학 기상 증착(plasma enhanced chemical vapor deposition:이하 PECVD라 칭함)에 의해 형성된 산화막과, 스핀-온-글래스(spin-on-glass:이하 SOG라 칭함)를 코팅/베이킹(Coating/Baking)하여 형성된 SOG막과, 고밀도 플라즈마 화학 기상 증착방법에 의해 형성된 산화막(High Density PECVD oxide film)과, 불소가 도핑되어 형성된 산화막 (F-Doped oxide film) 등이 있다.In addition to the interlayer insulating film of the semiconductor device formed as described above, it is formed by various methods, and tetraethyl allosilicate formed by atm-pressure chemical vapor deposition (APCVD) method using O 3 as a catalyst. Tetra ethyl ortho silicate (hereinafter referred to as TEOS), an oxide film formed by plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD), and spin-on-glass (hereinafter referred to as SOG). SOG film formed by coating / baking, High Density PECVD oxide film formed by high density plasma chemical vapor deposition method, and F-Doped oxide film formed by fluorine doping Etc.
그러나, 상기 다수 개의 산화막중에서 불소가 도핑되어 형성된 산화막은 유전상수가 3.2∼3.7정도이며, 다른 방법에 의해 형성된 산화막들의 유전상수는 약 4.0정도이다. 그러나, 상기한 바와 같은 방법을 사용하여 층간 절연막을 형성하는 경우, 반도체 소자의 배선간격이 0.3㎛이상일 경우에는 별문제가 없이 배선간을 절연시키는 절연막으로서 역할을 할 수 있지만, 반도체소자의 집적도가 증가하여 배선간격이 0.3㎛이하로 좁아지면, 층간 절연막의 유전상수는 배선간격이 넓은 경우보다 상대적으로 커지게 되므로 배선간을 절연시키지 못하게 되어 결국 단락(short)을 일으키는 문제점이 있었다.However, among the plurality of oxide films, an oxide film formed by fluorine doping has a dielectric constant of about 3.2 to 3.7, and a dielectric constant of oxide films formed by other methods is about 4.0. However, when the interlayer insulating film is formed using the method described above, when the wiring distance of the semiconductor device is 0.3 占 퐉 or more, it can serve as an insulating film to insulate the wiring without any problem, but the degree of integration of the semiconductor device is increased. Therefore, when the wiring spacing is narrowed to 0.3 占 퐉 or less, the dielectric constant of the interlayer insulating film becomes relatively larger than the case where the wiring spacing is wide, so that the wiring cannot be insulated, resulting in a short circuit.
본 발명의 목적은 반도체 소자의 집적도가 증가하여 배선 간격이 좁아지는 경우에도 단락을 일으키지 않도록 저 유전상수를 가진 반도체 소자의 층간 절연막을 제공함에 있다.An object of the present invention is to provide an interlayer insulating film of a semiconductor device having a low dielectric constant so as not to cause a short circuit even when the integration degree of the semiconductor device is increased and the wiring spacing is narrowed.
본 발명의 또 다른 목적은 반도체 소자의 집적도가 증가하여 배선 간격이 좁아지는 경우에도 단락을 일으키지 않도록 저 유전상수를 가진 반도체 소자 제조 방법을 제공함에 있다.It is still another object of the present invention to provide a method for manufacturing a semiconductor device having a low dielectric constant so as not to cause a short circuit even when the integration degree of the semiconductor device is increased and the wiring spacing is narrowed.
상기한 바와 같은 본 발명의 목적을 달성하기 위한 바람직한 일실시예에 따르면, 반도체 기판의 상면에 패터닝된 배선금속층과, 상기 배선금속층을 둘러싸는 제1보호막과, 상기 제1보호막 및 반도체 기판 상면에 형성된 에어로젤 층간 절연막과, 상기 에어로젤 층간 절연막 상면에 형성된 제2보호막으로 구성된 것을 특징으로 하는 반도체 소자의 층간 절연막이 제공된다.According to a preferred embodiment for achieving the object of the present invention as described above, a wiring metal layer patterned on the upper surface of the semiconductor substrate, a first protective film surrounding the wiring metal layer, and the first protective film and the upper surface of the semiconductor substrate There is provided an interlayer insulating film of a semiconductor device, comprising a formed airgel interlayer insulating film and a second protective film formed on an upper surface of the airgel interlayer insulating film.
본 발명에 따른 반도체 소자의 층간 절연막 제조방법은 반도체 기판의 상면에 배선금속을 증착하고 패터닝하여 배선금속층을 형성하는 단계와, 상기 배선금속층상면을 둘러싸도록 제1보호막을 형성하는 단계와, 상기 보호막 및 반도체기판상에 유기졸을 코팅하는 단계와, 상기 유기졸이 코팅된 반도체기판이 초임계건조공정을 통해 상기 유기졸을 에어로젤 층간 절연막으로 변형시키는 단계와, 그리고 상기 에어로젤층간 절연막상에 제2보호막을 형성하는 단계를 포함하여 이루어진 반도체 소자의 층간 절연막이 제공된다.A method of manufacturing an interlayer insulating film of a semiconductor device according to the present invention includes the steps of depositing and patterning a wiring metal on the upper surface of a semiconductor substrate to form a wiring metal layer, forming a first protective film to surround the upper surface of the wiring metal layer, and the protective film Coating an organic sol on a semiconductor substrate, transforming the organic sol into an airgel interlayer insulating film through a supercritical drying process, and a second layer on the airgel interlayer insulating film. An interlayer insulating film of a semiconductor device comprising the step of forming a protective film is provided.
이하, 본 발명에 따른 반도체 소자의 층간 절연막 및 그 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, an interlayer insulating film and a method of manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제2e도에 도시한 바와 같이, 본 발명에 따른 반도체 소자의 층간 절연막은 반도체 기판(1)의 상면에 패터닝된 배선금속(2)층과, 상기 배선금속(2)층을 둘러싸는 플라즈마-TEOS 산화막으로된 제1보호막(3)과, 상기 제1보호막(3) 및 반도체 기판(1) 상면에 형성된 에어로젤 층간 절연막(7)과, 상기 에어로젤 층간 절연막(7) 상면에 플라즈마-TEOS 산화막으로 형성된 제2보호막(8)으로 구성되어있다.As shown in FIG. 2E, the interlayer insulating film of the semiconductor device according to the present invention includes a wiring metal layer 2 patterned on the upper surface of the semiconductor substrate 1 and a plasma-TEOS surrounding the wiring metal layer 2. A first protective film 3 made of an oxide film, an airgel interlayer insulating film 7 formed on an upper surface of the first protective film 3 and a semiconductor substrate 1, and a plasma-TEOS oxide film formed on an upper surface of the airgel interlayer insulating film 7. The second protective film 8 is formed.
이하, 본 발명에 따른 반도체 소자의 층간 절연막 제조방법을 설명한다.Hereinafter, a method for manufacturing an interlayer insulating film of a semiconductor device according to the present invention will be described.
제2e도에 도시한 바와 같이, 반도체 기판(1)의 상면에 알루미늄(Al), 구리(Cu), 티타늄(Titanum), 폴리 실리콘(Poly-Si)중 어느 하나의 성분으로 된 배선금속(2)을 증착하고 패터닝하여 배선금속(2)층을 형성한다.As shown in FIG. 2E, a wiring metal 2 composed of any one of aluminum (Al), copper (Cu), titanium (Titanum), and polysilicon (Poly-Si) on the upper surface of the semiconductor substrate 1 ) Is deposited and patterned to form a wiring metal (2) layer.
제2b도에 도시한 바와 같이, 상기 2a의 공정후, 상기 배선금속(2)층과 반도체기판(1)상면에 보호막의 역할을 하는 플라즈마-TEOS 산화막을 증착한 후 상기 배선금속(2)층상에만 상기 플라즈마-TEOS 산화막이 남도록 하고, 나머지 부분은 제거한다.As shown in FIG. 2B, after the process of 2a, a plasma-TEOS oxide film serving as a protective film is deposited on the wiring metal 2 layer and the semiconductor substrate 1, and then on the wiring metal 2 layer. Only the plasma-TEOS oxide film remains, and the remaining portions are removed.
제2c도에 도시한 바와 같이, 상기 2b의 공정후, 상기 보호막(3) 및 반도체 기판(1)상에 TEOS 및 이소프로패널(Isopropanel)과 질산(Nitride)을 상온에서 혼합한 유기졸(4), 또는 TEOS 및 메탄올(Ethanol)과 질산을 상온에 혼합한 유기졸(4) 또는 TEOS 및 에탄올(Ethanol)과 질산을 상온에서 코팅(coating)한다.As shown in FIG. 2C, after the process of 2b, an organic sol (4) obtained by mixing TEOS, isopropanel, and nitric acid on the protective film 3 and the semiconductor substrate 1 at room temperature. ), Or an organic sol (4) or TEOS, ethanol (Ethanol) and nitric acid mixed with TEOS, methanol (Ethanol) and nitric acid at room temperature (coating) at room temperature.
상기 2c의 공정 후, 제2d도에 도시한 바와 같이, 상기 유기졸(4)을 코팅한 반도체 기판(1)을 오토클레이브(autoclave)(도시안됨)(일종의 압력솥과 유사한 장치)에 넣고, 초임계건조(Supercritical Drying)공정을 수행하여 에어로젤(Aerogel) 층간 절연막(7)을 형성한다. 상기 초임계건조공정은 제3도에 도시한 바와 같이, 유기졸(4)을 코팅한 반도체기판(1)을 임계점, 예를들면, 메탄올의 임계온도(Critical Temperature, Tc) 240℃ 및 임계압력(Critical Pressure, Pc) 7.93㎫, 에탄올의 임계온도 243℃ 및 임계압력 6.36㎫, 이상으로 승온,승압시키거나(5), 또는 일정한 온도에서 승압한 후 임계온도 및 임계압력이상으로 승온,승압시키고(6), 임계점 이후에 용매인 이소프로패널 및 메탄올 또는 에탄올을 배수시킨 후, 그 상태에서 온도를 일정하게 하고, 압력만을 수직강하시키는 공정이다. 이로인해 에어로젤 층간 절연막(7)이 형성된다. 상기 에어로젤층간절연막(7)은 기공율(porosity)이 90% 이상으로 매우 높기 때문에, 유전상수는 공기(air)의 유전상수인 1에 가까워지며, 상기 유기졸(4)은 초임계건조공정을 수행한 후에도 전혀 부피수축이 일어나지 않으므로, 초기에 코팅(coating)된 유기졸(4)의 두께를 그대로 유지한다.After the process of 2c, as shown in FIG. 2d, the semiconductor substrate 1 coated with the organic sol 4 is placed in an autoclave (not shown) (a device similar to a pressure cooker), and A critical drying process is performed to form an aerogel interlayer insulating film 7. In the supercritical drying process, as shown in FIG. 3, the semiconductor substrate 1 coated with the organic sol 4 is disposed at a critical point, for example, a critical temperature (Tc) of 240 ° C. and a critical pressure. (Critical Pressure, Pc) 7.93 MPa, the temperature is raised and elevated above the critical temperature of 243 ° C. and the critical pressure of 6.36 MPa of ethanol (5), or after the pressure is raised at a constant temperature, the temperature is raised and raised above the critical temperature and the critical pressure. (6) After draining the isopropanel and methanol or ethanol which are solvents after a critical point, temperature is made constant in that state, and only a pressure is dropped vertically. As a result, the airgel interlayer insulating film 7 is formed. Since the airgel interlayer insulating film 7 has a very high porosity of 90% or more, the dielectric constant becomes close to 1, which is the dielectric constant of air, and the organic sol 4 performs a supercritical drying process. Since volume shrinkage does not occur at all, the thickness of the initially coated organic sol 4 is maintained as it is.
제2e도에 도시한 바와 같이, 상기 2d의 공정후, 상기 에어로젤 층간 절연막(7)은 기공율이 높은 반면에, 표면의 거칠기 (roughness) 및 밀도가 낮으므로 플라즈마 산화막을 그 상면에 증착하여 보호막(8)을 형성하여 반도체 소자의 층간절연막이 완성된다.As shown in FIG. 2E, after the process of 2d, the airgel interlayer insulating film 7 has a high porosity, while the surface roughness and density are low, so that a plasma oxide film is deposited on the upper surface of the protective film ( 8) is formed to complete the interlayer insulating film of the semiconductor element.
상기 설명한 바와 같이 본 발명의 실시예에 따른 반도체 소자의 층간 절연막 및 그 제조방법에 의하면, 256M DRAM이상의 고집적화 반도체 소자의 제조 공정시, 초임계건조공정에 의해 층간 절연막을 제조함으로써 종래 층간 절연막에 비해 유전상수가 2배이상 낮은 저 유전상수를 가지는 절연막을 제공하는 효과가 있고, 초임계건조공정을 수행한 후에도 유기졸의 부피수축이 전혀 일어나지 않기 때문에, 초기의 도포 두께를 그대로 유지할 수 있는 효과가 있다. 또한, 디자인 룰(design rule)이 0.2㎛이하의 반도체 소자의 층간 절연막의 제조에도 응용할 수 있는 효과가 있다.As described above, according to the interlayer insulating film of the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, in the manufacturing process of the highly integrated semiconductor device of 256M DRAM or more, the interlayer insulating film is manufactured by a supercritical drying process, compared to the conventional interlayer insulating film. It has the effect of providing an insulating film having a low dielectric constant of more than two times the dielectric constant, and since the volume shrinkage of the organic sol does not occur even after performing the supercritical drying process, it is possible to maintain the initial coating thickness as it is. have. In addition, there is an effect that can be applied to the production of an interlayer insulating film of a semiconductor device having a design rule of 0.2 μm or less.
Claims (9)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960077488A KR100218349B1 (en) | 1996-12-30 | 1996-12-30 | Isolation layer of semiconductor device and manufacturing method thereof |
| JP9359108A JPH10214831A (en) | 1996-12-30 | 1997-12-26 | Inter-layer insulation film structure of semiconductor device, and its manufacturing method |
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| KR1019960077488A KR100218349B1 (en) | 1996-12-30 | 1996-12-30 | Isolation layer of semiconductor device and manufacturing method thereof |
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| KR100218349B1 true KR100218349B1 (en) | 1999-09-01 |
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