KR100218147B1 - Manufacturing process of semiconductor device load resistor - Google Patents

Abstract

An object of the present invention is to provide a method for manufacturing a load resistance of a semiconductor device having a high resistance value.

Method of manufacturing a load resistance of a semiconductor device of the present invention, forming a first insulating film on the semiconductor substrate; Forming a conductive layer pattern on a predetermined portion of the upper portion of the first insulating layer; Forming a second insulating layer on the semiconductor substrate on which the conductive layer pattern is formed; Forming an etch stop layer on the second insulating layer; Etching the etch stop layer and the second insulating layer to expose the surface of the conductive layer pattern; Forming a first polysilicon film on the second insulating film so as to contact the conductive layer pattern on the resultant material; Forming a third insulating film to fill the resultant; Removing the third insulating layer and the first polysilicon layer to expose the etch stop layer; And forming a resistance by forming a second polysilicon pattern to be in contact with the remaining first polysilicon film.

Description

Manufacturing method of load resistance of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a load resistor of a semiconductor device, and more particularly, to a method of manufacturing a load resistor of a semiconductor device in which the length of the resistor is increased to have a high resistance.

In general, SRAM is a volatile memory along with DRAM. Unlike DRAM, SRAM does not need to recharge periodically stored information and is easier to design than DRAM. Have

The configuration of such an SRAM device includes two pull-down drivers, two pull-up devices, and an access transistor. Among them, a resistor or a PMOS thin film transistor is used as the pull-up element.

Here, the manufacturing method of the load resistor used as the pull-up element of the SRAM will be described in detail with reference to FIG.

Referring to FIG. 1, first, a first insulating film 2 is formed on a semiconductor substrate 1, and a doped polysilicon film is deposited as a conductive layer thereon, and then a predetermined portion is etched to form a conductive layer pattern ( 3) form. Then, the second insulating layer 4 is deposited on the entire structure, and the second insulating layer 4 is etched by a predetermined portion to expose the lower conductive layer pattern 3 by a predetermined portion. Next, an undoped polysilicon film 5 for a resistor is deposited on the resultant, and a predetermined portion is patterned to complete the resistance.

However, since the resistor according to the conventional method does not have a high resistance per unit area, there is a problem that it is difficult to apply to the load resistance of the device such as the current SRAM that is becoming highly integrated.

In addition, since the upper surface of the resistor formed by the above process has a bend, it has a hassle to proceed a separate planarization process.

Accordingly, the present invention is to solve the above-mentioned conventional problems, and increases the length of the resistance based on the resistance formula (R = ρ1 / S, ρ: specific resistance, 1: length, S: area), thereby increasing the resistance value. An object of the present invention is to provide a method for manufacturing a load resistance of a semiconductor device.

In addition, another object of the present invention is to provide a method for manufacturing a load resistance of a semiconductor device that the top surface can be planarized without a separate planarization process.

1 is a view for explaining a load resistance manufacturing method of a conventional semiconductor device.

2 (a) to 2 (f) are cross-sectional views of respective manufacturing processes for explaining a method of forming a resistance of a semiconductor device according to the present invention.

* Explanation of symbols for main parts of the drawings

11 semiconductor substrate 12 first insulating film

13 conductive layer pattern 14 second insulating film

15 silicon nitride film 16, 21 mask pattern

17 contact hole 18 first polysilicon film

19: third insulating film 20: second polysilicon film

In order to achieve the above object of the present invention, a method of manufacturing a load resistance of a semiconductor device of the present invention, forming a first insulating film on the semiconductor substrate; Forming a conductive layer pattern on a predetermined portion of the upper portion of the first insulating layer; Forming a second insulating layer on the semiconductor substrate on which the conductive layer pattern is formed; Forming an etch stop layer on the second insulating layer; Etching the etch stop layer and the second insulating layer to expose the surface of the conductive layer pattern; Forming a first polysilicon film on the second insulating film so as to contact the conductive layer pattern on the resultant material; Forming a third insulating film to fill the resultant; Removing the third insulating layer and the first polysilicon layer to expose the etch stop layer; Forming a resistance by forming a second polysilicon pattern to contact the remaining first polysilicon layer.

According to the present invention, the contact cross-sectional area between the conductive layer pattern and the polysilicon film pattern for load resistance is reduced, and a double polysilicon film is formed as a resistance to increase the length of the load resistance.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 (a) to 2 (f) are cross-sectional views of respective manufacturing processes for explaining a method of manufacturing component resistance of a semiconductor device according to the present invention.

First, as shown in FIG. 2 (a), a first insulating film 12 is formed on the semiconductor substrate 11, and a doped polysilicon film is deposited thereon as a conductive layer. Subsequently, the doped polysilicon is partially etched to form the conductive layer pattern 13, and then the second insulating layer 14, for example, the TEOS layer is formed on the semiconductor substrate 1. Deposit to thickness. Subsequently, 300 to 1000 on the second insulating layer 14. A silicon nitride film 15 having a thickness of is formed.

Thereafter, as shown in FIG. 2 (b), a contact mask pattern 16 for exposing a predetermined portion of the conductive layer pattern 13 on the silicon nitride film 15 is formed by a known photolithography process. The silicon nitride film 15 and the second insulating film 14 are patterned in the form of the contact mask pattern 16 to form a contact hole 17 in which the conductive layer pattern 13 is partially exposed.

Next, as shown in FIG. 2 (c), after the contact mask pattern 16 is removed by a known removal method, impurities doped as a resistor are not doped on the resulting product of the semiconductor substrate 11. First polysilicon film 18 is 500 to 1000 Deposited to a thickness of < RTI ID = 0.0 > and then < / RTI > It is formed on the first polysilicon film 18 to a thickness of.

Subsequently, referring to FIG. 2D, the third insulating film 19 and the first polysilicon film 18 are etched back to expose the silicon nitride film 15. In this case, the third insulating layer 19 and the first polysilicon layer 18 may be etched back at the same etching rate. In the above etch back process, the first polysilicon film 18 and the third insulating film 19 of the groove portion generated by the bent portion T of the contact hole and the second insulating film, that is, the height of the conductive layer pattern 13 are formed. Is buried.

Then, as shown in FIG. 2 (e), the second polysilicon film 20 which is not doped with impurities on the etched back semiconductor substrate 11 is about 500 to 1000. After being deposited to a thickness, a mask pattern 21 is formed on the second polysilicon film 20 to limit the shape of the resistance.

Subsequently, as shown in FIG. 2 (f), the second polysilicon film 20 is patterned by the mask pattern 21 to complete the resistance according to the present invention.

In the present invention, the first and second polysilicon films are formed to surround the bent portion of the second insulating film and the third insulating layer portion in the contact hole, so that the length of the resistance is increased, whereby a resistance having a high resistance value is formed. do.

As described in detail above, according to the present invention, while reducing the contact cross-sectional area between the conductive layer pattern and the polysilicon film pattern for load resistance, the resistance is formed to surround the inner wall of the contact hole and the bent portion, so that the length of the resistance is increased. Is increased.

Thus, a load resistor having a high resistance value is formed.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (11)

Forming a first insulating layer on the semiconductor substrate; Forming a conductive layer pattern on a predetermined portion of the upper portion of the first insulating layer; Forming a second insulating layer on the semiconductor substrate on which the conductive layer pattern is formed; Forming an etch stop layer on the second insulating layer; Etching the etch stop layer and the second insulating layer to expose a predetermined portion of the conductive layer pattern; Forming a first polysilicon film on the second insulating film so as to contact the conductive layer pattern on the resultant material; Forming a third insulating film to fill the resultant; Removing the third insulating layer and the first polysilicon layer to expose the etch stop layer; And forming a resistance by forming a second polysilicon pattern in contact with the remaining first polysilicon film. The method of claim 1, wherein the first polysilicon film and the second polysilicon film are polysilicon films which are not doped with impurities. The method of claim 1 or 2, wherein the first polysilicon film and the second polysilicon film are 500 to 1000 The method of manufacturing a load resistor of a semiconductor device, characterized in that formed in a thickness. The method of claim 1, wherein the etch stop layer is a silicon nitride layer. The method of claim 4, wherein the etch stop layer is 300 to 1000 Method for manufacturing a load resistance of a semiconductor device, characterized in that deposited to a thickness of about. The method of claim 1, wherein the forming of the conductive layer pattern comprises: depositing a polysilicon layer doped with impurities on the first insulating layer; And partially patterning the polysilicon film. The method of claim 1, wherein the third insulating layer is a TEOS-ozone oxide layer. The method of claim 7, wherein the third insulating film is 5000 to 10000 Method for manufacturing a load resistance of a semiconductor device, characterized in that formed to a thickness of. The method of claim 1, wherein the third insulating layer and the first polysilicon layer are anisotropically etched by an etch back method so that the etch stop layer is exposed. The method of claim 9, wherein the third insulating layer and the first polysilicon layer are etched back at the same etching rate. The method of claim 1, wherein forming a second polysilicon pattern to contact the remaining first polysilicon layer comprises: depositing a second polysilicon layer on the semiconductor substrate; And patterning the second polysilicon film so as to contact the remaining first polysilicon film.