KR100328557B1 - Method for forming a metal line of semiconductor device - Google Patents
Method for forming a metal line of semiconductor device Download PDFInfo
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- KR100328557B1 KR100328557B1 KR1019990066404A KR19990066404A KR100328557B1 KR 100328557 B1 KR100328557 B1 KR 100328557B1 KR 1019990066404 A KR1019990066404 A KR 1019990066404A KR 19990066404 A KR19990066404 A KR 19990066404A KR 100328557 B1 KR100328557 B1 KR 100328557B1
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- South Korea
- Prior art keywords
- wiring
- insulating film
- forming
- groove
- wiring material
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000002184 metal Substances 0.000 title claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 26
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- 238000007796 conventional method Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 210000004185 liver Anatomy 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 배선을 형성할 부위에 배선의 크기보다 크게 홈 형태로 절연막을 형성하고, 상기 홈에 의한 단차부위와 더불어 배선물질의 스텝커버리지를 이용함으로써 주어진 면적내에서 배선간의 피치 제한을 효과적으로 개선시킬 수 있으며, 배선의 증착 두께에 의하여 자유롭게 배선 폭을 결정하고, 미리 형성하는 홈의 깊이로 원하는 배선의 높이를 결정하므로 공정의 난이도를 매우 쉽게 가져갈 수 있고, 제조공정 수율 향상에 따른 원가 절감과 배선의 레이아웃 효율을 극대화시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein an insulating film is formed in a groove shape at a portion where a wiring is to be formed to be larger than the size of the wiring, and the step coverage of the wiring material is used together with the stepped portion caused by the groove. It is possible to effectively improve the pitch limit between wirings within the area, and to freely determine the wiring width by the deposition thickness of the wiring, and to determine the desired wiring height by the depth of the grooves to be formed in advance, thus making the process difficulty very easy. In addition, the cost reduction and the layout efficiency of wiring can be maximized.
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 특히 배선간의 구분을 자기 정렬(Self-Align) 방법으로 구현하여 배선간의 절연 특성을 개선시킬 수 있고, 포토 리소그라피 공정의 영향을 받지 않고도 배선 라인간의 폭을 미세하게 형성할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and in particular, the separation between wirings can be implemented by a self-aligning method to improve insulation characteristics between wirings, and the wiring lines are not affected by the photolithography process. The present invention relates to a metal wiring forming method of a semiconductor device capable of forming a fine width of a liver.
일반적으로 반도체 소자의 집적도가 증가하면서 패턴의 미세화가 가속되어더욱 작은 배선의 폭이 요구되고 있다.In general, as the degree of integration of semiconductor devices increases, the miniaturization of patterns is accelerated, and smaller wiring widths are required.
그러나 상기 작은 배선의 폭을 구현하기 위해서는 미세 선폭을 형성할 수 있는 보다 정밀한 리소그라피(Lithography) 및 식각 기술이 요구되어지며, 특히 배선사이의 전기적 절연성을 확보해야 하는 문제점을 만족시켜야 한다.However, in order to realize the small wiring width, more precise lithography and etching techniques for forming a fine line width are required, and in particular, the problem of securing electrical insulation between the wirings must be satisfied.
또한 현재 리소그라피 기술의 한계에 의하여 배선의 폭과 스페이스(space)가 결정되므로 배선의 레이아웃 효율이 저하될 수 밖에 없으며, 배선간의 좁은 스페이스 마진에 따른 브리지 패일(Bridge fail)에 의한 불량발생이 더욱 심해진다.In addition, since the width and space of the wiring are determined by the limitations of current lithography technology, the layout efficiency of the wiring is inevitably deteriorated, and the failure of the bridge fail due to the narrow space margin between the wiring is more severe. Lose.
도 1 은 종래의 기술에 의해 금속배선이 형성된 상태를 도시한 도면으로서, 상기 도면에 도시된 바와 같이, 종래의 기술로는 리소그라피 및 식각기술 그리고 전기적 절연 특성이 결정해 준느 피치(폭 + 스페이스) 내에서만 레이아웃을 하여 배선을 형성할 수 밖에 없다. 따라서 반도체 소자 제품의 집적도를 높이고 칩 사이즈를 줄여 네트 다이(Net Die)를 증가시키는 데 한계가 있는 문제점이 있다.1 is a view showing a state in which metal wiring is formed by a conventional technique, as shown in the figure, the conventional technique is a pitch (width + space) determined by lithography and etching techniques and electrical insulation properties There is no choice but to lay out wiring by laying out the inside. Therefore, there is a limit in increasing the net die by increasing the integration of semiconductor device products and reducing the chip size.
따라서 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 본 발명은 배선간의 구분을 자기 정렬 방법으로 구현하여 배선간의 절연 특성을 개선시킬 수 있고, 포토 리소그라피 공정의 영향을 받지 않고도 배선 라인간의 폭을 미세하게 형성할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, the present invention can implement the separation between the wiring by the self-aligning method to improve the insulation characteristics between the wiring, the width between the wiring lines without being affected by the photolithography process It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device which can form a fine.
도 1 은 종래의 기술에 의해 금속배선이 형성된 상태를 도시한 단면도1 is a cross-sectional view showing a state in which metal wiring is formed by a conventional technique.
도 2a 내지 도 2e 는 본 발명의 방법에 따른 금속배선 형성방법을 도시한 단면도2A through 2E are cross-sectional views illustrating a metal wiring forming method according to the method of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 : 제1 절연막층 3 : 홈1: first insulating layer 3: groove
5 : 배선물질 7 : 희생 절연막5: wiring material 7: sacrificial insulating film
9 : 감광막 마스크 11 : 제2 절연막9: photosensitive film mask 11: second insulating film
상기 목적을 달성하기 위한 본 발명의 금속배선 형성방법은,Metal wiring forming method of the present invention for achieving the above object,
실리콘 기판상에 공지의 방법으로 트랜지스터 등의 단위소자를 형성하고, 그상부에 제1 절연막을 형성한 후 평탄화 하는 공정과;Forming a unit element such as a transistor on a silicon substrate by a known method, forming a first insulating film thereon, and then flattening it;
상기 제1 절연막의 배선이 형성될 위치의 아래 부분을 배선의 높이를 고려하여 일정깊이만큼 제거하여 홈을 형성하는 공정과;Forming a groove by removing a portion below the position where the wiring of the first insulating film is to be formed by a predetermined depth in consideration of the height of the wiring;
상기 홈에 의한 단차를 이용하여 원하는 배선 폭만큼의 두께로 배선물질을 상기 구조의 전면에 증착하는 공정과;Depositing a wiring material on the entire surface of the structure to a thickness of a desired wiring width by using the step by the groove;
전체구조의 상부 전면에 희생 절연막을 전면에 증착하는 공정과;Depositing a sacrificial insulating film on the entire upper surface of the entire structure;
상기 희생 절연막과 상기 배선물질 사이에 선택비가 같은 식각기로 식각하여 상기 희생 절연막의 측벽에만 상기 배선물질이 남아 있도록 하는 공정과;Etching the same between the sacrificial insulating film and the wiring material with an etcher such that the wiring material remains only on sidewalls of the sacrificial insulating film;
상기 홈의 반대편 일측벽의 배선물질 부위만을 별도의 마련된 마스크를 이용하여 제거하는 공정과;Removing only a wiring material portion of one side wall opposite the groove using a separate mask;
전체 구조 상부에 제 2 절연막을 증착한 후 연마하여 평탄화 하는 공정을 포함하는 것을 특징으로 한다.And depositing a second insulating film over the entire structure and then polishing and planarizing the second insulating film.
이하 첨부된 도면을 참조하여 본 발명에 대해 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e 는 본 발명의 방법에 따른 금속배선 형성방법을 도시한 단면도이다.2A to 2E are cross-sectional views illustrating a metal wiring forming method according to the method of the present invention.
먼저 도 2a를 참조하면, 실리콘 기판상에 공지의 방법으로 트랜지스터 등의 단위소자를 형성하고, 그 상부에 제1 절연막(1)을 사용하여 평탄화 한다.Referring first to FIG. 2A, a unit device such as a transistor is formed on a silicon substrate by a known method, and planarized by using the first insulating film 1 thereon.
상기 제1 절연막(1)의 소정부위, 예컨데 배선이 형성될 위치의 아래 부분을 배선의 높이를 고려하여 일정깊이만큼 제거하여 홈(3)을 형성한다. 이때 상기 배선이 형성될 부위의 상기 제1 절연막(1)을 식각하되, 포토 리소그라피 공정의 허용하는 범위내에서 홈형태로 구현한 후 식각하여 홈(3)에 의한 단차를 형성한다.The groove 3 is formed by removing a predetermined portion of the first insulating layer 1, for example, a portion below the position where the wiring is to be formed, by a predetermined depth in consideration of the height of the wiring. In this case, the first insulating film 1 of the portion where the wiring is to be formed is etched, but is formed in a groove shape within the allowable range of the photolithography process and then etched to form a step by the groove 3.
이때 상기 홈(3)은 배선의 크기보다 큰 크기로 한다.At this time, the groove 3 is larger than the size of the wiring.
예컨데, 상기 배선의 높이를 결정하는 제1 절연막의 홈(3) 깊이는 500∼10,000Å로 한다.For example, the depth of the groove 3 of the first insulating film for determining the height of the wiring is set to 500 to 10,000 mW.
도 2b를 참조하면, 상기 홈(3)에 의한 단차를 이용하여 원하는 배선 폭만큼의 두께로 배선물질(5)을 상기 구조의 전면에 증착한다. 이어 또 다른 희생 절연막(7)을 전면에 증착한다.Referring to FIG. 2B, the wiring material 5 is deposited on the entire surface of the structure to a thickness equal to the desired wiring width by using the step by the groove 3. Next, another sacrificial insulating film 7 is deposited on the entire surface.
한편, 상기 배선물질로 폴리실리콘, WSi2, 폴리사이드, Ti-Silicide, W, Al 중 임의의 어느 하나의 배선물질을 사용하며, 상기 배선물질의 중착두께는 50∼1000Å 로 한다.Meanwhile, any one of polysilicon, WSi 2 , polyside, Ti-Silicide, W, and Al may be used as the wiring material, and the thickness of the wiring material may be 50 to 1000 kW.
도 2c를 참조하면, 상기 희생 절연막(7)과 상기 배선물질(5) 사이에 선택비가 같은 식각기(Etchant)로 이방성 건식식각을 하여 상기 희생 절연막(7)의 측벽에만 상기 배선물질(5)이 남아 있도록 한다.Referring to FIG. 2C, anisotropic dry etching is performed using an etchant having the same selectivity between the sacrificial insulating film 7 and the wiring material 5, so that only the wiring material 5 is formed on the sidewall of the sacrificial insulating film 7. Should remain.
이때, 상기 희생 절연막(7)과 상기 배선물질(5) 사이에 선택비가 같은 식각기로 식각할 때, 배선의 높이가 최초 홈(3)의 깊이의 50%∼80%가 되게 한다.At this time, when the etching rate between the sacrificial insulating film 7 and the wiring material 5 is etched by the same etching, the height of the wiring is 50% to 80% of the depth of the first groove 3.
도 2d를 참조하면, 불필요한 상기 홈(3)의 반대편 일측벽의 배선물질 부위(5)를 별도의 마스크(9)를 이용하여 노출시키고, 이어 건식 식각 혹은 습식식각으로 제거하여 원하는 배선만을 남긴다.Referring to FIG. 2D, the wiring material portion 5 of the one side wall opposite to the groove 3 is unnecessary by using a separate mask 9 and then removed by dry etching or wet etching to leave only desired wiring.
이때 상기 배선의 폭은 배선물질(5)의 두께에 따라 결정되므로 원하는 대로 미세하게 형성할 수 있다.At this time, since the width of the wiring is determined according to the thickness of the wiring material 5, it can be formed finely as desired.
도 2e를 참조하면, 전체 구조 상부에 제 2 절연막(11)을 증착한 후 화학적 기계적 연마(Chemical Mechanical Polishing ; 이하 'CMP'라 함)로 평탄화 한 후, 후속공정을 진행한다. 이때 상기 제2 절연막(11) 증착공정 및 평탄화 공정을 통하여 미세하게 형성된 배선(5)의 쓰러짐 등을 방지할 수 있다.Referring to FIG. 2E, the second insulating layer 11 is deposited on the entire structure, and then planarized by chemical mechanical polishing (hereinafter referred to as 'CMP'), and then a subsequent process is performed. At this time, the second insulating film 11 may be prevented from falling down through the finely formed wiring 5 through the deposition process and the planarization process.
상기와 같은 본 발명의 방법으로 배선을 형성할 경우, 포토 공정 능력에 관계없이 배선물질의 증착 두께, 예컨데 50Å 이상의 증착 두께에 따라 그 폭을 결정할 수 있는 초미세 배선공정이 가능하고, 배선의 쓰러짐도 효과적으로 방지할 수 있다.When the wiring is formed by the method of the present invention as described above, an ultra-fine wiring process is possible to determine the width according to the deposition thickness of the wiring material, for example, 50 kPa or more, regardless of the photoprocessing capability, and the wiring collapses. Can also be effectively prevented.
따라서 배선의 폭은 배선물질의 증착 두께에 의하여 조절이 가능하고, 배선의 높이는 홈 깊이에 의해 조절이 가능해 지므로 종래의 배선두께를 조절하기 위하여 물질의 증착 두께를 조절해야 하는 한계에서 벗어 날 수 있다.Therefore, the width of the wiring can be controlled by the deposition thickness of the wiring material, and the height of the wiring can be adjusted by the groove depth, so that the thickness of the conventional wiring thickness can be adjusted to control the deposition thickness of the material. .
한편, 상기 본 발명의 방법과 비슷한 방식으로 다마신 공정(Damacene Process)를 들 수 있으나, 이는 홈 부분 전체를 이용하는 기술로서, 결국 홈의 크기를 구현하는 포토 공정의 의존성을 탈피할 수 없는 문제점이 있다.On the other hand, the damascene process (Damacene Process) can be mentioned in a similar manner to the method of the present invention, which is a technique using the entire groove portion, the problem that can not escape the dependence of the photo process to implement the size of the groove after all have.
이상 상술한 바와 같은 본 발명의 방법은 배선을 형성할 부위에 배선의 크기보다 크게 홈 형태로 절연막을 형성하고, 상기 홈에 의한 단차부위와 더불어 배선물질의 스텝커버리지를 이용함으로써 주어진 면적내에서 배선간의 피치 제한을 효과적으로 개선시킬 수 있으며, 배선의 증착 두께에 의하여 자유롭게 배선 폭을 결정하고, 미리 형성하는 홈의 깊이로 원하는 배선의 높이를 결정하므로 공정의 난이도를 매우 쉽게 가져갈 수 있고, 제조공정 수율 향상에 따른 원가 절감과 배선의 레이아웃 효율을 극대화시킬 수 있다.As described above, the method of the present invention forms an insulating film in the shape of a groove larger than the size of the wiring in the site where the wiring is to be formed, and uses the step coverage of the wiring material together with the step portion caused by the groove to provide wiring within a given area. It is possible to effectively improve the pitch restriction between the wires, and to freely determine the wiring width by the deposition thickness of the wiring, and to determine the desired wiring height by the depth of the grooves to be formed in advance, the difficulty of the process can be very easily obtained, and the manufacturing process yield The cost reduction and the layout efficiency of wiring can be maximized.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990066404A KR100328557B1 (en) | 1999-12-30 | 1999-12-30 | Method for forming a metal line of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990066404A KR100328557B1 (en) | 1999-12-30 | 1999-12-30 | Method for forming a metal line of semiconductor device |
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| KR20010059026A KR20010059026A (en) | 2001-07-06 |
| KR100328557B1 true KR100328557B1 (en) | 2002-03-15 |
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