KR100213230B1 - Test method for core and embedded memory circuit - Google Patents

Abstract

A test method for core and memory embedded circuits is disclosed in which a boundary scan cell is inserted into a core and an embedded magnetic test circuit is inserted into a memory, and a connection part of the block and an existing macro block is also taken into consideration when generating an automatic test pattern.

In a test method for a core and a memory embedded circuit for testing a circuit in which a macro block such as a core and a memory of a semiconductor device and a logic block such as a scan cell and a memory embedded self test circuit except the macro block are mixed, an embedded core Scan-Flip by inserting boundary scan cells to test, inserting flip-flops into the memory's built-in magnetic test circuit and the memory's input and output stages, and applying scan design techniques to logic block parts other than the embedded core and memory Provides test methods for core and memory-embedded circuits that organize the flops into scan chains.

Therefore, according to the present invention, in a test method for a core and a memory embedded circuit of a semiconductor device, a boundary scan cell and a memory embedded magnetic test circuit are inserted, and the connection part between the block and the existing macro block is also taken into consideration when generating an automatic test pattern. This provides a test method for core and memory embedded circuits that extends the defect detection range.

Description

Test Methods for Core and Memory Embedded Circuits

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for a core and a memory embedded circuit of a semiconductor device, and more particularly, inserting a boundary scan cell into a core and an embedded magnetic test circuit into a memory, and connecting the block and an existing macro block to an automatic test pattern. The present invention relates to a test method for a core and a memory embedded circuit for testing.

In general, as digital integrated circuits become larger and more complex, embedding a core or a memory in a chip has become common. In addition, test vector generation using Scan Design and Automatic Test Pattern Generation (ATPG) programs are also common for efficient testing of digital integrated circuits. These integrated circuits have a mix of logic blocks inside the core, memory and these macro blocks. By the way, the embedded core is not in the form of a gate level that the automatic test pattern generator can generate a test vector. And memory uses a different fault model, unlike regular logic. So in the case of cores, test vectors are developed with the development of the core and given to the designer, and it is common to test the memory through a special algorithm. Therefore, a test method for a circuit including a core and a memory must be prepared. Therefore, if a core or a memory is embedded in the circuit in this way, the test is performed using this, and the memory is tested using the in-memory self-test circuit. In addition, after the scan design, the rest of the logic blocks obtain a test vector through an automatic test pattern generation program. In this case, a macro block such as a memory or a core is used by the automatic test pattern generation tool (Function) within the block. Because it is not recognized, the test vector cannot be generated for macroblocks such as core or memory and logic blocks, and fault coverage of the logic blocks is degraded.

In addition, the conventional test method has to test a macro block such as a core or a memory and other logic blocks separately, and a disadvantage in that the connection between the macro block and the logic block is not properly performed.

SUMMARY OF THE INVENTION The present invention provides a test method for a core and a memory embedded circuit of a semiconductor device, wherein a boundary scan cell is inserted into a core and an embedded magnetic test circuit is inserted into a memory, and the connection between the block and the existing macro block is also automatically tested. The present invention provides a test method for a core and a memory-embedded circuit for testing in consideration of pattern generation.

1 is a block diagram of an embedded core circuit test method using a boundary scan cell in accordance with the present invention;

2 is a circuit diagram of a boundary scan cell according to the present invention;

Explanation of symbols for the main parts of the drawings

121 ... boundary scan cell 126 ... scan chain

In order to achieve the above object, the present invention provides a core and a memory for testing a circuit in which a macro block such as a core and a memory of a semiconductor device and a logic block such as a scan cell and a memory-embedded magnetic test circuit except for such a macro block are mixed. A circuit test method comprising: inserting a boundary scan cell for testing an embedded core, a flip-flop at the input and output terminals of the memory embedded magnetic test circuit and memory, and a logic block excluding the embedded core and memory It provides a test method for core and memory embedded circuits by applying a scan design technique to a portion to configure a scan flip-flop into a scan chain.

The boundary scan cell for testing the embedded core is inserted into the input and output stages of the core circuit and configures the boundary scan chain into a scan chain.

The boundary scan cell for testing the embedded core is inserted around the core so that the core can be tested when a test vector is given.

Preferably, the boundary scan cell for testing the embedded core has a test input so that when the test input is high, the signal entering the core is replaced with the signal from the boundary scan cell and the signal from the core is sent to the boundary scan cell for testing. Do it.

The boundary scan cell for testing the embedded core shifts the test vector through the scan chain and shifts the output to test the core output against the expected value of a given test vector.

The in-memory magnetic test circuit inserts between the memory's address, data and other control signals to test the memory.

Preferably, the flip-flops inserted at the input and output ends of the memory are designed to be scan flip-flops and connected to the scan chain according to the scan design method.

The scan flip-flop is configured as a scan chain by applying a scan design technique to the logic block portion except for the embedded core and memory, which is configured at the input and output ends of the embedded core and the memory. Enable observation of the signal.

Therefore, according to the present invention, in a test method for a core and a memory embedded circuit of a semiconductor device, a boundary scan cell and a built-in magnetic test circuit are inserted into a core and a connection portion between the block and an existing macro block is also generated when an automatic test pattern is generated. By considering and testing, it is possible to provide a test method for core and memory embedded circuits that extends the defect detection range.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

1 is a block diagram of an embedded core circuit test method using a boundary scan cell according to the present invention. Referring to the drawings, in the embedded core circuit test method using the boundary scan cell according to the present invention, the boundary scan cell 121 is inserted around the embedded core, and the input and output pins of each boundary scan cell are inserted into the core core circuit. Connect each pin and terminal outside the core circuit, and configure each boundary scan cell into a single scan chain.

2 is a circuit diagram of a boundary scan cell according to the present invention. Referring to the drawings, the boundary scan cell circuit according to the present invention is composed of MUX 232 and 237 and D-Flipflop 244 and 245. The input and output pins of the boundary scan cell are used to insert into the core original input or output stages. The scan input pins and scan output pins of the boundary scan cells are used to configure the boundary scan cells inserted around the core into one scan chain. The scan input and scan output of the configured scan chain connect to the outside of the integrated circuit. In addition, the test inputs, shifts, first clock, and second clock pins of all boundary scan cells inserted around the core are connected to pins of the same name and to the outside of the integrated circuit for direct control from outside the circuit. In this case, the clock input of the core should be directly controllable from the outside during the test using the mux 232 or the like.

The test vector given with the core is made only by considering the input and output pins of the core, so that if the core is built into the circuit, it cannot be used. However, using the structure as shown in FIG. 1, when a test vector is given, the core can be tested through a boundary scan cell inserted around the core. First, set the test pin of the boundary scan cell to '1' to replace the signal entering the embedded core with the signal from the boundary scan cell rather than the original signal, and intercept the signal from the embedded core with the boundary scan cell. Make sure The built-in core test follows this sequence: First, one line of a given test vector input is shifted-in through the scan chain. Next, the second clock signal and the clock of the core are applied one cycle. It then shifts out through the scan chain to compare the output of the core with the expected value of a given test vector. Simultaneously shifts out the next input of the test vector. The second clock signal and the clock of the core are added one cycle until all the test vectors are applied.

In embedded memory testing, an additional built-in self test (BIST) circuit is inserted between the memory address, data, and other control signals. The test of the memory is performed by the embedded memory-embedded magnetic test circuit, which does not define the method or structure, but uses a flip-flop structure for testing the memory at the input and output of the memory. These flip-flops must be designed as scan flip-flops according to the scan design method used in the test method of the logic block and connected to the scan chain composed of the logic blocks. By inserting the in-memory self-test circuit, a flip-flop inserted at the input and output ends of the memory is connected to the scan chain of the logic blocks so that the memory block does not know the content when generating the test vector of the logic block, that is, a black box. Processing with (Black Box) prevents the defect detection coverage of the logic block from being lowered. The memory test is performed according to the implemented in-memory magnetic test circuit method.

The scan design is applied to the logic block part except the embedded core, memory, and the like. According to the scan design rules, all of the flip-flops to which the scan design is applied are replaced with scan flip-flops, and these flip-flops are composed of one or more scan chains. Configuring the scan chain in the circuit connects the scan enable pin to the outside of the circuit and uses a constant pin as the scan clock pin.

Once the circuit has been configured with a scan chain, automatic test pattern generation is performed to generate test vectors, with some precedence for the embedded core and embedded memory.

First, the embedded core is treated as an unknown black box when generating an automatic test pattern, so that the input to the core cannot be observed at all from the outside, and the output of the core is treated as an unknown value ('X'). This should prevent you from generating vectors that test the circuits connected to the output of the core. For this purpose, a boundary scan cell inserted around the core is used. During the test, the test input and the second clock signal of FIG. 2 are fixed to '1'. Apply a shift pin equal to the scan enable signal of the circuit. The first clock pin is applied with the same value as the scan clock signal of the circuit. In this case, the scan chain connected around the core has the same function as the scan chain inserted in the random logic so that the automatic test pattern generation tool can recognize the new test chain as one new scan chain and perform automatic test pattern generation. . The memory is also processed into a block whose contents are unknown when the automatic test pattern is generated, that is, a black box, so that the value input into the memory cannot be observed, and the output of the memory is treated as an unknown value ('X'). This prevents them from generating test vectors for circuits connected to the output of the memory. To this end, the scan chain of the logic blocks includes flip-flops inserted into the memory input and output terminals of the circuit of the memory embedded self test circuit when the memory embedded self test circuit is inserted.

Since scan chains are configured at the input and output stages of the embedded core and memory, signals entering the embedded core or memory can be observed at scan cells located at the input stage. In addition, the circuit connected to the output core of the embedded core and the memory can be applied with a desired value through a cell scan located at the output terminal. Therefore, even if the core or the memory embedded in the automatic test pattern generation is recognized as an unknown block, it is possible to prevent the defect detection application range of the logic block from being lowered.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, according to the present invention, in a test method for a core and a memory embedded circuit of a semiconductor device, a boundary scan cell and a built-in magnetic test circuit are inserted into a core, and the connection portion between the block and the existing macro block is also automatically tested. By testing in consideration of pattern generation, it is possible to provide a test method for core and memory embedded circuits that extends a defect detection range.

Claims (8)

In a test method for core and memory embedded circuits for testing a circuit in which a macro block such as a core and a memory of a semiconductor device and a logic block such as a scan cell and a memory built-in magnetic test circuit except for such a macro block are mixed, Insert boundary scan cells to test embedded cores, insert flip-flops into the memory input and output stages of memory embedded self-test circuits and memory, and apply scan design techniques to logic block portions other than embedded cores and memories To configure a scan flip-flop into a scan chain. The test method according to claim 1, wherein the boundary scan cell for testing the embedded core is inserted into the input and output ends of the core circuit and configures the boundary scan chain as a scan chain. . The test method of claim 1, wherein the boundary scan cell for testing the embedded core is inserted around the core so that the core can be tested when a test vector is given. The boundary scan cell of claim 1, wherein the boundary scan cell for testing the embedded core has a test input, and when the test input is high, replaces the signal entering the core with the signal from the boundary scan cell and replaces the signal from the core with the boundary scan cell. Test method for the core and memory built-in circuit, characterized in that the test by sending. The method of claim 1, wherein the boundary scan cell for testing the embedded core shifts a test vector through a scan chain and shifts the output to compare the output of the core with an expected value of a given test vector. Test method for core and memory embedded circuits. 2. The test method of claim 1 wherein the embedded memory test circuit tests the memory by inserting it between addresses, data, and other control signals of the memory. The test method of claim 1, wherein the flip-flop inserted into the input and output terminals of the memory is designed as a scan flip-flop and connected to a scan chain according to a scan design method. . The method of claim 1, wherein the scan flip-flop is configured as a scan chain by applying a scan design technique to a logic block portion other than the embedded core and the memory, since the scan flip-flop is configured at the input and output ends of the embedded core and the memory. A test method for a core and a memory embedded circuit, which enables observation of a signal entering the core or memory.

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