JPH0288980A - Method for testing logic circuit - Google Patents

Abstract

PURPOSE:To easily test a logic circuit in a simple processing way by measuring a standby current after flip flops incorporated in the logic circuit as forcibly set to hold state and a source gate group on a tri-state bus forcibly set to a disable state. CONSTITUTION:Flip flop controlling signal suppression circuits 11 and 13 which forcibly set flip flops 22 and 26 to hold states and a tri-state bus control circuit 12 which forcibly sets tri-state elements 24a and 24b to non-high impedance states are provided. At the time of performing a standby current measuring test for testing a logic circuit, the flip flops 22 and 26 and tri-state elements 24a and 24b incorporated in the logic circuit are respectively set forcibly to hold states and non-high impedance states. Therefore, the testing cost of a logic circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit testing method, and more particularly to a logic circuit testing method for identifying manufacturing defects in the logic circuit by measuring standby current.

[Conventional technology]

In the CMO8 logic circuit, the P-channel MO8 and the N-channel MO8 are connected in a complementary manner, so that when the input potential level is stationary.

Either the P channel MO8 or the N channel MO8 is always in a cutoff state. Therefore, there is no bus through which current flows from the power supply, and no current should flow; however, in reality, a reverse bias current flows across the whole-N junction, including the parasitics that exist within the chip of the CMOS logic circuit.

As a means of identifying manufacturing defects in CMO8 logic LSIs and the like, an extremely small reverse bias current (standby current) flowing through the PN junction of a CMO8 logic circuit with a stable input potential level is measured. Then, if the determined standby current is significantly different from the standard standby current, a test is performed to determine that the measured CMO5 logic circuit component is defective.

For standby current measurement, it is necessary that the input potential level of the internal cells be stable.

For this purpose, 1. Either create a dedicated test pattern that stabilizes the input potential of all cells in the circuit using normal logic operation, or extract the input potential stable state in logic operation using an existing test pattern and perform the test. I try to do it.

[Problem to be solved by the invention]

However, when designing a dedicated test pattern for standby current measurement, (1) it is necessary to use normal logic operation as a processing procedure to establish the internal flip-flop in the hold state during testing; The procedure is complicated.

(2) The processing procedure for establishing the internal tristate bus into a non-high-impedance state during testing requires the use of normal logic operations, making the processing procedure complicated.

(3) Also, when actually testing, it is necessary to simultaneously set the internal flip-flops to the hold state and the internal tri-state bus to the non-high-impedance state for the entire circuit. It is difficult to design procedures and confirm that conditions hold.

(4) Furthermore, the cost of designing and confirming test patterns to set the conditions for the states in (1), (2), and (3) above for many circuit internal states of one logic circuit is large. There was a problem.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic circuit testing method that measures standby current using simple processing procedures and easily tests logic circuits.

Another object of the present invention is to provide a logic circuit testing method that easily tests a logic circuit by measuring standby current using any existing test pattern.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention forcibly puts a flip-flop built in the logic circuit into a hold state in a test mode for the logic circuit to be tested.
Test the logic circuit by forcibly disabling all the source gates on the tri-state bus built into the logic circuit, except for the test signal application gate, and measuring the standby current to determine circuit failure. A method of testing a logic circuit is provided.

Further, the logic circuit testing method of the present invention includes a flip-flop control circuit that forcibly holds a flip 70 block built in the logic circuit in a hold state in a test mode, and a source on a tristate bus built in the logic circuit. The logic circuit under test is provided with a tri-state bus control circuit that forcibly disables all gate groups except for the test signal application gate in a test mode, and the flip-flop control circuit and the tri-state bus control circuit are separately configured. The present invention is characterized in that a period in which the entire circuit is in a static stable state is provided during a test cycle in which a test pattern signal is applied, and a standby current is measured to determine a circuit failure.

Furthermore, in the logic circuit testing method of the present invention,
In a test mode for testing a logic circuit, the first step is to apply an arbitrary test pattern to the logic circuit under test, and the second step is to force the flip-flops built into the logic circuit into a hold state. , a third step of forcibly disabling all the source gates on the tri-state bus built in the logic circuit except for the test signal application gate, and a fourth step of measuring the standby current. A fifth step of releasing a forced disable state of a group of source gates on a built-in tri-state bus, and a sixth step of releasing a forced hold state of a flip-flop built into a logic circuit. It is characterized by being repeated sequentially.

[Effect]

According to the above means, when testing a logic circuit, a flip-flop built in the logic circuit under test is forcibly put into a hold state, and a source on a tristate bus built in the logic circuit is forced to be in a hold state. A circuit failure is determined by forcibly disabling all gate groups except for the test signal application gate and measuring the standby current.

Thereby, circuit defects in the logic circuit can be easily and reliably determined without the need for testing using complicated test patterns.

In addition, in order to test such logic circuits, a flip-flop control circuit that forcibly puts the flip-flops built into the logic circuit into a hold state in test mode, and a The logic circuit under test is equipped with a tri-state bus control circuit that forcibly disables all source gates except for the test signal application gate in test mode.
The flip-flop control circuit and the tristate bus control circuit are individually controlled to provide a period during which one entire circuit is in a static stable state in a test cycle in which a test signal is applied, and a standby current is measured. , determine circuit failure.

Thereby, circuit defects in the logic circuit can be easily and reliably determined without the need for testing using complicated test patterns.

In addition, the logic circuit testing method performed here is a first test in which an arbitrary test pattern is applied to the logic circuit under test.
step, and a second step that forcibly puts the flip-flops built into the logic circuit into a hold state, and a second step that forces all the source gates on the tri-state bus built into the logic circuit except for the test signal application gate. A third step of disabling the logic circuit, a fourth step of measuring the standby current, a fifth step of releasing the forced disable state of a group of source gates on a tri-state bus built in the logic circuit, and a fifth step of disabling the logic circuit. This is performed by sequentially repeating the process including the sixth step of releasing the forced hold state of the flip-flop built in the circuit.

This makes it possible to realize a state for standby current measurement and add test items for standby current measurement during a logic circuit test process in which a logic circuit is tested for an arbitrary test pattern. Therefore, it is possible to easily and reliably determine a circuit defect in a logic circuit by adding a test item for measuring standby current without performing a test using a complicated test pattern.

In order to perform such a logic circuit testing method reliably and easily, the logic circuit under test includes, for example.

When designing a logic circuit, (1) A flip-flop circuit that suppresses control signals such as a clock signal, set signal, and reset signal to force the value of an internal flip-flop into a hold state from an external pin in test mode. Embedded control signal suppression circuit.

(2) A circuit that disables all normal logic tri-state sources and enables test-only tri-state sources to force the value of the internal tri-state bus to a non-high-impedance state from an external pin in test mode. Embedded tri-state bus control circuit, and more.

(3) External pins for test mode setting to individually control these flip-flop control signal suppression circuits and tristate bus control circuits are provided in advance, thereby easily and reliably testing the above-mentioned logic circuits. be able to.

Furthermore, in order to realize the desired state in the test mode for an arbitrary test pattern, the order of test execution is: (a) Setting the logic circuit to the test mode, (b) Applying an arbitrary test pattern, (c) ) Test mode settings.

(d) Tri-state gate test mode setting.

(e) Standby current measurement.

(f) Release of flip-flop test mode.

(g) Release of test mode of tri-state gate.

(h) Repeating the above (b) to (g).

In this type of test execution, the test mode control external pins are independently controlled by the flip-flop control system and the tristate bus system.

The flip-flop control signal suppression circuit provided in the logic circuit operates to suppress the flip-flop control signal in test mode, regardless of the values of the data input terminal and control signal terminal of each flip-flop. . Therefore, the internal state of the flip-flop can be forcibly held during the test mode. Furthermore, the tristate bus control circuit operates in the test mode to enable only the test-dedicated tristate source and disable the other tristate sources.

In addition, the value of the pass line can be forced into a non-high impedance state from an external pin.

The test execution order is to change the value of the tristate bus after holding the flip-flop, and release the hold of the flip-flop after recovering the value of the tristate bus, so the value of the tristate bus,
Flip-flop inputs and stored values do not change before and after test mode. As a result, the order of any test pattern is not disturbed.

Since the test mode control external pin allows the flip-flop control system and the tristate bus control system to be made independent, the test execution procedure can be controlled by the pattern application procedure from the test device. If the external pin for test mode control is shared between the flip-flop control system and the tri-state bus control system, an internal phase control circuit can be used to control the signals for each control system so that they can be used independently. Similarly to the case where a test device is provided, the test execution procedure can be controlled by the pattern application procedure from the test device.

〔Example〕

EMBODIMENT OF THE INVENTION Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In all the figures for explaining the embodiments, the same elements are given the same reference numerals, and repeated explanations thereof will be omitted.

FIG. 1 is a circuit diagram specifically showing the configuration of main parts when testing a logic circuit in which a method for testing a logic circuit according to an embodiment of the present invention is carried out in one aspect. Further, FIG. 2 is a circuit diagram showing the main part configuration of the logic circuit shown in FIG. 1 during non-testing.

Here, the logic circuit that performs the standby current measurement test consists of a combinational logic section 21.degree. flip-flop 222, a combinational logic section 23. Tri-state element 2
4a and 24b2 combinational logic section 25. It is assumed that a logic circuit 20 includes a flip-flop 26 and a flip-flop 26 connected in series.

In order to perform a standby current measurement test on such a logic circuit 20, as shown in FIG. State element 2
A tristate bus control circuit 12 that forcibly puts 4a and 24b in a non-high impedance state and a flip-flop control signal suppression circuit 13 that forcibly puts flip-flop 22 in a hold state are provided.

When performing a standby current measurement test for testing a logic circuit, these circuits (11, 12, 13) force the flip-flops in the logic circuit into a hold state, and the tristate element is used for applying test signals. Force all tri-state elements into a non-high impedance state.

Continuing the explanation of the circuit configurations of the flip-flop control signal suppression circuit and tristate bus control circuit provided in the logic circuit under test with reference to FIG. 1, in FIG.
14 is an external pin for controlling the tri-state bus system, and 17 is an external pin for controlling the flip-flop system. The flip-flop control signal suppression circuit 11 includes AND gates lla,
This circuit suppresses the control signal of the flip-flop 22 by llb and lie in the test mode, and allows the control signal to pass in the non-test mode to enable normal logic operation. Further, the tristate bus control circuit 12 disables the tristate elements 24a and 24b in the test mode using the OR gates 12a and 12b, and enables normal logic operation in the non-test mode. 12c
This circuit sets the test data applied to the input pin 15 to the pass line 16 in the test mode, and disables it in the non-test mode. Further, the flip-flop control signal suppression circuit 13 includes an AND gate 13a
, 13b, and 13c are used to inhibit the control signal of the flip-flop 25 in the test mode to hold the flip-flop 25, and in the non-test mode, the control signal is passed to enable normal logic operation.

FIG. 3 is a diagram showing a time chart of the operation of applying a test pattern to the logic circuit under test.

As shown in FIG. 3, each test cycle is repeated at predetermined intervals. The test pattern signal other than the external pin for testing is at timing 31 in each test cycle.
and changes as necessary at timing 37. Corresponding to the timing of each test cycle, the signal of the external pin for controlling the flip-flop system and the signal of the external pin for controlling the tristate bus system change as shown in FIG.

The test operation of the logic circuit under test will be explained. When a normal test pattern signal is applied at timing 31 at the beginning of test cycle 1, the signal on the flip-flop system control external pin 17 is at H (High) level, and the flip-flops 22, 26 The control signal terminals of C (clock) terminal, S (set) terminal, R (
A signal during normal logic operation reaches each terminal of the (reset) terminal.

Further, at this time, the signal of the tristate bus system control external pin 14 is at L (Low) level.

A normal logic operation signal reaches the enable terminals of tristate elements 24a and 24b. Furthermore, the tristate element 12c is in a disabled state and does not affect the normal logic operation of the pass line 16. After the input stimulus given by the test pattern signal propagates through one circuit and stabilizes, the external pin 1 for controlling the flip-flop system is
When the signal No. 7 is brought to the L level at timing 32, the control signals for flip-flops 22 and 26 are suppressed, and flip-flops 22 and 26 hold the flip-flop setting values at that time. After the hold state of the flip-flop is established, when the signal on the tristate bus control external pin 14 is set to H level at timing 33, the tristate elements 24a and 24b are disabled. Further, the tristate element 12a is enabled, and the level given by the signal from the input pin 15 is set on the pass line 16. At timing 34 after the circuit has become sufficiently stable in response to the input stimulus from the external pin 14 for controlling the tristate bus system, the flip-flops are in the hold state, the tristate bus is in the L or H level stable state, and at this time, the circuit Since the whole is in a static stable state, the standby current measurement requirements are met.Therefore, the standby current is measured at timing 34.Then, at timing 35, the signal on the external pin 14 for tri-state bus system control is set to L level. Then, the pass line 16 is restored to the state before the test mode. When the signal on the external pin 17 for controlling the flip-flop system is set to H level at the subsequent timing 36, the value of the signal at the input terminal of the flip-flop has already been recovered before the test mode at the previous timing 35. , timing 3
At step 6, each flip-flop also returns to its state before the test mode. The same procedure is repeated in test cycle 2, starting from timing 37 by adding a test pattern signal, and thereafter repeating the test cycle as many times as necessary.

In this example, the standby current measurement test is performed for each successive test cycle, but the standby current measurement test may be performed only for a specific test cycle.

Next, another embodiment of the present invention will be described. First, other circuit examples of a flip-flop control circuit and a tristate bus control circuit used in this logic circuit testing method will be explained.

FIG. 4 is a diagram showing another embodiment of the flip-flop control circuit. In the circuit example of FIG. 1, the flip-flop control circuit is a circuit composed of an independent gate group, but as shown in FIG. AND gates 42a, 42b,
42c and the flip-flop 43 are equivalently incorporated into the cell. In this case, since a flip-flop cell to which a gate for controlling the supply of a control signal to the flip-flop is added is used to configure the logic circuit, there is no need to provide a gate for the flip-flop control circuit. Also.

A test gate circuit is incorporated to perform tests using a logic circuit method designed for testability, which can be used as a gate for a similar flip-flop control circuit by using the gate already provided in the peripheral circuit of the flip-flop. In the case of a circuit, such a test gate circuit may be used.

Figures 5a and 5b are diagrams showing other embodiments of the tristate bus control circuit. This example circuit is shown in section 5a.
As shown in the figure, as the tristate element cell 51 of the basic circuit cell constituting the logic circuit, a tristate element 53 and a control OR gate 52 are equivalently incorporated into the cell, and As a tri-state gate for applying a test signal, a cell 54 dedicated to applying a test signal, which is made up of only tri-state elements, is used, as shown in FIG. 5b. This dedicated cell 54 is a cell in which a tri-state element 55 is built-in. When a logic circuit is constructed using these basic circuit cells, a circuit configuration as shown in FIG. 6 is obtained. The logic circuit in FIG. 6 has the same configuration as that in FIG. 1, but the logic circuit in FIG.

This is a circuit constructed using each basic circuit cell shown in FIGS. 5a and 5b. These basic circuit cells incorporate a control circuit at the gate level inside the cell, but by realizing equivalent circuit operation at the transistor level, the logic circuit configuration reduces delay and overhead such as cell area. It is also possible to do this.

FIG. 7 is a phase control circuit showing another embodiment of the test control external pin. In FIG. 7, 71 is an external pin for test control, 72 is a signal terminal to the flip-flop control system, and 73 is a signal terminal to the tristate bus control system. Also,? 4.75°76 are delay values di, d2. It is an AND gate with d3. Using this phase control circuit.

The signal terminal 72 is the external pin 17 for controlling the flip-flop system.
By connecting the signal terminal 73 to the external pin 14 for controlling the tri-state bus system, the number of external signal pins for controlling the test of the logic circuit can be reduced to one.

FIG. 8 is a time chart showing the operation of the phase control circuit related to the external signal pin for test control shown in FIG. 7. As shown in the time chart of FIG. 8, AND gate 74. AND gate 75 and AND gate 76 have delay values di, d2, and d3, respectively, and if a waveform shown in timing signal 77 is applied as an external control signal to external test control pin 71, a timing signal is output to signal terminal 72. 78 is output, and a timing signal 79 is output to the signal terminal 73. The delay values are set so that the rising or falling timings 91, 92, and 93 of each timing signal waveform output from these terminals correspond to, for example, the timings 31, 32, and 33 of the time chart in FIG. By appropriately setting d1 to d3 degrees and the timings 91 and 94, it is possible to configure one external pin for test control.

The present invention has been specifically described above based on examples, but 1.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, when testing a logic circuit, an internal flip-flop can be easily set to a hold state and a tristate bus can be set to a non-high impedance state from an external pin with a small amount of hardware control overhead. , standby current measurements can be made. This allows you to design a dedicated test pattern for standby current measurement, or search for a test pattern that meets the standby current measurement requirements from existing test patterns.
There is no need to test the logic circuit, which has the effect of reducing the cost for testing the logic circuit.

In addition, by performing a logic circuit test using the test execution procedure according to the present invention, it is possible to use an existing test pattern as it is and use it as a standby current measurement pattern, thereby reducing the design cost of the logic circuit test pattern. This has the effect of reducing test pattern file resources, etc. Furthermore, by reusing patterns such as those for DC function tests in existing patterns, it becomes possible to measure standby current for a large number of internal circuit states, improving test pattern test performance and making it easier and more reliable. Can test logic circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram specifically showing the configuration of main parts when testing a logic circuit in which a method for testing a logic circuit according to an embodiment of the present invention is carried out in one aspect. FIG. 2 is a circuit diagram showing the main part configuration of the logic circuit of FIG. 1 during non-testing, and FIG. 3 is a diagram showing a time chart of the operation of applying a test pattern to the logic circuit under test. FIG. 4 is a diagram showing another embodiment of the flip-flop control circuit, FIGS. 5a and 5b are diagrams showing other embodiments of the tristate bus control circuit, and FIG. 6 is a diagram showing another embodiment of the tristate bus control circuit. FIG. 7 is a circuit diagram showing a main part configuration of a logic circuit in another embodiment; FIG. 7 is a circuit diagram of a phase control circuit in another embodiment related to external pins for test control; FIG. 5 is a time chart showing the operation of the phase control circuit related to the external signal pin for test control shown in FIG. In the figure, 11.13... blip prop control circuit,
12... Tri-state bus control circuit, 14... External pin for tri-state bus system control, 17... External pin for flip-flop system control, 20... Logic circuit, 2
1.23... Combinational logic section, 22.26... Flip flop, 24a. 24b... Tri-state element, 41... Freelough prop cell, 51... Tri-state element cell, 5
4... Dedicated cell for applying test signals.

Claims (1)

[Claims] 1. For the logic circuit under test, in the test mode, the flip-flops built in the logic circuit are forcibly put into a hold state, and a group of source gates on the tri-state bus built in the logic circuit are A method for testing a logic circuit, comprising: forcibly disabling all but a test signal application gate, and determining a circuit failure by measuring standby current. 2. A flip-flop control circuit that forcibly puts the flip-flops built into the logic circuit into a hold state in test mode, and a test signal application gate that controls the group of source gates on the tri-state bus built into the logic circuit in test mode. The logic circuit under test is provided with a tri-state bus control circuit that forcibly disables all but the flip-flop control circuit, and the test signal is applied by individually controlling the flip-flop control circuit and the tri-state bus control circuit A method for testing a logic circuit, which comprises providing a period in a test cycle in which the entire circuit is in a static stable state, measuring standby current, and determining a circuit defect. 3. The first step is to apply an arbitrary test pattern to the logic circuit under test, the second step is to force the flip-flops built into the logic circuit into a hold state, and the flip-flops built into the logic circuit are The third step is to forcibly disable all source gates on the state bus except for the test signal application gate, the fourth step is to measure the standby current, and the third step is to forcibly disable all source gates on the state bus except for the test signal application gate. The fifth step of releasing the forced disable state of the source gate group and the sixth step of releasing the forced hold state of the flip-flops built in the logic circuit are sequentially repeated. How to test logic circuits.