JP2004511045A - System and method for enhancing manufacturing test failure analysis with dedicated pins - Google Patents

Abstract

The present invention is a scan test chain intermediate debugging system and method that facilitates simplified debugging of internal component scan test results with minimal impact on normal operation and manufacturing processes. The scan test chain intermediate debugging system and method of the present invention enhances internal scan test analysis on internal scan test chains included in digital circuits and is compatible with scan test methods. One embodiment of the present invention includes a scan test chain intermediate debugging system including a test vector debugging control circuit (eg, a multiplexer), an auxiliary scan test output port, and an intermediate control signal port. The test vector debugging control circuit selectively provides a communication port from a dedicated intermediate scan test chain signal to an auxiliary scan test output port. The intermediate scan test signal is a measurement or logical value obtained from an intermediate point in the scan test chain. The intermediate control signal port provides a communication port for a control signal that indicates to the test vector debugging control circuit which intermediate scan test signal to transmit to the auxiliary scan test output port. The auxiliary scan test output port operates to transmit an intermediate scan test signal off of the IC. By selectively transmitting one of the IC's intermediate scan test chain signals off, the scan test chain intermediate debugging system and method facilitates higher accuracy of test vector results and scan test analysis including debugging indications of faults. Help.

Description

[0001]
(Technical field to which the invention belongs)
The present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to systems and methods that facilitate debugging of internal component scan test failures.
[0002]
(Background of the Invention)
Electronic systems and circuits make a significant contribution to recent social progress and are used in a number of applications to achieve advantageous results. Many electronic technologies, such as digital computers, calculators, audio devices, video devices, and telephone systems, analyze and communicate data, ideas, and trends in most areas of business, science, education, and entertainment. Increased productivity and reduced costs. Often, electronic systems designed to achieve these results include various components or devices, including microelectronic integrated circuits. Generally, the components or devices of an electronic system need to operate properly to achieve a desired result. Effective and reliable integrated circuit (IC) test systems and methods are very important to ensure that ICs operate properly.
[0003]
The complexity of commonly used integrated circuits included in system-on-a-chip (SOC) designs has increased remarkably, and built-in self-test (BIST) diagnostics are critical for effective circuit testing, debugging, and maintenance. is there. Modern BIST technology generally involves the insertion of a scan test architecture into an IC. Scan testing of complex electronic systems and circuits often involves the application of test vectors to facilitate the observation of certain circuit areas (eg, functional logic components) and the output resulting from this circuit. Typically, a scan test architecture includes a scan test chain that includes scan test components or devices (eg, scan test cells) that are coupled together to form a scan test chain. The scan test element communicates test vectors to the components of the IC and interacts with functional logic used to perform non-test or normal operation of the IC. Generally, a scan test chain scans or shifts scan test information (eg, a test vector) for an appropriate location in a circuit through the scan test chain, obtains the scan test information, and then scans the IC. Designed to shift off information.
[0004]
It is usually desirable to have significant scan test coverage, and generally the greater the coverage, the greater the performance of scan test systems and methods for detecting failures. Boundary scan testing is a very commonly known method of scan testing that is included in a typical BIST scheme. The International Electro-Electronics (IEEE) Standard 1149.1 (also referred to as the Joint Task Action Group (JTAG)) boundary scan compliant architecture is one of the most widely used boundary scan schemes. It is also very important to have an internal scan function that gives greater scan test coverage. Having both internal scan and boundary scan capabilities often requires significant involvement of limited IC resources, such as increasing the dedicated use of fewer IC pins for scan test operations.
[0005]
Debugging scan test results often require complex analysis of logic values derived from appropriately selected circuit nodes (eg, functional logic outputs or inputs) after application of test vectors. Conventional long scan test vectors provided by automatic test pattern generation (ATPG) tools make scan test debugging very difficult. Test patterns provided by the ATPG tool often appear to engineers as random data that is shifted into the chip. Typically, engineers do not have a thorough understanding of each scan test pattern generated by the ATPG tool. A common way to try to solve a scan test debug problem is to push some sort of predetermined pattern into the scan test input and see what is causing the problem based on how the scan test output behaves or changes. Including trying to infer. However, it is difficult to accurately identify normal faults without a thorough understanding of test vector patterns.
[0006]
Scan test patterns are generally very long (thousands of scan elements are common scan test chain lengths), and it is inherently difficult to debug a fault or fault indication. It is relatively easy to analyze the operation of a limited number of circuit elements in response to a test vector, and it is relatively accurate to make inferences to identify elements that cause a failure problem. Each element added to the scan test chain becomes another element that is a potential source of failure. Accurately inferring which device is the source of the failure becomes increasingly more difficult due to the many possible sources of problems and increases the number of scan test devices.
[0007]
Conventional methods that attempt to solve the difficulties of scan test debugging consume considerable resources and often lack reliability. For example, the use of a small scan test chain with a shorter test vector will generally significantly increase the need to dedicate less pin resources to scan test operations. Although a small scan test chain can provide some advantages, it does not provide the flexibility to test many parts of the system, and only a small part is tested at any given time, so that Makes it difficult to test the operation of the system. Thus, attempts to identify the source of failure in conventional scan test operations are often inaccurate and unreliable.
[0008]
What is needed is a system and method that facilitates easy debugging of internal component scan test results. The system and method should support effective scan testing of integrated circuit components and embrace the use of existing scan test architectures with minimal adverse redesign impact on existing IC designs.
[0009]
(Summary of the Invention)
The present invention is a system and method that facilitates simple debugging of internal component scan test results with minimal impact on normal operation and manufacturing processes. The scan test chain intermediate debugging system and method of the present invention enables an effective scan test of an integrated circuit component with an ATPG tool and assists a debugging operation. The systems and methods of the present invention embrace the use of existing test scan architectures with minimal impact of adverse redesign on existing IC designs. The present invention enhances the internal scan test analysis of digital circuits and is compatible with scan test methods.
[0010]
One embodiment of the present invention includes a scan test chain intermediate debugging system that includes a test vector debugging control circuit (eg, a multiplexer), an auxiliary scan test output port, and an intermediate control signal port. The test vector debugging control circuit selectively provides a communication path from the designated intermediate scan test chain signal to the auxiliary scan test output port. The intermediate scan test signal is a measurement or logical value obtained from an intermediate point in the scan test chain. The intermediate control signal port provides a communication port for a control signal that controls a test vector debugging control circuit that outputs an intermediate scan test signal for transmission to an auxiliary scan test output port. The auxiliary scan test output port operates to transmit an intermediate scan test signal off of the IC. In one embodiment of the present invention, the intermediate scan test signal is accessible to the ATPG tool via a scan test chain intermediate debugging system.
[0011]
(Embodiment of the invention)
Reference will now be made in detail to a preferred embodiment of the invention, a scan test intermediate debugging system and method, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that the preferred embodiments are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover the alterations, modifications, and equivalents, which may be included within the scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
[0012]
One embodiment of the present invention includes a scan test chain intermediate debugging system and method. In one embodiment of the present invention, the scan test chain intermediate debugging system is included in the scan test chain and is compatible with normal scan test methods. The scan test chain intermediate debugging system is included in the design at various locations during the early stages of the manufacturing process of one embodiment of the present invention and is coupled to the intermediate scan test signal. In one exemplary implementation of the invention, the scan test chain intermediate debugging system is configured to be compatible with a scan test architecture that is open to the ATPG tool and that is easily accessible by the ATPG tool. The scan test chain intermediate debugging system of the present invention facilitates debugging of scan test failure indications by helping to analyze the middle portion of the scan test chain.
[0013]
FIG. 1 is a block diagram of a scan test chain intermediate debugging system 100 according to an embodiment of the present invention. The scan test chain intermediate debugging system 100 includes a test vector debugging control circuit 110, an auxiliary scan test output port 120, and an intermediate control signal port 130. Test vector debugging control circuit 110 is coupled to auxiliary scan test output port 120 and intermediate select control signal port 130. In one embodiment of the present invention, scan test chain intermediate debugging system 100 is included in an IC to efficiently provide data related to intermediate scan test chain signals with minimal impact on the design process and minimal design rework. I do.
[0014]
Components of the scan test chain intermediate debugging system 100 cooperate to facilitate debugging of faults by extracting intermediate scan test chain signals. The test vector debugging control circuit 110 transmits the designated intermediate scan test chain signal to the auxiliary scan test output port 120. Auxiliary scan test output port 120 provides a communication port for communicating the intermediate scan test chain signal off of the IC. The intermediate control signal port 130 provides a communication port for communicating control signals that control which intermediate scan chain signals are transferred by the test vector debugging control circuit 110 to the auxiliary scan test output port 120.
[0015]
In one embodiment of the present invention, test vector debugging control circuit 110 receives a plurality of intermediate scan test chain signals, including intermediate scan test chain signal 141 and intermediate scan test chain signal 142. In one exemplary embodiment, intermediate scan test chain signals 141 and 142 are measurements (eg, logical values) from intermediate scan test chain elements. The test vector debugging control circuit 110 selectively transmits one of the scan test chain intermediate measurement signals to an auxiliary scan test output port 120 for transmitting an IC off. By selectively transmitting one of the IC's intermediate scan test chain signals off, the scan test chain intermediate debugging system 100 facilitates higher accuracy of the test vector results and performs scan test analysis including fault debugging indications. help.
[0016]
FIG. 2 is a block diagram of a scan test chain intermediate debugging system 200 according to an embodiment of the present invention. The scan test intermediate debugging system 200 includes a multiplexer circuit (MUX) 215, an auxiliary intermediate scan test signal output port 217, an intermediate control signal port 219, design circuit blocks 231 to 233, a scan test input pin 221 and a scan test. Output pin 225. The design circuit blocks 231 to 233 include scan test elements. The MUX 215 is coupled to the auxiliary intermediate scan test signal output port 217, the intermediate control signal port 219, and the design circuit blocks 231 to 233. Design circuit block 231 is coupled to scan input pin 221 and design circuit block 232. Design circuit block 233 is coupled to scan output pin 225 and design circuit block 232.
[0017]
The components of the scan test chain intermediate debugging system 200 cooperate to perform functional operations and facilitate fault debugging by extracting the intermediate scan test chain signal off of the IC. The MUX 215 transmits the designated intermediate scan test chain signal to the auxiliary intermediate scan test signal output port 217, which is a communication port for communicating the intermediate scan test signal off of the IC. The intermediate control signal port 219 is a communication port for communicating an intermediate control signal on the IC. This intermediate control signal indicates which intermediate scan test chain signal is transferred to the auxiliary intermediate scan test signal output port 219. The design circuit blocks 231 to 233 execute designated functions during the normal operation mode of the IC. The scan test elements of the design circuit blocks 231 to 233 shift in the scan test vector, acquire the resulting scan test information, and shift out the scan test result during the scan test operation. Scan test input pin 221 provides a communication port for scan test input information, and scan output pin 225 provides a communication port for scan test output information.
[0018]
Scan test chain intermediate debugging system 200 facilitates higher accuracy of test vector results and aids in scan test analysis, including fault debugging indications. By selectively transmitting the intermediate scan test signal 271 OFF of the IC, the operation of the scan test vector value input of the scan test input port 221 by the design circuit block 231 is changed from the operation of the test vector value by the design circuit blocks 232 and 233. Separated in analytical sense. If the intermediate scan test signal 271 is an unexpected value, this signal indicates that a fault may be in the design circuit block 231. Isolating the fault in the design circuit block 231 facilitates debugging without having to consider the manipulation of test vector values by the design circuit blocks 232 and 233. The scan test results from the intermediate position will be located at some potential fault locations in the scan test chain as long as the scan test results for the entire chain from scan test input pin 221 to scan test output pin 225 are still enabled. Effectively reduce the number of certain components (eg, design circuit blocks).
[0019]
Similarly, the operations by the design circuit blocks 232 and 233 on the scan test vector values are separated by extracting the test vector values of the design circuit blocks 232 and 233. The test vector value inputs of design circuit blocks 232 and 233 (which are also outputs of circuit block 232) are extracted by MUX 215 according to an intermediate control signal communicated via intermediate control signal port 219. For example, it is extracted that the intermediate scan test signal 271 of the IC information related to the logic value input of the design circuit block 232 is selectively transmitted, and the intermediate scan of the IC information related to the logic value output from the design circuit block 232 is extracted. The selective transmission of the test signal 272 off is extracted. If the expected logic value is not output from the design circuit block 232 after confirming the input to the design circuit block 232, this value is an indication that the design circuit block 232 has a fault. Thus, the present invention facilitates simple debugging of internal scan test results by checking the scan test vector input of the design circuit block and extracting the intermediate scan test signal output of the design circuit block.
[0020]
FIG. 3 is a block diagram of a design block 300 that is one embodiment of a design block (eg, design block 232) included in one implementation of the invention. The design block 300 includes a full scan cell (FSC) 397, an FSC 399, and a functional circuit 340. The output of FSC 397 is connected to a functional circuit 340 that is coupled to the input of FSC 399. All scan cells 397 include an enable MUX 391 and a scan D flip-flop (FF) 393. Enable MUX 391 is coupled to regular data-in signal 310, intermediate scan test signal 181, scan serial input signal 330, scan enable signal 320, and scan DFF 393. Scan DFF 393 is also coupled to clock signal 350, scan serial signal 360, and FSC 399. All scan cells 399 include an enable MUX 394 and a scan D flip-flop (DFF) 395. Enable MUX 394 is coupled to functional circuit 340, scan serial signal 360, scan enable signal 320, and scan DFF 395. Scan DFF 395 is also coupled to clock signal 350, regular data out signal 370, intermediate scan test signal 182, and scan serial output signal 380.
[0021]
The design block 300 facilitates testing of the functional circuit 340 during a scan test operation. The enable MUX 391 selects the regular data-in signal 310 or the serial data input signal 330 to be transmitted to the scan DFF 393 according to the logic state of the scan enable signal 320. When scan enable signal 320 is active, data is serially shifted in and out of DFFs 393 and 394. The scan DFF 393 latches the signal from the enable MUX 391 and transmits this signal to the functional circuit 340 and to the DFF 394 as a scan serial signal 360 according to the cycle of the clock signal 350. Thus, data is provided to the functional circuit 340 via the DFF 393 from the regular data-in signal 310 if the scan enable signal 320 is inactive, or from the serial input signal 330 if the scan enable signal 320 is active. . After the functional circuit 340 has been activated with the desired test data, the scan enable signal 320 is deactivated to obtain the output of the functional circuit 340. By deactivating the scan enable signal 320, the MUX 394 does not transfer the serial signal 360 from the scan DFF 395, but instead transfers the output of the functional circuit 340 to the scan DFF 395. After the output of the functional circuit 340 has been transferred to the scan DFF 395, this output can be either a regular output signal 370 through a normal operating output pin or a serial output via another FSC (eg, the FSC included in the design block 273). Output as either signal 380 or intermediate scan test signal 272.
[0022]
Referring again to FIG. 2, MUX 215 receives a plurality of intermediate scan test chain signals including an intermediate scan test chain signal 271 and an intermediate scan test chain signal 272 during a scan test mode operation. In one exemplary embodiment, intermediate scan test chain signals 271 and 272 are measurements (eg, logical values) from the inputs of functional logic 340 and the outputs of functional logic 340. The MUX 215 selectively transmits one of the scan test chain intermediate scan test signals to an auxiliary intermediate scan test signal port 217 for transmitting an IC off. In one exemplary implementation of the invention, MUX 215 selects an intermediate scan test chain signal 271 to transmit a chip off. If the scan test chain signal 271 matches the expected value of the test vector shifted to the FSC 397, there is a high probability that the test vector value is an input to the functional circuit 340 during the next acquisition cycle. After the next acquisition cycle, MUX 215 selects intermediate scan test chain signal 272 to transmit chip off. If the intermediate scan test chain signal 272 does not match the expected value for the output of the functional circuit 340 based on the input test vector value, the failure of the functional circuit 340 has a high probability.
[0023]
FIG. 4 is a flowchart of a scan test intermediate debugging method 400 according to an embodiment of the present invention. The scan test chain debugging method 400 facilitates debugging scan test failure indications in an IC. In one embodiment of the present invention, the scan test chain intermediate debugging method 400 increases scan test accuracy and simplifies scan test result analysis.
[0024]
At step 410, an intermediate scan test signal is received from a scan test chain. In one embodiment of the scan test chain intermediate debugging method 400, an intermediate scan test signal is received during an acquisition mode of the scan test system and is performed by deactivating a scan test enable signal and activating a clock pulse. . In one embodiment of the invention, the intermediate scan test signal is a signal received from the output of the functional logic component included in the IC after the functional logic component has performed the specified operation. In one exemplary embodiment of the scan test chain intermediate debugging method 400, the functional logic components are shifted into the scan chain and based on scan input information (eg, test vectors) presented at the input of the functional component. Perform the specified action.
[0025]
In step 420, the intermediate scan test signal is selected to transmit an IC off according to the command received from the dedicated intermediate control signal port. In one embodiment of the present invention, the switching circuit is operated to combine with an intermediate scan test signal to transmit the off of the IC. In one example of step 420, the multiplexer is used to provide a communication path from one of its inputs to its output based on control values sent from the dedicated control signal port to the multiplexer. In one embodiment, the multiplexer Os input is coupled to the output of the internal design circuit block. The control values that determine the selection of the intermediate scan test signal are cycled through in one embodiment of the present application to sequentially obtain information associated with each intermediate scan test signal.
[0026]
In step 430, the intermediate scan test signal is transmitted to the IC off via the dedicated auxiliary intermediate scan test signal output port. In one embodiment of the present invention, the intermediate scan test signal is used to facilitate debugging of a scan test failure indication. In one exemplary embodiment, the intermediate scan test signal is derived from the inputs and outputs of the functional logic block if the functional logic block is faulty. The test vector value input of the functional logic block is verified by selecting a scan test intermediate signal at the input of the functional logic block, and the intermediate scan test signal value derived by the scan test chain intermediate debugging method 400 at the output of the functional logic block. If does not match the expected value for a properly functioning logic circuit, the functional logic block is not operating properly and there is an indication that there is a fault.
[0027]
Accordingly, the present invention is a system and method that facilitates desirable scan testing of internal components with minimal impact on normal operation and manufacturing processes. The present invention facilitates simplification (eg, higher accuracy) of debugging analysis and supports increased fault identification accuracy. It is possible to select an intermediate internal scan test chain signal for transmitting an IC off, as long as the scan test results for the entire chain are still enabled via the scan test chain final output pin (not shown). Facilitates isolation and analysis of potential scan test failures. The scan test chain intermediate debugging system and method of the present invention embraces the use of existing test scan architectures and minimizes the redesign of the adverse effects of existing IC designs.
[0028]
The foregoing description of a specific embodiment of the invention has been presented for purposes of illustration and description. This embodiment is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. This embodiment has been chosen and described in order to best explain the principles of the invention and its practical applications, so that those skilled in the art will recognize the invention and its various modifications with various modifications suitable for the particular use contemplated. The embodiments can be best utilized. It is intended that the scope of the invention be defined by the following claims and their equivalents:
[Brief description of the drawings]
FIG.
1 is a block diagram of a scan test chain intermediate debugging system according to an embodiment of the present invention.
FIG. 2
FIG. 9 is a block diagram of another embodiment of the scan test chain intermediate debugging system of the present invention.
FIG. 3
FIG. 3 is a block diagram of an all-scan cell, which is one embodiment of a design block included in the implementation of the present invention.
FIG. 4
4 is a flowchart of a scan test chain intermediate debugging method according to an embodiment of the present invention.
[Explanation of symbols]
110 Test Vector Debugging Control Circuit 120 Auxiliary Scan Test Output Port 130 Intermediate Control Signal Port 141 Intermediate Scan Test Signal 142 Intermediate Scan Test Signal 200 Scan Test Chain Intermediate Debugging System 221 Scan Input Pin 225 Scan Output Pin

Claims (17)

A scan test chain intermediate debugging system included in an integrated circuit,
A test vector debugging control circuit configured to select an intermediate scan test chain signal for transmission;
An auxiliary intermediate scan test signal output port coupled to the test vector debugging control circuit and configured to provide a communication port for an intermediate scan test chain signal;
An intermediate control signal port coupled to the test vector debugging control circuit and configured to provide a communication port for a control signal instructing the debugging control circuit. Bagging system. Further comprising a plurality of circuit blocks including scan test elements, wherein the plurality of circuit blocks are sequentially coupled to form a scan test chain and shift test data obtained along the scan test chain. The scan test chain intermediate debugging system according to claim 1, wherein the system is configured. A scan test input port coupled to a first circuit block of the plurality of circuit blocks, wherein the scan test input port communicates for scan test data to the first circuit block of the plurality of circuit blocks; 3. The scan test chain intermediate debugging system of claim 2, wherein the system is configured to provide a port. 3. The scan test chain intermediate debugging system of claim 2, further comprising a scan test output port coupled to a circuit block at an end of the plurality of circuit blocks and configured to send a scan test data out. . 2. The scan test chain intermediate debugging system according to claim 1, wherein the test vector debugging control circuit includes a multiplexer. 6. The scan test chain intermediate debugging system according to claim 5, wherein the input to the multiplexer includes a plurality of intermediate scan test signals obtained from intermediate nodes of the scan test chain. The multiplexer is controlled by the control signal received through the intermediate control signal port, wherein the control signal is one of the plurality of scan test signals obtained from the intermediate node of the scan test chain and the auxiliary intermediate scan test signal 7. The scan test chain intermediate debugging system of claim 6, indicating that the signal is sent by the multiplexer on an output port. A scan test chain intermediate debugging system,
An auxiliary intermediate scan test signal output port configured to provide a communication port for communicating an intermediate scan test signal off of the IC;
A multiplexer coupled to the auxiliary intermediate scan test signal output port and configured to transmit a designated intermediate scan test chain signal to the auxiliary intermediate scan test signal output port;
Intermediate control coupled to the multiplexer and configured to provide a communication port for communicating control signals on the IC to indicate the intermediate scan test chain signal for transfer to the auxiliary intermediate scan test signal output port. A signal port,
A plurality of design circuit blocks coupled to the multiplexer and configured to perform designated functions during a normal mode of operation of the IC;
A scan test input pin coupled to one of the plurality of design circuit blocks and configured to provide a communication port for scan test input information;
A scan test output pin coupled to one of the plurality of design circuit blocks and configured to provide a communication port for scan test output information. 9. The scan test chain intermediate debugging system according to claim 8, wherein the input to the multiplexer includes a plurality of intermediate scan test signals obtained from intermediate nodes of the scan test chain. The multiplexer is controlled by the control signal received through the intermediate control signal port, wherein the control signal is one of the plurality of scan test signals obtained from the intermediate node of the scan test chain and the auxiliary intermediate scan test signal 10. The scan test chain intermediate debugging system according to claim 9, indicating whether it is sent by the multiplexer on an output port. A scan test chain intermediate debugging method,
Receiving an intermediate scan test signal from the scan test chain;
Selecting said intermediate scan test signal for transmitting an IC off according to a command received from a dedicated intermediate control signal port;
Transmitting the intermediate scan test signal off of the IC via a dedicated auxiliary intermediate scan test signal output port. The scan chain intermediate debugging method according to claim 11, wherein the intermediate scan test signal is a signal received from an output of a function logic component included in an IC. The step of selecting a scan test signal to transmit the off of the IC includes the step of operating a switching circuit to combine with an intermediate scan test signal to transmit the off of the IC. The scan test chain intermediate debugging method according to claim 11. The step of selecting scan test information for transmitting an off of the IC comprises the step of: establishing a communication path from one of a plurality of inputs to the multiplexer based on a control value transmitted from a dedicated control signal port to the multiplexer. The method of claim 11, including using the multiplexer to provide the output of the multiplexer. One of the plurality of inputs to the multiplexer is coupled to an output of an internal design circuit block, and one of the plurality of inputs to the multiplexer is a test data input to the internal design circuit block of the scan test chain. The method of claim 14, wherein the method is coupled to a signal. The method of claim 11, further comprising using the intermediate scan test signal to facilitate debugging of a scan test failure indication. 12. The scan test chain intermediate debugging method according to claim 11, further comprising circulating a control value for determining selection of an intermediate scan test signal for sequentially obtaining information related to each intermediate scan test signal.

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