WO2002029569A2

WO2002029569A2 - A system and method to enhance manufacturing test failure analysis with dedicated pins

Info

Publication number: WO2002029569A2
Application number: PCT/EP2001/011402
Authority: WO
Inventors: Kenneth Jaramillo; Varaprasda Vajjhala
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2000-10-02
Filing date: 2001-10-02
Publication date: 2002-04-11
Also published as: EP1370940A2; JP2004511045A; WO2002029569A3

Abstract

The present invention is a scan test chain intermediate debugging system and method that facilitates simplified debugging of internal component scan test results with minimal impacts to normal operations and manufacturing processes. The scan test chain intermediate debugging system and method of the present invention enhances internal scan test analysis on internal scan test chains included in digital circuits and is compatible with scan test methodologies. One embodiment of the present invention includes a scan test chain intermediate debugging system including a test vector debugging control circuit (e.g., a multiplexer), a supplemental scan test output port and an intermediate control signal port. The test vector debugging control circuit selectively provides a communication path from an indicated intermediate scan test chain signal to the supplemental scan test output port. The intermediate scan test signal is a measurement or logical value captured from an intermediate point in the scan test chain. The intermediate control signal port provides a communication path for a control signal that directs the test vector debugging control circuit which intermediate scan test signal to transmit to the supplemental scan test output port. The supplemental scan test output port operates to transmit intermediate scan test signals off of the IC. By selectively transmitting one of the intermediate scan test chain signals off of the IC, the scan test chain intermediate debugging system and method facilitates greater granularity of test vector results and assists scan test analysis including debugging indications of faults.

Description

A system and method to enhance manufacturing test failure analysis with dedicated pins

FIELD OF THE INVENTION

The present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to a system and method that facilitates debugging of internal component scan test faults.

BACKGROUND OF THE INVENTION

Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results comprise a variety of components or devices including microelectronic integrated circuits. Usually the components or devices of an electronic system are required to operate properly in order for the desired results to be realized. An efficient and reliable integrated circuit (IC) testing system and method is very important for assuring an IC operates properly.

The complexity of commonly used integrated circuits included in system-on- chip (SOC) designs has advanced dramatically and built in self test (BIST) diagnostics capability is essential for effective circuit testing, debugging, and maintenance. Modern BIST techniques typically include the insertion of a scan test architecture in an IC. Scan testing of complex electronic systems and circuits often includes the application of test vectors to stimulate certain aspects of a circuit (e.g., a functional logic component) and observation of the resulting output from the circuit. Usually, scan test architectures include scan test chains comprising scan test components or devices (e.g., scan test cells) coupled together. The scan test elements communicate test vectors to components of an IC and interact with functional logic utilized to perform non-test or normal operations of the IC. Typically, scan test chains are designed to scan or shift scan test information (e.g., test vectors) to appropriate locations in a circuit via the scan test chain, capture scan test information and then shift the information out via scan test cells of the scan test chain.

Usually it is desirable to have significant scan test coverage, typically the greater the test coverage the greater the capacity of a scan test system and method to detect faults. Boundary scan testing is a very common method of scan testing included in typical BIST schemes. International Electrical and Electronic Engineering (IEEE) Standard 1149.1 (also referred to as Joint Task Action Group (JTAG)) boundary scan compliant architecture is one of the most prevalent boundary scan schemes. It is also very important to have internal scan test capabilities to provide greater scan test coverage. Having both internal and boundary scan capability often requires significant commitment of limited IC resources, such as increased dedication of scarce IC pins to scan test operations.

Debugging scan test results often requires complicated analysis of logic values from appropriately selected circuit nodes (e.g., at the outputs or inputs of functional logic) retrieved after the application of test vectors. Traditional long scan test vectors provided by automated test pattern generation (ATPG) tools make scan test debugging very difficult. Test patterns provided by an ATPG tool often appear to an engineer as random data shifted into the chip. Usually the engineers do not have an in-depth understanding of each scan test patterns generated by ATPG tools. Common methods of attempting to solve scan test debug difficulties include forcing certain predetermined patterns into a scan test input and attempting to infer what is causing the problem based upon how a scan test output behaves or changes. However, without a good understanding of the test vector pattern it is usually difficult to accurately identify a fault.

Scan test patterns are typically very long (scan test chains lengths of thousands of scan elements are common) and it is inherently difficult to debug failures or fault indications. Analyzing the behavior of limited number of circuit elements in response to a test vector is relatively easy and making an inference identifying the element causing a fault problem is relatively accurate. However, each element added to a scan test chain results in another element that is a potential source of a fault. Accurately inferring which element is the source of the fault becomes increasingly more difficult the greater the number of scan test elements since there are more possible sources of a problem.

Traditional methods of attempting to solve scan test debug difficulties usually consume significant resources and often lack a high degree of reliability. For example, utilizing small scan test chains with shorter test vectors typically results in significantly increasing the requirement for dedication of scarce pin resources to scan test operations. While small scan test chains may offer some advantages, they do not offer the flexibility of testing large sections of a system and make it difficult to test the operations of an entire system since only a small portion is tested at any given time. Thus, attempts to identify sources of faults in traditional scan test operations is often inaccurate and unreliable. What is required is a system and method that facilitates simplified debugging of internal component scan test results. The system and method should support efficient scan test of integrated circuit components and accommodate utilization of existing testing scan architectures with minimal adverse redesign impacts to existing IC designs.

SUMMARY OF THE INVENTION

The present invention is a system and method that facilitates simplified debugging of internal component scan test results with minimal impacts to normal operations and manufacturing processes. The scan test chain intermediate debugging system and method of the present invention is capable of supporting efficient scan testing of integrated circuit components with an ATPG tool and assists debugging operations. The present invention system and method accommodates utilization of existing testing scan architectures with minimal adverse redesign impacts to existing IC designs. The present invention enhances internal scan test analysis in digital circuits and is compatible with scan test methodologies. One embodiment of the present invention includes a scan test chain intermediate debugging system comprising a test vector debugging control circuit (e.g., a multiplexer), a supplemental scan test output port and an intermediate control signal port. The test vector debugging control circuit selectively provides a communication path from an indicated intermediate scan test chain signal to the supplemental scan test output port. The intermediate scan test signal is a measurement or logical value captured from an intermediate point in the scan test chain. The intermediate control signal port provides a communication path for a control signal that directs the test vector debugging control circuit which intermediate scan test signal to transmit to the supplemental scan test output port. The supplemental scan test output port operates to transmit intermediate scan test signals off of the IC. In one embodiment of the present invention, the intermediate scan test signals are assessable to an ATPG tool via the scan test chain intermediate debugging system. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram of a scan test chain intermediate debugging system, one embodiment of the present invention.

Figure 2 is a block diagram of another embodiment of a scan test chain intermediate debugging system of the present invention.

Figure 3 is a block diagram of a full scan cell, one embodiment of a design block included in an implementation of the present invention.

Figure 4 is a flow chart of a scan test chain intermediate debugging method, one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the preferred embodiments of the invention, a scan test intermediate debugging system and method, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one ordinarily skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the current invention. One embodiment of the present invention includes a scan test chain intermediate debugging system and method. In one embodiment of the present invention, a scan test chain intermediate debugging system is included in a scan test chain and is compatible with normal scan testing methodologies. Scan test chain intermediate debugging systems are included in a design at various locations during the initial stages of a manufacturing process in one embodiment of the present invention and coupled to intermediate scan test signals. In one exemplary implementation of the present invention, the scan test chain intermediate debugging system is configured in a manner that is compatible with a scan test architecture familiar to the ATPG tool and easily accessible by the ATPG tool. The scan test chain intermediate debugging system of the present invention facilitates debugging of scan test fault indications by assisting analysis of intermediate sections of a scan test chain.

Figure 1 is a block diagram of scan test chain intermediate debugging system 100, one embodiment of the present invention. Scan test chain intermediate debugging system 100 comprises test vector debugging control circuit 110, supplemental scan test output port 120 and intermediate control signal port 130. Test vector debugging control circuit 110 is coupled to supplemental scan test output port 120 and intermediate selection control signal port 130. In one embodiment of the present invention, scan test chain intermediate debugging system 100 is included in an IC and efficiently provides data associated with intermediate scan test chain signals with minimal impacts to design processes and minimal design rework.

The components of scan test chain intermediate debugging system 100 cooperatively operate to facilitate debugging of faults through extraction of intermediate scan test chain signals. Test vector debugging control circuit 110 transmits an indicated intermediate scan test chain signal to supplemental scan test output port 120. Supplemental scan test output port 120 provides a communications port for communicating an intermediate scan test chain signal off of the IC. Intermediate control signal port 130 provides a communications port for communicating a control signal that directs which intermediate scan test chain signal is forwarded by the test vector debugging control circuit 110 to supplemental scan test output port 120.

In one embodiment of the present invention, test vector debugging control circuit 110 receives a plurality of intermediate scan test chain signals including intermediate scan test chain signal 141 and intermediate scan test chain signal 142. In one exemplary embodiment, intermediate scan test chain signals 141 and 142 are measurements (e.g., logical values) from intermediate scan test chain elements. Test vector debugging control circuit 110 selectively transmits one of the scan test chain intermediate measurement signals to supplemental scan test output port 120 for transmission off of the IC. By selectively transmitting one of the intermediate scan test chain signals off of the IC, scan test chain intermediate debugging system 100 facilitates greater granularity of test vector results and assists scan test analysis including debugging indications of faults.

Figure 2 is a block diagram of scan test chain intermediate debugging system 200, one embodiment of the present invention. Scan test chain intermediate debugging system 200 comprises a multiplexer circuit (MUX) 215, supplemental intermediate scan test signal output port 217, intermediate control signal port 219, design circuit blocks 231 through 233, scan test input pin 221, and scan test output pin 225. Design circuit blocks 231 through 233 include scan test elements. MUX 215 is coupled to supplemental intermediate scan test signal output port 217, intermediate control signal port 219 and design circuit blocks 231 through 233. Design circuit blocks 231 is coupled to scan input pin 221 and design circuit block 232. Design circuit block 233 is coupled to scan output pin 225 and design circuit block 232.

The components of scan test chain intermediate debugging system 200 cooperatively operate to provide functional operations and facilitate debugging of faults through extraction of intermediate scan test chain signals off of the IC. MUX 215 transmits an indicated intermediate scan test chain signal to supplemental intermediate scan test signal output port 217 which is a communications port for communicating the intermediate scan test signal off of the IC. Intermediate control signal port 219 is a communications port for communicating an intermediate control signal onto the IC. The intermediate control signal indicates which intermediate scan test chain signal to forward to supplemental intermediate scan test signal output port 219. Design circuit blocks 231 through 233 perform designated functions during normal operation mode of the IC. The scan test elements of design circuit blocks 231 through 233 shift in scan test vectors, capture resulting scan test information and shift out the scan test results during scan test operations. Scan test input pin 221 provides a communication port for scan test input information and scan test output pin 225 provides a communication port for scan test output information.

Scan test chain intermediate debugging system 200 facilitates greater granularity of test vector results and assists scan test analysis including debugging indications of faults. By selectively transmitting intermediate scan test signal 271 off of the IC, manipulation by design circuit block 231 of a scan test vector value input on scan test input port 221 is isolated in an analytical sense from manipulations of the test vector value by design circuit blocks 232 and 233. If intermediate scan test signal 271 is an unexpected value it provides an indication that a fault may exist in design circuit block 231. Isolating the fault to design circuit block 231 facilitates debugging without having to consider the manipulation of test vector values by design circuit blocks 232 and 233. Scan test results from intermediate locations effectively reduce the number of components (e.g., a design circuit block) that are locations of a potential fault in a portion of the scan test chain while still permitting a scan test result for the entire chain from scan test input pin 221 to scan test output pin 225. Similarly, manipulations by design circuit blocks 232 and 233 on a scan test vector value are isolated by extracting test vector values input and outputs of design circuit blocks 232 and 233. Test vector values input to design circuit blocks 232 and 233 (which is also the output of circuit block 232) are extracted by MUX 215 in accordance with an intermediate control signal communicated via intermediate control signal port 219. For example, selectively transmitting intermediate scan test signal 271 off of the IC information associated with the logical value input to design circuit block 232 is extracted and by selectively transmitting intermediate scan test signal 272 off of the IC information associated with the logical value output from design circuit block 232 is extracted. If an expected logical value is not output from design circuit block 232 after confirming the input to design circuit block 232, it is an indication design circuit block 232 has a fault. Thus, the present invention facilitates simplified debugging of internal scan test results by checking scan test vector inputs to a design circuit block and retrieving an intermediate scan test signal output of the design circuit block. Figure 3 is a block diagram of design block 300, one embodiment of a design block (e.g., design block 232) included in one implementation of the present invention. Design block 300 comprises full scan cell (FSC) 397, FSC 399 and functional circuit 340. The output of FSC 397 is coupled to functional circuit 340 which is coupled to the input of FSC 399. Full scan cell 397 comprises enable MUX 391 and scan D flip flop (FF) 393. Enable MUX 391 is coupled to normal data in signal 310, intermediate scan test signal 271, scan serial input signal 330, scan enable signal 320, and scan DFF 393. Scan DFF 393 is also coupled to clock signal 350, scan serial signal 360 and FSC 399. Full scan cell 399 comprises enable MUX 394 and scan D flip flop (DFF) 395. Enable MUX 394 is coupled to functional circuit 340, scan serial signal 360, scan enable signal 320, and scan DFF 395. Scan DFF 395 is also coupled to clock signal 350, normal data out signal 370, intermediate scan test signal 272, and scan serial output signal 380.

Design block 300 facilitates testing of functional circuit 340 during scan test operations. Enable MUX 391 selects normal data in signal 310 or serial data input signal 330 for transmission to scan DFF 393 depending upon the logical state of scan enable signal 320. When scan enable signal 320 is active data is serially shifted into and out of DFF 393 and 394. Scan DFF 393 latches the signal from enable MUX 391 and transmits the signal to functional circuit 340 and scan serial signal 360 to MUX 394 based upon cycles in clock signal 350. Thus, data is provided to functional circuit 340 via DFF 393 from normal data in signal 310 if scan enable signal 320 is not active or serial input signal 330 if scan enable signal 320 is active. To capture the output of functional circuit 340 after it has acted upon the desired test data, scan enable signal 320 is deasserted. By deasserting scan enable signal 320, MUX 394 does not forward the serial signal 360 from scan DFF 395, instead MUX 394 forwards the output of functional circuit 340 to scan DFF 395. After the output of functional circuit 340 is transferred to Scan DFF 395 it is output either as normal output 370 signal through a normal operation output pins or serial output signal 380 via other FSCs (e.g., FSCs included in design block 273) or as intermediate scan test signal 272.

Referring again to Figure 2, MUX 215 receives a plurality of intermediate scan test chain signals including intermediate scan test chain signal 271 and intermediate scan test chain signal 272 during scan test mode operations. In one exemplary embodiment, intermediate scan test chain signals 271 and 272 are measurements (e.g., logical values) from the input to functional logic 340 and the output of functional logic 340. MUX 215 selectively transmits one of the scan test chain intermediate scan test signals to supplemental intermediate scan test signal output port 217 for transmission off of the IC. In one exemplary implementation of the present invention, MUX 215 selects intermediate scan test chain signal 271 for transmission off of the chip. If scan test chain signal 271 matches the expected value of a test vector shifted into FSC 397, then there is a high degree of probability that during the next capture cycle the test vector value will be input to functional circuit 340. After the next capture cycle, MUX 215 selects intermediate scan test chain signal 272 for transmission off of the chip. If intermediate scan test chain signal 272 does not match the expected value for an output of functional circuit 340 based upon the input test vector value there is high probability of a fault in functional circuit 340.

Figure 4 is a flow chart of scan test chain intermediate debugging method 400, one embodiment of the present invention. Scan test chain intermediate debugging method 400 facilitates debugging of scan test fault indications within an IC. In one embodiment of the present invention scan test chain intermediate debugging method 400 is utilized to enhance scan test granularity and simplify analysis of scan test results.

In step 410, intermediate scan test signals are received from a scan test chain. In one embodiment of scan test chain intermediate debugging method 400, an intermediate scan test signal is received during a capture mode of a scan test system and is accomplished by deasserting a scan test enable signal and asserting a clock pulse. In one embodiment of the present invention the intermediate scan test signal is a signal received from an output of a functional logic component included in an IC after the functional logic component performs designated operations. In one exemplary embodiment of scan test chain intermediate debugging method 400, the functional logic component performs designated operations based upon scan input information (e.g., a test vector) shifted in on the scan chain and presented to inputs of the functional component.

In step 420, an intermediate scan test signal is selected for transmission off of the IC in accordance with instructions received from a dedicated intermediate control signal port. In one embodiment of the present invention, a switching circuit is manipulated to couple with an intermediate scan test signal for transmission off of the IC. In one example of step 420, a multiplexer is utilized to provide a communication path from one of its inputs to its output based upon control values sent to the multiplexer from a dedicated control signal port. In one implementation, the multiplexerOs input is coupled to the output of an internal design circuit block. Control values that determine the selection of an intermediate scan test signal are cycled in one embodiment of the present application to sequentially obtain information associated with each intermediate scan test signal.

In step 430 the intermediate scan test signal is transmitted off of an IC through a dedicated supplemental intermediate scan test signal output port. In one embodiment of the present invention, the intermediate scan test intermediate signal is utilized to facilitate debugging of scan test fault indications. In one exemplary implementation, intermediate scan test signals are retrieved from the inputs and outputs of functional logic blocks providing an indication if the functional logic block is faulty. If a test vector value input to a functional logic block is confirmed by selecting a scan test intermediate signal at the input of the functional logic block and an intermediate scan test signal value retrieved by scan test chain intermediate debugging method 400 at the output of the functional logic block does not match an expected value for a properly functioning logic circuit, there is an indication that the functional logic block is not operating properly and has a fault. Thus, the present invention is a system and method that facilitates desirable scan testing of internal components with minimal impacts to normal operations and manufacturing processes. The present invention facilitates simplification (e.g., greater granularity) of debugging analysis and assists increased fault identification accuracy. Selecting an intermediate internal scan test chain signal for transmission off of an IC facilitates isolation and analysis of a potential scan test fault while still permitting a scan test result for the entire chain via a scan test chain final output pin (not shown). A scan test chain intermediate debugging system and method of the present invention accommodates utilization of existing testing scan architectures and minimization of adverse redesign impacts to existing IC designs. The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explam the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.

Claims

CLAIMS:

1. A scan test chain intermediate debugging system included in an integrated circuit comprising: a test vector debugging control circuit (110) adapted to select an intermediate scan test chain signal (141) for transmission; a supplemental intermediate scan test signal output port (120) coupled to said test vector debugging control circuit, said supplemental intermediate scan test signal output port adapted to provide a communications port for an intermediate scan test chain signal; and a intermediate control signal port (130) coupled to said test vector debugging control circuit, said test vector intermediate control signal port adapted to provide a communications port for a control signal that directs said debugging control circuit.

2. A scan test chain intermediate debugging system of Claim 1 further comprising a plurality of circuit blocks (231) including scan test elements, said plurality of circuit blocks coupled sequentially to form a scan test chain and adapted to shift captured test data along said scan test chain.

3. A scan test chain intermediate debugging system of Claim 2 further comprising a scan test input port (221) coupled to a first circuit block of said plurality of circuit blocks, said scan test input port adapted to provide a communication port for scan test data to said first circuit block of said plurality of circuit blocks.

4. A scan test chain intermediate debugging system of Claim 2 further comprising a scan test output port (225) coupled to an end circuit block of said plurality of circuit blocks, said scan test output port adapted to transmit scan test data out.

5. A scan test chain intermediate debugging system of Claim 1 wherein said test vector debugging control circuit includes a multiplexer (215) .

6. A scan test chain intermediate debugging system of Claim 5 wherein inputs to said multiplexer includes a plurality of intermediate scan test signals (271) taken from intermediate nodes in a scan test chain.

7. A scan test chain intermediate debugging system of Claim 6 wherein said multiplexer is controlled by said control signal received through said intermediate control signal port, said control signal indicating which one of said plurality of scan test signals taken from said intermediate nodes in said scan test chain is transmitted out by said multiplexer on said supplemental intermediate scan test signal output port.

8. A scan test chain intermediate debugging system comprising: a supplemental intermediate scan test signal output port (217) adapted to provide a communications port for communicating the intermediate scan test signal off of an IC; a multiplexer (215) coupled to said supplemental intermediate scan test signal output port, said multiplexer circuit (MUX) adapted to transmitting an indicated intermediate scan test chain signal to said supplemental intermediate scan test signal output port; an intermediate control signal port (219) coupled to said multiplexer, said intermediate control signal port adapted to provide a communications port for a communicating a control signal onto said IC to indicate said intermediate scan test chain signal to forward to said supplemental intermediate scan test signal output port; a plurality of design circuit blocks (231, 232, 233) coupled to said multiplexer, said design circuit blocks adapted to perform designated functions during normal operation mode of said IC; a scan test input pin (221 ) coupled to one of said plurality of design circuit block, said scan test input pin adapted to provide a commumcation port for scan test input information; and a scan test output pin (225) coupled to one of said plurality of design circuit blocks, said scan test output pin adapted to provide a communication port for scan test output information.

9. A scan test chain intermediate debugging system of Claim 8 wherein inputs to said multiplexer includes a plurality of intermediate scan test signals (271, 272) taken from intermediate nodes in a scan test chain.

10. A scan test chain intermediate debugging system of Claim 9 wherein said multiplexer is controlled by said control signal received through said intermediate control signal port, said control signal indicating which one of said plurality of scan test signals taken from said intermediate nodes in said scan test chain is transmitted out by said mulitplexer on said supplemental intermediate scan test signal output port.

11. A scan test chain intermediate debugging method comprising the steps of: receiving an intermediate scan test signal from a scan test chain; selecting said intermediate scan test signal (271 ) for transmission off of the IC in accordance with instructions received from a dedicated intermediate control signal port (130); and transmitting said intermediate scan test signal off of an IC through a dedicated supplemental intermediate scan test signal output port (120).

12. The scan test chain intermediate debugging method of Claim 11 wherein said intermediate scan test signal is a signal received from an output of a functional logic component (231) included in an IC.

13. The scan test chain intermediate debugging method of Claim 11 wherein said step of said selecting scan test signal for transmission off of the IC comprises manipulating a switching circuit (215) to couple with an intermediate scan test signal (271) for transmission off of the IC.

14. The scan test chain intermediate debugging method of Claim 11 wherein said step of selecting scan test information for transmission off of the IC comprises utilizing a multiplexer (215) to provide a communication path from one of a plurality of inputs to said multiplexer to an output of said multiplexer based upon control values sent to the multiplexer from a dedicated control signal port (219).

15. The scan test chain intermediate debugging method of Claim 14 wherein one of said plurality of inputs to said multiplexer is coupled to the output of an internal design circuit block (231) and one of said plurality of inputs to said multiplexer is coupled to a test data in signal to said internal design circuit block in said scan test chain.

16. The scan test chain intermediate debugging method of Claim 11 further comprising the step of utilizing said intermediate scan test signal to facilitate debugging of scan test fault indications.

17. The scan test chain intermediate debugging method of Claim 11 further comprising cycling control values that determine the selection of an intermediate scan test signal to sequentially obtain information associated with each intermediate scan test signal (271, 272).