KR19990047437A - Semiconductor device with bypass circuit using scan chain - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bypass circuit, and more particularly, to a bypass circuit for improving a test capability of a peripheral circuit block by using a scan chain. In the case of the circuit, the bypass circuit using the scan chain can be built-in to independently test the peripheral logic to be tested.

Description

SEMICONDUCTOR APPARATUS HAVING BYPASS CIRCUIT USING SCAN CHAIN

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a bypass circuit for improving a test capability of a peripheral circuit block using a scan chain.

1 to 3 are diagrams for explaining the background of the present invention.

Referring to FIG. 1, considering block-based design, the normal operation of the circuit 10 is based on blocks A, B, and C (13, 14, 15) from input to output. Will go through. Dotted lines 11 and 12 shown in the figure indicate a path through which the circuit 10 is connected to the block B 14 when the circuit 10 is in a test mode. In the design of such a circuit, block B (14) is a core part of the circuit, and block A (13) and block C (15) can be regarded as neighboring blocks. Macro blocks such as core or memory are considered. In the case of a circuit in which (Macro Block) is incorporated, such a circuit configuration is frequently used. Testing of the circuit 10 having such a configuration is typically performed in units of blocks. In particular, the testing of the critical block B 14 is performed by directly passing the input / output of the circuit through the path indicated by reference numeral 20 as shown in FIG. 2 due to the complexity of the internal logic or the size. Can be done.

For example, testing of cores that do not include a boundary scan circuit is very difficult to control using peripheral blocks. Therefore, a test vector developed exclusively for the core itself is directly applied from outside and directly. You have no choice but to monitor it. In addition, in the case of a memory block, it is very inefficient to apply a test algorithm through a neighboring block. Therefore, unless the BIST method is used, direct access is performed. You have no choice but to test it.

However, in the above configuration, the test of the block B 14 is easily performed, but the test of the remaining blocks is very difficult because the test of the remaining block has to go through the block B 14. In general, structurally complex block B 14 can significantly reduce the testability of neighboring blocks. Specifically, block A 13 addresses the problem of observability, and block C 15 There is a problem of controllability. Therefore, in such a case, a method of bypassing the block B 14 is required so that the peripheral logic can be independently tested regardless of the block B 14.

Of course, as shown in FIG. 3, the output of block A 13 and the input of block C 15 are referred to to satisfy the observation capability of block A 13 and the control capability of block C 15 simultaneously. It is pulled out directly to the external pin as shown at 16 and 17. However, in this case, since an additional pin is required, the pin overhead of the heavy pin may be increased depending on the circuit, thereby decreasing practicality.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a semiconductor device having a bypass circuit that can improve the test capability of a peripheral circuit block using a scan chain circuit. It is.

1 to 3 are views for explaining the background of the present invention;

4 is a block diagram of a semiconductor circuit including a bypass circuit using the scan chain of the present invention;

5 is a block diagram for explaining the operation of the present invention; And

6 is a circuit diagram according to an embodiment of a scan chain block.

According to a feature of the present invention for achieving the object of the present invention as described above, a semiconductor device comprising a first circuit block, a second circuit block, and a third circuit block includes: the first circuit A bypass circuit block configured between the block and the third circuit block to bypass the second circuit block.

In this embodiment, the bypass circuit block includes: a first pass for outputting the output of the first circuit block to the outside in a test mode of the first circuit block; A second pass for inputting test data into the third circuit block in a test mode of the third circuit block; And a third path for inputting the output of the first circuit block to the third circuit block in a mode of simultaneously testing the first circuit block and the third circuit block.

In this embodiment, the bypass circuit block consists of a scan chain circuit.

In this embodiment, the scan chain circuit is composed of a plurality of multiplexers and a plurality of flip-flops respectively corresponding thereto.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a semiconductor circuit including a bypass circuit using the scan chain of the present invention, and FIG. 5 is a block diagram for explaining the operation of the present invention. 6 is a circuit diagram according to an embodiment of a scan chain block.

Referring to FIG. 4, in accordance with a preferred embodiment of the present invention, a scan chain block 36 is formed between block A 33 and block C 35 by bypassing block B 34. Thus, in addition to the pin for the test mode signal (Test Mode Signal) input, it is possible to test the block A (33) and the block C (35) by adding only three pins. The 3 pins added here are scan_in, scan_out, and scan_enable.

A multiplexer (not shown) for selecting an output of the block B 34 and an output of the scan chain block 36 is implemented at an input of the block C 35, which may be controlled by a test mode signal. The scan chain block 36 may monitor the output of block A 33 through a Scan Operation, or is used to load the input of block C 35. Thus, the observation ability of block A 33 and the control ability of block C 35 are completely solved through a scan operation.

Additionally, during normal operation, i.e., when the scan-enable signal is disabled, the output of block A 33 is one clock at the flip-flop in scan chain block 36. Delayed and passed to block C (35). Therefore, the tests of the block A 33 and the block C 35 are performed in the mode of simultaneously testing the block A 33 and the block C 35 as shown in FIG. 5 and only the block A 33. The mode of testing and the mode of testing only the block C 35 may be composed of three modes. Arrow 40 denotes a path for testing blocks A 33 and C 35, reference 41 a path for testing only block A 33, and reference 42 for a block C 35 only. Show the test path.

FIG. 6 shows an embodiment of the scan chain block 36 shown in FIG. 4.

The scan chain block 36 is divided into first to fourth multiplexers 50, 51, 54, and 56 and first to fourth flip-flops 51, 53, 55, and 57 for input / output 4 bits. It is composed. In other words, the number of outputs of the block A 33 and the number of inputs of the block C 35 are equal to four. The length of the scan chain may be the larger of the number of outputs of the block A 33 and the number of inputs of the block C 35, and the remaining signals are not used. The configuration of the scan chain has the advantage that the scan chain is shorter in length and the scan cell is smaller in size than the boundary scan at the output of the block A 33 and the input signal lines of the block C 35. .

According to the present invention as described above, even in the case of a semiconductor device including a structurally complex circuit block, it is possible to independently test the peripheral logic provided therein by embedding a bypass circuit using a scan chain.

Claims (4)

In a semiconductor device comprising a first circuit block 33, a second circuit block 34, and a third circuit block 35: A bypass circuit block 36 configured between the first circuit block 33 and the third circuit block 35 to bypass the second circuit block 34. Semiconductor device. The method of claim 1, The bypass circuit block 36 A first pass 41 which outputs the output of the first circuit block 33 to the outside in the test mode of the first circuit block 33; A second pass (42) for inputting test data into the third circuit block (35) in the test mode of the third circuit block (35); A third input of the output of the first circuit block 33 to the third circuit block in a mode in which the first circuit block 33 and the third circuit block 35 are simultaneously tested; And a path. The method of claim 1, The bypass circuit block 36 A semiconductor device comprising a scan chain circuit. The method of claim 3, wherein The scan chain circuit may include a plurality of multiplexers and a plurality of flip-flops respectively corresponding thereto.