KR100212095B1 - Semiconductor device - Google Patents

Abstract

The present invention relates to a semiconductor device and a stacked semiconductor device, which cannot accommodate a large semiconductor chip, have poor heat dissipation, have a high cost, have a low mechanical strength, and a problem such as a decrease in reliability of thermal stress and an increase in built-in area. In order to solve the problem, in the semiconductor device in which the inner lead portion is fixed to the circuit forming surface of the semiconductor chip via an insulating adhesive film and electrically connected to the external terminal on the semiconductor chip, the back surface facing the circuit forming surface of the semiconductor chip. It extends to and here it is set as the chip size of the shape which electrically connects with an external device.

By using such a device, the package can be made approximately the same size as the semiconductor chip, and the heat dissipation efficiency, the mechanical strength, the internal density, and the cost can be reduced.

Description

Semiconductor device

1 is a plan view partially developing the entire configuration of a small resin-encapsulated semiconductor device according to the first embodiment of the present invention.

2 is a cross-sectional view of the main portion taken along the line A-A shown in FIG.

3 is a plan view showing the structure of the lead frame of the first embodiment;

4 is a semiconductor chip layout diagram of an embodiment of the present invention.

5 is a cross-sectional view for explaining the configuration of the insulating adhesive film of the embodiment of the present invention.

6 is a cross-sectional view for explaining the configuration of the solder bump electrode of the embodiment of the present invention.

7 (a) and 7 (b) are views for explaining the assembling method of the embodiment.

8, 9 and 10 show the structure of a modification of the first embodiment.

11 is a cross-sectional view of an apparatus for manufacturing a flow stopping member of resin.

12 is a view for explaining the supply nozzle shape shown in FIG.

13 is a view for explaining the configuration of the flow stop member of the resin of the first embodiment.

FIG. 14 is a view showing a modification of Embodiment 1 made into a mold without providing the flow stop member of the resin. FIG.

FIG. 15 shows an example in which two small resin-encapsulated semiconductor devices of Embodiment 1 are stacked on an embedded substrate; FIG.

FIG. 16 is a sectional view of an essential part of an ultra-thin resin-encapsulated semiconductor device according to Embodiment 2 of the present invention. FIG.

17 is a cross-sectional view for explaining the configuration of the gold bump electrode of the embodiment of the present invention.

18 is a sectional view of principal parts of a resin-encapsulated semiconductor device, according to a third embodiment of the present invention.

19 (a) and 19 (b) are plan views showing the arrangement of the external terminals (bonding pads) of the semiconductor chip of Example 3 and the positional relationship between the respective external terminals and the lead pins.

20 is a plan view showing the entire configuration of the lead frame of the third embodiment;

21 is a sectional view of principal parts of a modular semiconductor device of Embodiment 4 of the present invention;

FIG. 22 is a circuit diagram showing the system configuration of the modular semiconductor device shown in FIG.

23 to 26 are plan views showing the connection relationship between the input / output terminals and the external leads of each semiconductor chip.

27 is a view showing a modification of the fourth embodiment.

FIG. 28 shows an example in which a plurality of stacked semiconductor devices of Example 4 are embedded by soldering onto a built-in substrate; FIG.

Fig. 29 is a perspective view showing the overall configuration of a small resin-encapsulated semiconductor device according to a fifth embodiment of the present invention.

30 is a cross-sectional view of a main portion taken along line A-A shown in FIG. 29;

FIG. 31 is a cross-sectional view showing a structure in which heat dissipation fins are provided on the back surface of the semiconductor chip of Example 5. FIG.

32 is a sectional view of an essential part of an ultra-thin resin-encapsulated semiconductor device according to a sixth embodiment of the present invention.

33 is a cross-sectional view showing a state in which the compact, ultra-thin resin-encapsulated semiconductor device of Embodiment 6 of the present invention is embedded in a card substrate.

34 is a sectional view of principal parts of a resin-encapsulated semiconductor device, according to a seventh embodiment of the present invention.

35 is a plan view showing the relationship between the lead frame and the semiconductor chip of the seventh embodiment.

36 and 37 are cross-sectional views showing the structure of the insulating adhesive film of the seventh embodiment.

38 is a flowchart for explaining the assembling process of the resin-encapsulated semiconductor device of the seventh embodiment.

39 is a view for explaining a modification of the resin-encapsulated semiconductor device of the seventh embodiment.

40 is a sectional view of principal parts of a resin-encapsulated semiconductor device, according to Embodiment 8 of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a stacked semiconductor device, and more particularly, to a semiconductor device and a stacked semiconductor device in which leads and external terminals of the semiconductor chip are electrically connected in terms of circuit formation of the semiconductor chip.

Conventionally, as a resin-encapsulated compact semiconductor device, for example, as described in US Pat. No. 4,943,843, a plurality of internal leads are fixed to the circuit forming surface of the semiconductor element via an insulating film, wire-bonded by gold wire, and made of resin. Some molds have a mold on chip (LOC) structure.

Further, as described in Japanese Patent Application Laid-open No. Hei 1-217933, a finger-shaped lead is projected into the device hole, the semiconductor chip is face-bonded and bonded to the tip of the lead, and the chip is molded by resin or the like. In addition, there is a TAB (Tape Automated Bonding) method in which a frame member is attached to the tape carrier so that the outer lead does not protrude from the end edge of the tape, or the outer lead is bent to the rear surface of the frame member.

In addition, as described in Japanese Patent Application Laid-open No. Hei 1-186390, a semiconductor chip encapsulated in a package and one end thereof are connected to the semiconductor chip, and the other end is outside the package from the back side of the semiconductor chip. There is a thin semiconductor device having an exposed lead, formed by the metal foil, and bent in the encapsulant layer of the package and exposed to the outside of the package.

In addition, as described in Japanese Patent Application Laid-Open No. 2-198148, a plurality of semiconductor devices thinned using TAB are stacked, and each semiconductor device is electrically connected by an interlayer bonding layer provided on an outer frame, respectively. There is a stacked semiconductor device.

However, the present inventors have found the following problems as a result of examining the conventional LOC structure semiconductor device, TAB type semiconductor device, thin semiconductor device, and stacked semiconductor device.

Since the semiconductor device of the conventional LOC structure has a structure in which the periphery of the semiconductor chip is sealed with a resin by, for example, a transfer molding method, the size of the semiconductor chip that can be accommodated for a package dimension of a predetermined size is small and the package is small. The thickness of is also about 1mm, the heat dissipation generated in the semiconductor chip is not good.

In the conventional TAB system, the external terminal (electrode) of the semiconductor chip is special, so that the ghost is high.

In addition, since the inner lead is not directly fixed to the semiconductor chip, the mechanical strength is small, so that the reliability of the thermal stress generated by the temperature stress is lowered.

Moreover, since a lead is formed in a polyimide film by the etching technique, cost becomes high.

In the conventional thin semiconductor device described in Japanese Patent Application Laid-Open No. 1-186390, since a sealing resin exists on the circuit forming surface of the semiconductor chip, a multilayer semiconductor device in which several semiconductor devices are directly stacked and modularized can be used. Can't.

In addition, since only the back surface of the semiconductor chip is exposed, heat dissipation generated in the semiconductor chip is not good.

Further, in the conventional stacked semiconductor device, since the lead is fixed only by the bump electrodes, a stacking outer frame supporting weak strength is required.

Moreover, the built-in area of this lamination external frame becomes large.

In addition, the heat dissipation becomes poor due to the outer frame for lamination.

An object of the present invention is to provide a technique capable of accommodating a large semiconductor chip and also obtaining an ultra-thin package.

Another object of the present invention is to provide a technique capable of efficiently dissipating heat generated in a semiconductor chip.

Another object of the present invention is to provide a semiconductor device in which the built-in area is approximately equal to the area of the semiconductor chip.

Another object of the present invention is to provide a compact and ultra-thin semiconductor device which can be easily manufactured by stacking a plurality of semiconductor devices.

Another object of the present invention is to provide a stacked semiconductor device in which a plurality of semiconductor devices are stacked to form a module.

It is another object of the present invention to provide a compact and ultra-thin semiconductor device capable of alleviating thermal stress due to temperature stress in a state in which a package is soldered to a substrate.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Brief descriptions of representative of the inventions disclosed herein are as follows.

(1) A semiconductor device in which a lead and an external terminal of the semiconductor chip are electrically connected on a circuit forming surface of a semiconductor chip and sealed with resin, wherein the lead is fixed to the circuit forming surface of the semiconductor via an insulating adhesive layer, and the lead Is a semiconductor device which extends from the circuit formation surface of the semiconductor chip to the back surface and is fixed to the back surface of the semiconductor chip through an insulating adhesive layer.

(2) A semiconductor device in which a semiconductor chip is sealed by a means (resin) in which a lead and an external terminal of the semiconductor chip are electrically connected and sealed in a circuit formation surface, wherein the lead is formed on the circuit formation surface of the semiconductor via an insulating adhesive layer. It is fixed, and only a part of the circuit forming surface portion of the semiconductor chip is sealed by means (resin), and the lead extends from the circuit forming surface of the semiconductor chip to the back surface, and interposes an insulating adhesive layer on the back surface of the semiconductor chip. Is a semiconductor device that is fixed.

(3) The electrical connection between the lead and the external terminal of the semiconductor chip is made of metal wire or metal bump or metal ball.

(4) A stacked semiconductor device comprising a plurality of semiconductor devices stacked and a means for selecting each semiconductor device.

(5) In a semiconductor device in which a lead and an external terminal of the semiconductor chip are electrically connected on the circuit forming surface of the semiconductor chip and sealed with resin, the lead is fixed to the semiconductor circuit forming surface via an insulating adhesive layer. Only the circuit forming surface portion or the circuit forming surface portion and the side surface portion of the semiconductor chip are sealed with resin.

(6) The outer lead portion of the lead has a shape suitable for thinning in in-plane mounting.

(7) The outer lead of the lead of the above-mentioned (5) is comprised in the shape which can relieve thermal stress.

(8) The electrical connection of the lead of the above-mentioned (5) and the external terminal of the semiconductor chip is made of metal wire or metal bump or metal ball.

According to the above-described means (1) and (2), only a part of the circuit forming surface portion of the semiconductor chip is sealed with a resin, so that the package can have a dimension substantially the same as that of the semiconductor chip.

Moreover, since portions other than a part of the circuit forming surface portion of the semiconductor chip are exposed, the heat radiation efficiency can be improved.

In addition, since the lead is fixed to the circuit formation surface of the semiconductor chip by the insulating adhesive layer, mechanical stress due to heat generated by the difference in thermal expansion coefficient between the embedded wiring board and the semiconductor chip or the lead shaping when embedded in the embedded wiring board Resistant to mechanical stress during bending.

In addition, since the lead is also exposed on the circuit formation surface of the semiconductor chip, a modular semiconductor device can be easily manufactured by stacking a plurality of semiconductor devices and providing a means for selecting each semiconductor device.

In addition, since the built-in bonding surface of the outer lead bent to the rear surface is disposed on substantially the same plane, it is possible to improve the solder bonding efficiency and the electrical reliability when the semiconductor device is embedded by soldering the embedded wiring board.

According to the aforementioned means (3), since the electrical connection between the lead and the external terminal of the semiconductor chip is made of metal wires or metal bumps or metal balls, it is possible to use a conventional lead frame made by pressing or etching. Can be reduced.

According to the means 4 described above, since a plurality of semiconductor devices are laminated and provided as a stacked semiconductor device provided with means for selecting each semiconductor device, the built-in density can be improved.

According to the means 5 described above, only the circuit forming surface portion or the circuit forming surface portion and the side surface portion of the semiconductor chip are sealed with resin, so that the package can be made approximately the same size as the semiconductor chip. Moreover, since the surface opposite to the circuit formation surface part of a semiconductor chip is exposed, heat dissipation efficiency can be improved. In addition, since the lead is fixed to the circuit forming surface of the semiconductor chip by the insulating adhesive layer, the mechanical strength of the lead is large, so that the reliability is high with respect to mechanical stress and thermal stress.

According to the means 6, since the outer lead portion of the lead has a shape suitable for thinning in in-plane mounting, an ultra-thin package can be obtained.

For the means 7, since the outer lead of the lead is formed in a shape that can alleviate the thermal stress, the thermal stress when the semiconductor device is embedded in the substrate by soldering can be alleviated. In this state, thermal stress due to temperature stress can be alleviated.

According to the means 8, since the electrical connection between the lead and the external terminal of the semiconductor chip is made of a wire and a metal ball, a conventional lead frame made by a press or an etching method can be used, and the cost can be reduced.

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described concretely using drawing.

In addition, in the whole drawing for demonstrating an embodiment, the thing which has the same function is attached | subjected with the same code | symbol, and the repeated description is abbreviate | omitted.

Example 1

FIG. 1 is a plan view showing a part of the overall structure of a small resin-encapsulated semiconductor device of Embodiment 1 of the present invention.

FIG. 2 is a sectional view of an essential part taken along line A-A shown in FIG.

As shown in FIG. 1 and FIG. 2, the small resin bag type semiconductor device 20 of the first embodiment has an insulating adhesive film (tape) 2 interposed on the circuit formation surface of the semiconductor chip 1. The lead 3 is fixed, and the inner lead 3A of the lead 3 and the external terminal (aluminum electrode) of the semiconductor chip 1 are electrically connected by the solder bump electrode 4. The inner lead 3A of the lead 3 and the external terminal (aluminum electrode) of the semiconductor chip 1 are electrically connected to each other by the solder bump electrode 4 on the circuit formation surface of the semiconductor chip 1. The resin flow stopping member 5 is provided to surround the portion. Inside the resin flow stop member 5, a liquid resin 6 made of epoxy resin or the like is injected by a potting method and sealed with a liquid resin 6. The outer lead 3B of the lead 3 extends by bending from the circuit formation of the semiconductor chip 1 to the back side, as shown in FIG. 2, and the insulating adhesive film 7 on the back side of the semiconductor chip 1. It is fixed by interposing.

In the resin-encapsulated semiconductor device 20, as shown in FIG. 1, terminal 1, terminal 2, .., terminal 14 (terminal 7, terminal 8 is not present) sequentially from the top left to the bottom. Terminals 15, 16, ..., 28 (without 21 and 22) are arranged in order from the bottom right to the top, and are made up of 24 terminals (24 pins) in total.

The signals applied to each of the external leads 3B include, for example, a control system signal, an address system signal, a data system signal, and a power supply. The control system signal is a low address strobe system signal. , Column address strobe signal , The light enable signal WE. The data system signal includes a data output signal Dout and a data input signal Din. The power source has a reference power supply voltage Vss, for example, the ground potential of the circuit 0V, an operating power supply voltage Vcc, for example, the circuit operating voltage 5V.

As shown in FIG. 3, the structure of the entire lead frame of the lead 3 includes 24 internal leads 3A, 24 external leads 3B, semiconductor chip support leads 3C, and their leads ( 3) It is composed of an external frame (3D) that supports and is integrally constructed.

Then, the insulating adhesive films 2 and 7 are bonded to the predetermined position of the lead frame. The lead 3 is made of a Fe-based (42Ni-Fe material) or a Cu-based thin plate or foil, and is plated with Ag, Au or the like on the surface as necessary for bonding and solder bonding.

The semiconductor chip (pellet) 1 is formed of a planar rectangular single crystal silicon substrate, and a DRAM having a large capacity of 26 Mbit is mounted on the circuit formation surface of the semiconductor chip 1 (the surface opposite to the inner lead 3A). . In this DRAM configuration, as shown in FIG. 4 (chip arrangement diagram), the memory cell array MARY is disposed almost in front of the circuit formation surface of the semiconductor chip 1. The memory cell array MARY is divided into 64 of the fourth drawings and arranged. One subdivided memory cell array, MARY, has a capacity of 256 Kbit. The 64 subdivided memory cell arrays MARY have 16 blocks on the left side, 16 on the right side, 16 on the right side, 16 on the right side, and 16 blocks on the right side. Construct a block.

A sense amplifier circuit SA is disposed between two memory cell arrays MARY of the 64 subdivided ones. Further, a low address decoder circuit XDEC and a word driver circuit WD, which are direct system peripheral circuits, are disposed at the center of each semiconductor chip 1 of the 64 memory cell arrays MARY.

Among the four blocks, a column address decoder circuit YDEC and a peripheral circuit MC, which are direct peripheral circuits, are disposed between each of the upper left and lower left blocks. Similarly, the column address decoder circuit YDEC and the peripheral circuit MC are disposed between each block on the upper right and the lower right. The peripheral circuit MC is an indirect peripheral circuit, for example Circuit, The system circuit, the address buffer circuit, the power supply limit circuit, and the like are arranged. Each of the direct system peripheral circuit and the indirect system peripheral circuit is basically composed of a combination of a complementary MISFET and a biplatistor.

Among the four blocks, a plurality of external terminals (bonding pads) BPs are disposed between the respective blocks on the upper left and the upper right and between each block on the lower left and the lower right. That is, several of these external terminals BP are arranged in the longitudinal direction of the semiconductor chip 1 in the fourth direction (from top to bottom).

In each of the 64 subdivided memory cell arrays MARY, a plurality of memory cells holding one bit of information are arranged in a matrix form. The memory cell consists of a series circuit of a memory cell selection MISFET and an information side application capacitor.

The said insulating adhesive films (tape) 2 and 7 are tapes which consist of a thermosetting or thermoplastic single layer (adhesive only) or a double-sided adhesive layer (structure of three or more layers). For example, as shown in Fig. 5, the insulating adhesive films 2 and 7 of the three-layer structure have a multilayer structure of the adhesive layer A, the substrate B, and the adhesive layer A. For example, polyetheramide Imide 25 micrometers / capton 50 micrometers / polyether amide imide 25 micrometers. Instead of the Kapton, another polyimide film may be used.

The solder bump electrode 4 has two barrier metal layers 52 of Cu / T1 formed on the A1 electrode (pad) 51 of the circuit formation surface of the semiconductor chip 1, as shown in FIG. The Ni layer 53 is formed thereon, and the solder bumps (Pb / Sn) 4 are formed on it, and it is produced.

The thickness of the semiconductor chip 1 is, for example, 0.2 to 0.5 mm, the thickness of the liquid resin 6 is, for example, 0.25 to 0.6 mm, and the thickness of the lead 3 is, for example, 0.1 to 0.25 mm, insulating adhesive. The thickness of the film 2 is, for example, 25 to 125 µm for the insulating film (substrate) and 10 to 30 µm for the adhesive layer.

For example, in the first embodiment, the thickness of the semiconductor chip 1 is 0.3 mm, the height of the liquid resin 6 in the lead 3 is 0.1 mm, the thickness of the lead 3 is 0.1 mm, and the insulating adhesive film ( The thickness of 2) is 0.05 mm, and the overall thickness of the semiconductor device is 0.7 mm. Therefore, the effective height, which is the height of the semiconductor devices other than the uppermost layer in the case of stacking the semiconductor devices, becomes 0.6 mm.

Next, the assembly method of the first embodiment will be briefly described.

As shown in Fig. 7 (a), a lead frame having an insulating adhesive film (tape) 2 is mounted on the circuit formation surface of the semiconductor chip 1 having the solder bump electrodes 4, and a heating block is provided. By bonding an insulating adhesive film (tape) 2 on the circuit forming surface of the semiconductor chip 1, and at the same time, the inner lead 3A of the lead 3 and the solder bump electrode 4 of the semiconductor chip 1 Splice.

Next, as shown in FIG. 7 (b), the tip of the outer lead 3B of the lead 3 is bent, and then bent in parallel with the side surface of the semiconductor chip 1 by a roller or the like, and an insulating crimping film (tape). (7) is thermocompression-bonded to the back surface portion of the semiconductor chip 1.

Next, the resin flow stopping member 5 is formed on the circuit formation surface of the semiconductor chip 1, and then the liquid resin 6 is dipped (poored), and cured to complete it.

By configuring in this way, since the sealing resin 6 does not exist in the back surface part of the semiconductor chip 1, the thickness of a package can be made thin about 0.6 mm.

Moreover, since only a part of the circuit formation surface of the semiconductor chip 1 is exposed, heat dissipation efficiency is improved.

In addition, since the lead 3 is fixed to the semiconductor chip 1 by the insulating adhesive films 2 and 7, the semiconductor chip 1, which becomes monocrystalline silicon when embedded in an embedded wiring board such as a printed circuit board, is provided. Even if the lead 3 receives a mechanical stress due to heat due to the difference in thermal expansion rate of the over-embedded wiring board, there is no problem that the connection portion of the semiconductor chip 1 and the lead 3 falls or breaks.

Moreover, since it is the same structure, it is strong also in the mechanical stress at the time of bending of a lead.

Moreover, since the lead 3 is exposed also on the circuit formation surface of the semiconductor chip 1, the said semiconductor device can be directly laminated | stacked and a modular semiconductor device can be manufactured easily.

In addition, when the semiconductor device is soldered to the internal wiring board and embedded therein, the internal adhesion surface of each external lead 3B bent to the rear surface is formed on the back surface of the semiconductor chip 1 with the insulating adhesive film 7 and the external lead ( Since they are arranged on substantially the same plane at positions separated by the thickness of 3B), the electrical reliability of the built-in adhesive portion can be improved. Thereby, the manufacturing efficiency of a built-in adhesive part can also be improved.

In the first embodiment, the lead 3 is fixed to the semiconductor chip 1 by the insulating adhesive films 2 and 7, but the adhesive area or place of the insulating adhesive films 2 and 7 is not changed. 8, 9, and 10 show a configuration of a modification of the first embodiment in which the lead 3 is increased to prevent deformation and insulation failure. In FIG. 8, the inner lead 3A and the external terminal of the semiconductor chip 1 are connected by a bonding wire 31 of Au or A1. That is, the inner lead 3A and the outer terminal of the semiconductor chip 1 may be electrically connected, and the connection means may be anything. In addition, in Example 1 and a modification, the liquid resin 6 is not necessarily required.

Next, a method of manufacturing the resin flow stop member 5 will be described.

11 is a cross-sectional view of the manufacturing apparatus of the resin flow stopping member 5, wherein 101 is a cylinder, 102 is a plastic plate, 103 is a resin flow stopping material, and 104 is a resin flow stopping material 103. Supply of The shape of the supply port 105 of this supply nozzle 104 is formed with a rectangular ring, for example as shown in FIG.

By this manufacturing apparatus, the resin flow stop member 5 of the rectangular frame as shown in FIG. 13 (a) is a plan view and (b) is a sectional view taken along the line B-B.

The resin flow stop member 5 of this rectangular frame is attached on the circuit formation surface of the semiconductor chip 1 with an insulating adhesive agent.

In the first embodiment, sealing with resin is carried out by potting. However, as shown in Fig. 14, the resin flow stopping member 5 may be sealed by a transfer molding method.

15 shows a state in which two small resin-encapsulated semiconductor devices 20 of the first embodiment are bonded together by soldering 22 on the embedded substrate 21 and shown in FIG. This laminated type will be described later in detail in another embodiment.

Example 2

FIG. 16 is a sectional view of an essential part of an ultra-thin resin-encapsulated semiconductor device of Example 2 of the present invention.

In the ultra-thin resin-encapsulated semiconductor device of the second embodiment, as shown in FIG. 17, gold (Au) balls (or gold) are formed on the A1 electrode (pad) 51 of the circuit formation surface of the semiconductor chip 1. (Au bump electrode) 4A is formed, and the tip of the inner lead 3A plated with tin (Sn) of the lead 3 on the gold (Au) ball (or gold (Au bump electrode)) 4A. At the same time, the lead 3 is fixed with the insulating adhesive film 2 interposed therebetween by direct thermocompression bonding. The circuit forming surface of the semiconductor chip 1 is used as it is without being sealed with a liquid resin such as epoxy resin.

The gold (Au) ball 4A is manufactured by a nail head bonding of gold (Au) wire on the A1 electrode (pad) 51 and then removing a gold wire other than the ball part.

The gold bump electrode 4A forms a two-layer barrier metal layer 54 made of Pb / Ti, W / Ti, Pt / Ti, etc. on the A1 electrode (pad) 51 as shown in FIG. It is produced by forming a gold bump on it.

By doing in this way, since the resin which seals on the circuit formation surface of the semiconductor chip 1 does not exist, it can be made thinner than the thickness of the package of Example 1 above.

A gold ball 4A is formed on the A1 electrode 51 of the circuit formation surface of the semiconductor chip 1, and the tip of the inner lead 3A, which is tin-plated of the lead 3, directly on the gold ball 4A. Since it is thermocompression-bonded, an ultra-thin semiconductor device is obtained.

Example 3

18 is a sectional view of an essential part of a resin-encapsulated semiconductor device according to a third embodiment of the present invention.

FIG. 19 (a) is a plan view showing the arrangement of external terminals (bonding pads) of the semiconductor chip of the third embodiment; FIG. 19 (b) is a view showing the positional relationship between the external terminals and the lead pins; Fig. 3 shows the overall configuration of the lead frame of the third embodiment.

18 to 20, the small resin-encapsulated semiconductor device 30 of the third embodiment of the present invention has a lead (with an insulating adhesive film 2 interposed on a circuit forming surface of the semiconductor chip 1). 3) is fixed, and the inner lead 3A (the signal inner lead 3A ₁ and the common inner lead 3A ₂ ) of the lead 3 and the external terminal (bonding pad) of the semiconductor chip 1 are fixed. Is electrically connected to the bonding wire (Au wire) 31. On the circuit forming surface of the semiconductor chip 1, a resin flow stopping member 5 is formed so as to surround a portion where the inner lead 3A of the lead 3 and the external terminal of the semiconductor chip 1 are electrically connected. It is prepared. Inside the resin flow stop member 5, a liquid resin 6 made of epoxy resin or the like is injected by a potting method and sealed with a liquid resin 6. The outer lead 3B of the lead 3 extends by bending from the circuit formation surface of the semiconductor chip 1 to the back surface and is fixed to the back surface of the semiconductor chip 1 with an insulating adhesive film 7 interposed therebetween.

The package of the third embodiment makes the width dimension L2 between the portions bent to the rear surface of the semiconductor chip 1 of the outer lead 3B larger than the dimension L1 between the resin flow stopping members 5, The dimension (depth) D2 from the rear surface of the semiconductor chip 1 to the outer surface of the portion bent to the rear surface of the external lead 3B is farthest from the circuit formation surface of the semiconductor chip 1 from the upper surface of the external lead 3B. It is larger than the height dimension D1 to the outer surface of the resin 6.

For example, as shown in FIG. 18, the thickness of each part is 0.3 mm in thickness E of the semiconductor chip 1, 0.2 mm in thickness of the lead 3, and 0.1 mm in thickness of the insulating adhesive film 7. , The thickness (depth D2) from the rear surface of the semiconductor chip 1 to the outer surface of the portion bent to the rear surface of the external lead 3B, the outer side of the external lead 3B on the circuit formation surface of the semiconductor chip 1 The thickness (D1) from one side to the outer side of the resin 6 is 0.25 mm. Therefore, the thickness F of the small resin-encapsulated semiconductor device 30 is 1.15 mm, and when laminated, the effective height G is 0.9 mm.

The semiconductor chip 1 is 16MDRAM, and has the same arrangement as shown in FIG. 4 (Example 1). The arrangement of the external terminals (bonding pads) is shown in FIG. 19 (a). The positional relationship between each external terminal and the lead pin is shown in Fig. 19B.

As shown in FIG. 19 (b), the resin-encapsulated semiconductor device 30 has terminals 1, 2, ..., 14 (terminal 7, terminal 8, None) are sequentially arranged, and terminals 15, 16, ..., 28 (no 21 and 22) are arranged in order from the bottom right to the total 24 terminals (24 pins). It is composed.

The signal applied to the external lead 3B includes, for example, a control system signal, an address system signal, a data system signal, and a power supply.

The control system signal is a low address strobe system signal. , Column address strobe signal , The light enable signal WE.

The data system signal includes a data output signal Dout and a data input signal Din. The power supply has a reference power supply voltage Vss, for example, the ground potential of the circuit 0V, the operating power supply voltage Vcc, for example, the circuit operating voltage 5V.

As shown in FIG. 20, the structure of the entire lead frame of the lead 3 includes 22 inner leads 3A, 24 outer leads 3B, semiconductor chip support leads 3C, and their leads ( It consists of the outer frame 3D which supports 3), and is integrally formed. Then, the insulating adhesive films 2 and 7 are bonded to the predetermined position of the lead frame. As described above, the inner lead 3A includes a signal inner lead 3A ₁ and a common inner lead 3A ₂ . By configuring in this way, the same effect as Example 1 can be obtained.

Example 4

21 is a cross-sectional view of an essential part of the modular semiconductor device according to the fourth embodiment of the present invention, and FIG. 22 is a circuit diagram showing the system configuration of the modular semiconductor device shown in FIG. 21, and FIGS. I / O terminal (bonding pad) A plan view showing a connection relationship between Din and Dout and an external lead.

In the modular semiconductor device of the fourth embodiment, as shown in FIG. 21, four 16MDRAMs 40A, 40B, 40C, and 40D of the third embodiment are placed on the embedded substrate 41. As shown in FIG. (Laminated package configuration example of 16 MDRAM x 4).

The system of the modular DRAM has a circuit configuration as shown in FIG.

That is, the low address strobe system signal applied to each of the four external leads 3B of 16MDRAM 40A, 40B, 40C, and 40D. , Column address strobe signal The mite enable signal WE, the reference power supply voltage Vss, and the operating power supply voltage Vcc are commonly input to four corresponding external leads 3B of 16MDRAM 40A, 40B, 40C, and 40D. .

In addition, the X and Y signals are inputted to the address multiplex to each of the address A0 to A11 pins of the 16MDRAMs 40A, 40B, 40C, and 40D.

In the fourth embodiment, as shown in FIG. 22, the terminals 16 and 16 are stacked so that the different leads (pins) of the stacked 16MDRAMs 40A, 40B, 40C, and 40D are the terminals D0 to D3 for input / output. I / O terminals (bonding) of terminals D0 to D3 of the corresponding external leads 3B and the 16MDRAMs 40A, 40B, 40C, and 40D, respectively, in order to use D0 to D3 and the selection terminal. Pads) Din and Dout are connected by bonding wires 31.

For example, as shown in FIG. 23, the bonding connection of the 16MDRAM 40A is performed by connecting the input / output terminals Din and Dout of the 16MDRAM 40A and the second terminal D0 of the external lead 3B to the bonding wire 31. As shown in FIG. Connect.

Similarly, the bonding connection of the 16MDRAM 40B connects the input / output terminals Din and Dout of the 16MDRAM 40B and the third terminal D1 of the external lead 3B to the bonding wire 31, as shown in FIG. .

As shown in FIG. 25, the bonding connection of the 16MDRAM 40C connects the input / output terminals Din and Dout of the 16MDRAM 40C and the 27th terminal D2 of the external lead 3B to the bonding wire 31. As shown in FIG.

The bonding connection of the 16MDRAM 40D connects the input / output terminals Din and Dout of the 16MDRAM 40D and the 26th terminal D3 of the external lead 3B to the bonding wire 31 as shown in FIG.

In this way, each of the input and output terminals Din, Dout of the 16MDRAMs 40A, 40B, 40C, and 40D is connected to the bonding wires 31, and terminals D0 to D3 of the external lead 3B. By stacking them, a 64 Mbit modular semiconductor device having a 16 Mx4 bit configuration can be realized.

Further, since only a part of each circuit forming surface portion of the 16MDRAMs 40A, 40B, 40C, and 40D is sealed with resin, it is possible to make the package approximately the same size as the semiconductor chip.

In addition, a part of each of the circuit forming surfaces of the 16MDARMs 40a, 40B, 40C, and 40D is exposed, and a gap is formed between the respective outer leads 3B in a stacked state. By passing through the air, the heat radiation efficiency can be improved.

In addition, since the lead 3 is fixed to each of the circuit forming surfaces of the 16MDRAMs 40A, 40B, 40C, and 40D by the insulating adhesive tape 2, the lead 3 is subjected to mechanical stress and heat mechanical stress. High reliability

In addition, since the leads 3 are also exposed on the circuit forming surfaces of the 16MDRAMs 40A, 40B, 40C, and 40D, the stacked modules can be easily formed by only laminating and adhering the respective leads 3 to each other. I can make it.

In addition, since the laminated bonding surfaces that are bent to the back surfaces of the 16MDRAMs 40A, 40B, 40C, and 40D of the external lead 3B are disposed on approximately the same plane, the efficiency of the laminated bonding and the electrical properties of the laminated bonding surface are arranged. Reliability can be improved.

In addition, as a modification of the fourth embodiment, FIG. 27 shows the configuration of a system of 64MDRAM modules (16777216 words x 32 bits).

It can be easily understood that this 64MDRAM module is also composed of a stacked semiconductor device similarly to the fourth embodiment.

The detailed description is omitted here.

For example, as shown in FIG. 28, the stacked semiconductor device 40 of the fourth embodiment is embedded by bonding a plurality of solders on the embedded substrate 21. As shown in FIG. In this example, the lead pins are arranged twice, but the present invention is also possible in the fourth arrangement.

It goes without saying that the semiconductor devices of the first and second embodiments can be applied to the multilayer modular semiconductor device of the fourth embodiment similarly to the semiconductor device of the third embodiment.

As can be seen from the above, the single body of the semiconductor device of the present invention is effective when applied to a memo device, a microcomputer, a logic device, a gate array device, or the like.

Further, the multilayer module device is effective when applied to a memory card, a memory board, a cache card, or the like.

Example 5

FIG. 29 is a perspective view showing the overall configuration of a small resin-encapsulated semiconductor device according to the fifth embodiment of the present invention, and FIG. 30 is a sectional view of an essential part taken along the line C-C shown in FIG.

29 and 30, the small resin-encapsulated semiconductor device 220 of the fifth embodiment has a lead (not shown) interposed with an insulating adhesive film 202 on the circuit formation surface of the semiconductor chip 201. The 203 is fixed, and the lead 203 and the external terminal (aluminum electrode) 204 of the semiconductor chip 201 are wire-bonded with metal thin wires 205 such as gold wires and electrically connected thereto. The circuit forming surface portion of the semiconductor chip 201 is sealed by a potting method with a liquid resin 206 made of epoxy resin or the like. Thereafter, the outer lead of the lead 203 is bent as shown in FIG. 29 to form a small resin-encapsulated semiconductor device.

The thickness of the semiconductor chip 201 is, for example, 0.2 to 0.5 mm, the thickness of the liquid resin 206 is, for example, 0.25 to 0.6 mm, and the thickness of the lead 203 is, for example, 0.1 to 0.25 mm, insulating adhesive. The thickness of the film 202 is, for example, 25 to 125 µm for the insulating film (substrate) and 10 to 30 µm for the adhesive layer.

The semiconductor chip 201 is, for example, 16 MDRAM or the like, and the lead 203 is made of 42 Ni-Fe material. As shown in FIG. 36, the insulating adhesive film 202 has a multilayer structure of the adhesive layer A, the substrate B, and the adhesive layer A. For example, the insulating adhesive film 202 is made of polyetheramide imide / captone / polyether amide imide. have.

As shown in FIG. 29, the small resin-encapsulated semiconductor device 220 is embedded by attaching the outer lead of the lead 203 to the internal wiring board 207 by soldering 208.

By doing in this way, since the resin which seals in the side part of the semiconductor chip 201 does not exist or exists, since it is a thin layer of the grade which flows at the time of resin potting, it is set as the package of substantially the same dimension as the semiconductor chip 201. Can be. In addition, since there is no resin encapsulated on the back surface of the semiconductor chip 201, the thickness of the package can be reduced to about 0.6 mm.

In addition, as shown in FIG. 31, the heat dissipation efficiency can be further improved by the structure in which the heat dissipation fins 209 are bonded to the back surface of the semiconductor chip 201 with the calorie conductive adhesive 210.

Example 6

32 is a sectional view of an essential part of an ultra-thin resin-encapsulated semiconductor device according to a sixth embodiment of the present invention.

In the ultra-thin resin-encapsulated semiconductor device of the sixth embodiment, as shown in FIG. 32, a gold ball 205A is formed on the A1 electrode of the circuit forming surface of the semiconductor chip 201, and the gold ball 205A The tin-plated inner lead tip of the lead 203 is directly thermocompressed and the lead 203 is fixed through the insulating adhesive film 202. The circuit forming surface portion of the semiconductor chip 201 is sealed by injecting a liquid resin 206 made of epoxy resin or the like by a potting method.

The gold ball 205A is manufactured by a method of removing gold wires other than the ball part after nail head bonding of gold wires.

By doing in this way, since the resin which seals in the side part of the semiconductor chip 201 does not exist or exists, since it is a thin layer of the grade which flows at the time of bonding, it can be set as the package of substantially the same dimension as the semiconductor chip 201. have. In addition, since there is no resin encapsulated on the back surface of the semiconductor chip 201, the thickness of the package can be reduced to about 0.6 mm.

In addition, since the gold ball 205A is formed on the A1 electrode of the circuit formation surface of the semiconductor chip 201, and the tin-plated inner lead end of the lead 203 is directly thermocompressed, the ultra-thin resin An encapsulated semiconductor device is obtained.

As shown in FIG. 33, the compact and ultra-thin resin-encapsulated semiconductor device 230 is embedded in the built-in hole 212 provided in the card substrate 211. As shown in FIG.

Example 7

34 is a cross-sectional view of an essential part of the resin-encapsulated semiconductor device according to the seventh embodiment of the present invention, and FIG. 35 is a plan view showing the relationship between the lead frame and the semiconductor chip of the seventh embodiment.

In the resin-encapsulated semiconductor device of the seventh embodiment, the lead 203 of the resin-encapsulated semiconductor device of the embodiments shown in Figs. 29 and 30 is made very thin (the external lead of the lead can relieve thermal stress). It is designed to relieve thermal stress due to temperature stress in a state in which the package is embedded in the substrate by soldering.

That is, as shown in FIGS. 34 and 35, a very thin lead 301 is fixed to the circuit forming surface of the semiconductor chip 201 with an insulating adhesive film 202 interposed therebetween. The external terminal (aluminum electrode) 204 of the semiconductor chip 201 is wire-bonded with a fine metal wire 205 such as a gold wire and electrically connected thereto.

The circuit forming surface portion of the semiconductor chip 201 is sealed by injecting a liquid resin 206 made of epoxy resin or the like by the potting method.

The outer lead portion of the lead 301 is provided with an insulating adhesive tape 213 for reinforcement.

In FIG. 35, reference numeral 300 denotes a lead frame, 301A denotes an outer lead of the lead 301, and 302 and 303 denote an outer frame of the lead frame.

The thickness of the lead 301 is 20 to 100 µm, for example, the thickness of the insulating adhesive film 202 is 25 to 125 µm for the insulating film (substrate), for example, and 10 to 30 µm for the adhesive layer. The semiconductor chip 201 is, for example, 16MDRAM. The lead 301 is made of, for example, 42Ni-Fe material, and the thickness thereof is, for example, 20 to 150 µm. As shown in FIG. 36, the insulating adhesive film 202 has a multilayer structure composed of an adhesive layer A, a substrate B, and an adhesive layer A. For example, polyether amide imide 25 µm / captone 50 µm / poly Ether amide imide is 25 micrometers. As shown in FIG. 37, the insulating adhesive tape 213 for reinforcement has a multilayer structure consisting of an adhesive layer A and a substrate B. For example, polyether amide imide 25 µm / captone 50 µm. .

In addition, another polyimide film may be used instead of the Kapton.

Next, the assembling process of the resin-encapsulated semiconductor device of this embodiment will be described according to the flowchart shown in FIG.

First, patterning of the lead frame 300 is first performed by etching or pressing (step 401). Next, as shown in FIG. 35, an insulating adhesive film (adhesive layer / substrate / adhesive layer) is applied to the paralleled lead frame 300 under conditions of 300 to 400 ° C., 10 to 100 kg / cm 2, and 3 to 10 seconds. 202 and an insulating adhesive tape (adhesive layer / substrate) 213 for reinforcement are attached (steps 402 and 403).

Next, the semiconductor chip 201 is fixed to the lead frame 300 under conditions of 300 to 400 ° C., 10 to 100 kg / cm 2, and 3 to 10 seconds (step 404).

Next, the wire bonding is performed by a thermocompression method in which a gold wire 205 having a diameter of 30 µm is combined with ultrasonic vibration at a temperature of 200 ° C (step 405).

Next, the semiconductor chip 201 pots and seals the resin 206 which becomes a liquid epoxy resin on the circuit formation surface (step 406). This is heated at 180 ° C. for 1 hour and then cured by heating at 150 ° C. for 5 hours (step 407).

Next, the outer frame 302 of the lead frame 300 is cut (step 408). Aging / selection (step 409) is carried out (step 410).

Then, the user molds the outer lead 301A of the lead 301 into the required shape, cuts the insulating adhesive tape (adhesive layer / substrate) 213 and the outer frame 303 for reinforcement and solders it to the internal wiring board. To be built.

By thinning the lead 301 in this way, the thermal stress at the time of soldering and embedding the semiconductor device in the substrate can be alleviated, and the thermal stress due to the temperature stress in the state where the semiconductor device is embedded in the substrate can be alleviated. Can be.

In addition, since the assembly, sorting, and shipping can be performed while the insulating adhesive tape 213 for reinforcement is attached, deformation or damage of the lead or the like can be prevented.

Also, as shown in FIG. 39, in order to relieve thermal stress when soldering and embedding the semiconductor device in a substrate, and to relieve thermal stress due to temperature stress while the semiconductor device is embedded in the substrate, The outer lead 301A of 301 may be bent to give elasticity.

Example 8

40 is a sectional view of principal parts of the resin-encapsulated semiconductor device according to the eighth embodiment of the present invention.

As shown in FIG. 40, the resin-encapsulated semiconductor device according to the eighth embodiment uses a resin-molded powder comprising epoxy resin or the like up to the circuit forming surface portion and the side surface portion of the semiconductor chip 201 according to the fifth embodiment. It is sealed by the transfer mold method. 214 is a part sealed with resin.

By doing in this way, the shape of the part 214 sealed with resin can be made constant, and reliability can be improved.

As mentioned above, although this invention was concretely demonstrated according to the Example, this invention is not limited to the said Example, Of course, it can change in various ways in the range which does not deviate from the summary.

The effects obtained by the representative of the inventions disclosed herein are briefly described as follows.

(1) The package can have dimensions of approximately the same size as the semiconductor chip.

(2) The heat radiation efficiency can be improved.

(3) A semiconductor device having high reliability against mechanical stress and mechanical stress due to heat can be provided.

(4) The stacked semiconductor device can be easily manufactured.

(5) A conventional lead frame made by a press or etching method can be used, and the cost can be reduced.

(6) The internal density can be improved.

(7) Since only the circuit formation surface portion or the circuit formation surface portion and the side surface portion of the semiconductor chip are sealed with resin, the package can be made approximately the same size as the semiconductor chip. Moreover, since the surface opposite to the circuit formation surface part of a semiconductor chip is exposed, the thickness of the whole package can be made thin and heat dissipation efficiency can be improved.

(8) Since the outer lead portion of the lead has a shape suitable for thinning in in-plane mounting, an ultra-thin package can be obtained.

(9) Since the outer lead of the lead is configured to relieve thermal stress, the thermal stress when soldering the semiconductor device to the substrate can be alleviated, and the semiconductor device is embedded in the substrate. It can alleviate the thermal stress caused by temperature stress.

(10) Since the electrical connection between the lead and the external terminal of the semiconductor chip is made of a wire, a metal ball, or a metal bump, a conventional lead frame made by a press or an etching method can be used, and the cost can be reduced.

Claims (39)

A semiconductor chip having a plurality of external terminals on its main surface, an encapsulation material covering the main surface of the semiconductor chip, and a plurality of leads each having a first portion inside the encapsulation material and a second portion exposed from the encapsulation material. And a plurality of leads whose corresponding leads are electrically connected to the plurality of external terminals, and wherein a second portion of the lead electrically connected to the plurality of external terminals is located on the main surface of the semiconductor chip. Device. The semiconductor device according to claim 1, wherein the entirety of the second portion of the plurality of leads is located on the main surface of the semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor chip has a rectangular shape, and the plurality of external terminals are arranged in a direction substantially parallel to a pair of long sides of the semiconductor chip. 4. The semiconductor device according to claim 3, wherein the plurality of external terminals are arranged at approximately the center of the pair of long sides. The semiconductor device according to claim 4, wherein the plurality of external terminals are two rows. The semiconductor device according to claim 1, further comprising a heat dissipation fin, wherein said heat dissipation fin is formed on the back surface of said semiconductor chip. The semiconductor device according to claim 1, wherein said encapsulation material is resin. The semiconductor device according to claim 1, wherein the second portion of the plurality of leads is a portion connected to the substrate by soldering. The semiconductor device according to claim 1, wherein the first portion of the plurality of leads and the plurality of external terminals are connected by wire bonding. The semiconductor chip of claim 1, further comprising an adhesive insulating film between the first portion of the plurality of leads and a main surface of the semiconductor chip, wherein the plurality of leads are fixed to the main surface of the semiconductor chip by the adhesive insulating film. A semiconductor device characterized by the above-mentioned. A semiconductor chip having a plurality of external terminals on a main surface thereof, an encapsulation material covering the main surface of the semiconductor chip, a plurality of leads each having a first portion inside the encapsulation material and a second portion exposed from the encapsulation material; A plurality of wires electrically connecting the plurality of external terminals and corresponding leads, wherein a second portion of the lead electrically connected to the plurality of external terminals is located on a main surface of the semiconductor chip, and a main surface of the semiconductor chip Wherein the height up to the second portion of the plurality of leads is higher than the height from the main surface of the semiconductor chip to the apex of the loop of the plurality of wires. A semiconductor chip having a plurality of external terminals on its main surface, an encapsulation material covering the main surface of the semiconductor chip, and a plurality of leads each having a first portion inside the encapsulation material and a second portion exposed from the encapsulation material. And a plurality of leads whose corresponding leads are electrically connected to the plurality of external terminals, wherein a second portion of the lead electrically connected to the plurality of external terminals is located on the main surface of the semiconductor chip, and the main surface of the semiconductor chip. And the height of the encapsulation material from the semiconductor device is lower than the height from the main surface of the semiconductor chip to the second portions of the plurality of leads. A semiconductor chip having a plurality of external terminals on its main surface, an encapsulation material covering the main surface of the semiconductor chip, and a plurality of leads each having a first portion inside the encapsulation material and a second portion exposed from the encapsulation material. And a plurality of leads having corresponding leads electrically connected to the plurality of external terminals, wherein a second portion of the lead electrically connected to the plurality of external terminals is located on a main surface of the semiconductor chip, and the plurality of external terminals. And the plurality of leads electrically connected to the plurality of leads extending toward the sides of the semiconductor chip in the vicinity of the plurality of external terminals. The semiconductor device according to claim 13, wherein the semiconductor chip has a rectangular shape, and the plurality of leads electrically connected to the plurality of external terminals extends the semiconductor chip toward a pair of long sides. The semiconductor device according to claim 13, wherein the entire second portion of the plurality of leads is located on a main surface of the semiconductor chip. A rectangular semiconductor chip having a plurality of external terminals on a main surface thereof, wherein the plurality of external terminals are arranged in a direction substantially parallel to a pair of long sides of the semiconductor chip and are arranged in a substantially center of the pair of long sides. A plurality of leads each having a chip, an encapsulation material covering the main surface of the semiconductor chip, and a first portion inside the encapsulation material and a second portion exposed from the encapsulation material, the corresponding leads being the plurality of external terminals. A second portion of the lead electrically connected to the plurality of external terminals is located on a main surface of the semiconductor chip, and the plurality of leads are arranged in the vicinity of the plurality of external terminals. The pair of long sides in the vicinity of the first lead group and the plurality of external terminals extending to one side of the long sides of And a second lead group extending to the other side of the semiconductor device. 17. The semiconductor device according to claim 16, further comprising a memory cell array formed on a main surface of said semiconductor chip, said memory cell array being formed on a main surface of said semiconductor chip on both sides of said plurality of external terminals. 17. The semiconductor device according to claim 16, wherein the entire second portion of the plurality of leads is located on a main surface of the semiconductor chip. A semiconductor device for stacking at least two semiconductor devices up and down, wherein one of the semiconductor devices has a rectangular main surface on which a plurality of external terminals are formed, a rear surface facing the main surface, and a side surface formed between the main surface and the rear surface. A semiconductor chip, an encapsulation member encapsulating a main surface of the semiconductor chip, electrically connected to each of the external terminals and connected to the interior on the main surface of the semiconductor chip and the interior of the encapsulation member. A first lead portion extending in a direction away from the chip, a second lead portion extending in a direction substantially parallel to the side surface of the semiconductor chip from the first lead portion, and the semiconductor in the second lead portion It consists of the outside which has each the 3rd lead part extended and formed in the back surface of a chip | tip. Is a semiconductor device having a plurality of leads, wherein the first lead portion is exposed from the encapsulation member on a main surface of the semiconductor chip, and the third lead portion has an electrical connection portion at a portion located on the back surface of the semiconductor chip. A semiconductor device, characterized in that. 20. The semiconductor device according to claim 19, wherein the semiconductor chip further has an insulating adhesive film fixing the inside to the main surface of the chip between the main surface and the inside. 20. The semiconductor device according to claim 19, wherein the external terminal is located at the center of the rectangular main surface of the semiconductor chip and is disposed along the side of the rectangular main surface. 20. The semiconductor device according to claim 19, wherein said external terminal and said interior are timely connected by bonding wires, respectively. Providing a semiconductor chip having a main surface having a plurality of external terminals formed thereon, the lead frame having a plurality of leads each comprising a first portion and a second portion connected to the first portion, the lead frame being the second portion Arranging the semiconductor chip so as to be positioned on a main surface of the semiconductor chip; electrically connecting one of the plurality of external terminals and a first portion of the lead corresponding thereto; and a first portion of the chip main surface and the lead. And sealing the resin so that the second portion of the lead is exposed. 24. The method of claim 23, further comprising, after the encapsulation step, separating the second part from the lead frame such that the entirety of the second part is located on the main surface of the semiconductor chip. Way. 24. The method of manufacturing a semiconductor device according to claim 23, wherein said external terminal is electrically connected to said first portion of said lead by a bonding wire. 26. The method of claim 25, wherein the bonding wire is formed such that the peak height of the wire on the main surface of the chip is lower than the height from the main surface of the chip to the second portion of the lead. 25. The method of manufacturing a semiconductor device according to claim 24, wherein the resin is encapsulated by a transfer molding method in the encapsulation step. 28. The method of manufacturing a semiconductor device according to claim 27, wherein the resin is encapsulated so that the height of the resin from the main surface of the chip is lower than the height from the main surface of the chip to the second portion of the lead. 28. The method of manufacturing a semiconductor device according to claim 27, wherein the semiconductor chip has a rear surface facing the main surface and a side surface between the main surface and the rear surface, and the side surface is sealed by resin in the resin encapsulation step. . 24. The method of manufacturing a semiconductor device according to claim 23, further comprising a step of fixing the first portion of the lead and the semiconductor chip by an insulating adhesive film before the step of electrically connecting. The semiconductor device according to claim 11, wherein the second portion of the plurality of leads is a portion connected to the substrate by soldering. The semiconductor device according to claim 12, wherein the second portion of the plurality of leads is a portion connected to the substrate by soldering. The semiconductor device according to claim 13, wherein the second portion of the plurality of leads is a portion connected to the substrate by soldering. The semiconductor device according to claim 16, wherein the second portion of the plurality of leads is a portion connected to the substrate by soldering. 24. The method of manufacturing a semiconductor device according to claim 23, wherein the second portion of the plurality of leads is a portion connected to the substrate by soldering. A semiconductor chip having a plurality of wiring layers on its main surface and a semiconductor package mounted on the main surface of the mounting substrate, the semiconductor package having a semiconductor chip having an integrated circuit and a plurality of external terminals on the main surface thereof, A plurality of leads each having an encapsulation material covering a main surface and a first portion disposed inside the encapsulation material and a second portion exposed from the encapsulation material, the lead being electrically connected to a corresponding external terminal of the plurality of external terminals. And a second portion of the lead electrically connected to the plurality of external terminals, the second portion of which is located on a main surface of the semiconductor chip and connected to a plurality of wiring layers of the mounting substrate. . The semiconductor device according to claim 36, wherein a second portion of the lead electrically connected to the plurality of external terminals is connected to the plurality of wiring layers of the mounting substrate by a solder layer. A mounting substrate having a plurality of wiring layers on its main surface and a first semiconductor package and a second semiconductor package mounted on the main surface of the mounting substrate, each of the first and second semiconductor packages being an integrated circuit and a plurality of; A semiconductor main body having a rectangular main surface having an outer terminal formed thereon, a rear surface facing the main surface and a side surface formed between the main surface and the rear surface, an encapsulation member covering the main surface of the semiconductor chip, and the plurality of external terminals electrically A first lead portion connected to the inside and extending in a direction away from the semiconductor chip on the main surface of the semiconductor chip and inside the sealing member; A second portion extending from one portion and the first lead portion in a direction substantially parallel to the side surface of the semiconductor chip And a plurality of leads formed outside of the lead portion and the third lead portion extending from the second lead portion to the rear surface of the semiconductor chip, and the third lead portion of the plurality of leads of the first semiconductor package. Connected to a plurality of wiring layers of the mounting substrate, the second semiconductor package is stacked on the first semiconductor package, and the third lead portion of the plurality of leads of the second semiconductor package corresponds to the first semiconductor. A semiconductor device characterized by being connected to a first lead portion of several leads of a package. 39. The semiconductor device of claim 38, wherein each of the third lead portion of the first semiconductor package and the plurality of wiring layers of the mounting substrate, the third lead of the second semiconductor package and the first lead portion of the first semiconductor package are respectively A semiconductor device, which is connected to each other by a solder layer.