KR100209704B1 - Method for forming wiring of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wiring forming method of a semiconductor device, and more particularly to a wiring forming method of a semiconductor device which flattens a gap between lower wirings in a narrow space.

A method for forming a wiring of a semiconductor device of the present invention includes forming a plurality of lower conductive layers on a semiconductor substrate, a dummy layer formed between the plurality of lower conductive layers, And forming conductive line extension layers at the same time.

Description

Method for forming wiring of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wiring forming method of a semiconductor device, and more particularly to a wiring forming method of a semiconductor device which flattens a gap between lower wirings in a narrow space.

Hereinafter, a wiring forming method of a semiconductor device according to the related art will be described with reference to the accompanying drawings.

FIG. 1 is a wiring layout view of a semiconductor device according to the related art.

As in FIG. 1, a plurality of lower conductor wires 12a are formed in one direction with a gap on the semiconductor substrate.

A dummy layer 12b is formed between the lower conductor wires 12a in the direction parallel to the lower conductor wires 12a and the same material as the lower conductor wires 12a.

The insulating layer 13 is formed on the entire surface including the lower conductive wire 12a and the dummy layer 12b thus formed.

FIG. 2 is a process sectional view taken along the line X-X 'in FIG. 1.

As shown in FIG. 2, a conductive layer and a photoresist layer are sequentially formed on a semiconductor substrate 11, and the photoresist layer is selectively exposed and developed such that only portions where a lower conductive line and a dummy layer are to be formed are left, A plurality of lower conductive wires 12a and a plurality of dummy layers 12b are formed by using the photoresist film as a mask to dry the conductive layer, and then the photosensitive film is removed. Next, an insulating layer 13 is formed on the entire surface including the lower conductive wire 12a and the dummy layer 12b.

Here, the dummy layer 12b is formed below the upper conductive line, which is not electrically connected to the lower conductive line 12a, and the upper conductive line to be formed in the subsequent process.

There has been a problem that it is difficult to limit the interval between the lower wirings when the space between the lower wirings is narrow to form the dummy layer.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a wiring forming method of a semiconductor device for forming a dummy layer and forming a lower wiring having a narrower width in a narrow place, .

FIG. 1 is a wiring layout diagram of a semiconductor device according to a related art. FIG.

FIG. 2 is a process sectional view taken along the line X-X 'in FIG. 1; FIG.

FIG. 3 is a wiring layout diagram of a semiconductor device according to an embodiment of the present invention; FIG.

4 is a process sectional view taken along the line X-X 'in FIG. 3;

DESCRIPTION OF THE REFERENCE NUMERALS

31: semiconductor substrate 32a: lower conductor wire

32b: a dummy layer 32c: a lower conductor extension layer

33: Insulating layer

A method of forming a wiring of a semiconductor device according to the present invention includes forming a plurality of lower conductive layers on a semiconductor substrate, a dummy layer formed between the plurality of lower conductive layers, and a lower conductive wire And forming the extension layers at the same time.

A preferred embodiment of a method for forming a wiring of a semiconductor device according to the present invention will now be described in detail with reference to the accompanying drawings.

3 is a wiring layout diagram of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 3, a plurality of lower conductor wires 32a are formed on the semiconductor substrate with a gap therebetween in one direction. A dummy layer 32b, which is the same material as the lower conductor 32a, is formed between the lower conductor wires 32a in a direction parallel to the lower conductor wire 32a. In addition, a plurality of lower wire extension layers 32c are formed in a space in which the dummy layer 32b is not formed due to a narrow gap between the lower die wire 32a and the lower die wire 32a.

The insulating layer 33 is formed on the entire surface including the lower conductive wire 32a, the dummy layer 32b, and the lower conductive wire extending layer 32c.

4 is a process sectional view taken along the line X-X 'in FIG. 3;

As shown in FIG. 4, a conductive layer and a photoresist layer are sequentially formed on a semiconductor substrate 31, and the photoresist layer is selectively exposed and developed such that only portions where a lower conductive line extension layer, a lower conductive line and a dummy layer are to be formed, The conductive layer is etched using the selectively exposed and developed photoresist as a mask to etch the conductive layers to form a plurality of lower conductive lines 32a, a plurality of dummy layers 32b, and a plurality of lower conductive lines 32a. A space which is too narrow and is not formed by the dummy layer 32b is formed in the lower portion of the lower wire 32a so that the distance between the lower wire 32a and the lower wire 32a is 3 to 10 times larger than the size of the Feaure, The conductive line extension layer 32c is simultaneously formed, and then the photosensitive film is removed. Next, an insulating layer 33 is formed on the entire surface including the lower conductor 32a, the dummy layer 32b, and the lower conductor extension layer 32c.

Here, the dummy layer 32b is formed on the lower side of the electric wire, which is not electrically connected to the upper electric wire and the lower electric wire 32a to be formed in a post process, and is connected to an electrically stable terminal such as Vcc or Vss Do not electrically float.

In addition, the insulating layer 33 is formed flat by the dummy layer 32b, the lower conductive extension layer 33c and the lower conductive line 32a, thereby facilitating the patterning of the upper wiring as a subsequent process .

The method of forming a wiring of a semiconductor device of the present invention has an effect of forming a dummy layer and a lower wiring extension layer having a wider width so as to define a space between lower wirings, have.

Claims (4)

Forming a plurality of lower conductive layers on the semiconductor substrate, a dummy layer formed between the plurality of lower conductive layers, and a lower conductive extension layer formed in a narrow space to form the dummy layer, Wherein the wiring is formed on the semiconductor substrate. The method according to claim 1, wherein the lower conductive layer and the dummy layer are made of the same material. The method according to claim 1, wherein the interval between the lower wirings is limited to three times to ten times the size of the feature. The method of claim 1, wherein the dummy layer is not electrically floated.