KR100208183B1 - Apparatus for d-channel switching in s pbx - Google Patents

Abstract

The present invention relates to a D-channel switching device of a digital simplified switching system, wherein the 8-bit data shifted by a multiplexed line clock is stored during a designated time slot so that a D-channel signal can be exchanged in a digital simplified switching system. Four 2-bit registers 221 which respectively export two-bit data inputted in parallel by the first register 210 and the register 210 which export four data in parallel to the digital transceivers 300 by the data clock. The two-bit data inputted in parallel by four two-bit registers 240 and four two-bit registers 240 that store and export two bits of data shifted by the clock in parallel to the multiplexed line by the multiplexed line clock. The register 230 is configured to export bit data serially.

Description

D channel exchange device of digital simple exchange system

1 is an overall block diagram of the present invention.

2 is a detailed block diagram of a digital signal exchange of the present invention.

3 is an output waveform diagram of each part of the present invention.

* Explanation of symbols for main parts of the drawings

100: time slot generation unit 200: digital signal exchange unit

210,220: register 221 228: 2-bit register

300: digital transceiver 400: CPU

The present invention relates to a digital simple switching system, and more particularly to a D-channel switching device of the switching system.

Conventionally, in the digital simplified switching system, each time slot has to be made separately for each channel signal.

Therefore, if there are a large number of signals in each channel, the number of tie slots must also be large, resulting in a complicated system configuration and a decrease in operating efficiency.

Therefore, the present invention was devised to solve the above-mentioned conventional problems, and an object of the present invention is to provide a D-channel digital exchange system that can be used by sharing timeslots by tying four D-channel signals into one to exchange signals. In providing a channel exchange device.

Preferred embodiments for achieving the object of the present invention described above in detail by the accompanying drawings as follows.

FIG. 1 is a block diagram of hardware functions according to the present invention. The time slot generator 100 receives a multiplexed line clock 1 and writes a desired time slot. The multiplexed line clock 1 and the time slot generator are shown in FIG. A digital signal exchanger 200 capable of multiplexing and demultiplexing a digital signal by receiving the time slot signal 2 and the frame clock 3 of the apparatus 100 is configured, and the digital signal exchanger 200 and data ( 4) (5) is composed of a digital transceiver unit 300 consisting of four digital transceivers.

The CPU 400 is connected to the timeslot generator 100, and the digital signal exchanger 200 emits a transmission signal TX and receives a reception signal RX.

FIG. 2 is a detailed block diagram of the digital signal exchanger 200 according to the present invention. The first register 210 stores 8-bit data shifted by the multiplexed line clock 1 and outputs 4 2-bit data in parallel. ) And first to fourth two-bit registers 221 outputting two-bit data 5 input in parallel by the register 210 to the digital transceiver unit 300 by the data clock 6. 224 is configured and includes fifth to eighth two-bit registers 225 which are input in parallel to store the two-bit data 4 shifted by the data clock 6. 228 is configured, and the fifth to eighth two-bit registers 225 A second register 230 is configured to collect data 4 input in parallel by 228, and output multiplexed 8-bit data serially by the multiplexed line clock 1.

Hereinafter, with reference to FIG. 3, which is an output waveform diagram of the present invention, their operation and effect will be described.

When the transmission speed of the multiplexed line is 384KB, when the waveform (a) of FIG. 3 and the multiplexed line clock 1 come in, the frame clock 3 of the time slot generator 106 has a clock cycle like the (b) waveform. 125 The number of timeslots of one frame is composed of six, each of six different waveforms (c print h).

However, if the transmission rate of the multiplexed line is 4096KB, the period of the frame clock 3 is 125 The number of timeslots is increased to 64.

In this case, the D channel transmission rate is 16KB for the data clock i, and the B channel transmission rate is 64KB.

The channel is 125 8 bits of data must be delivered within the D channel, and 2 bits of data must be delivered.

At this time, in order to facilitate control by the CPU 400, data exchange is performed by grouping four D-channels on the basis of the B-channel to exchange data with a multiplexed line.

First, when the D channel signal is loaded on the multiplexed line, the four D channel signals to be sent when the output of the digital transceiver unit 300 is loaded on the multiplexed line are first generated by the data clock 6 during one frame. Two bits of data 4 are stored in the fifth to eighth registers 225. 228, and the four received 2-bit data are latched as 8-bit data in the second register 230 at the next frame clock (b waveform) rising edge as shown in FIG.

At this time, the second register 230 multiplexes the data according to the clock (a waveform) of the multiplexing line 1 during the designated timeslot of the next frame generated by the timeslot generator 100 as shown in FIG. Output to line (1).

Secondly, when the D channel signal is extracted from the multiplexing line 1, the multiplexed signal is first generated during the designated timeslot of the timeslots generated by the timeslot generator 100 of one frame as shown in FIG. 8 bits of data are received while being shifted in accordance with the clock 1 (a waveform) of the multiplexed line to one register 210, and then 8 bits of data of the first register 210 at the rising edge of the next frame clock (b waveform). Is the first to fourth registers 221 as 2-bit data 5. 224, and the 2-bit data 5 are output to the digital transceiver section 300 connected to each of them in accordance with the data clock 6 (i waveform) during the next frame.

On the other hand, the B channel clock as shown in (j) waveform of FIG. 8 bits of data must be transferred in this case, and the D channel signal (i waveform) needs 2 bits of data.

As described above, the present invention can use the same time slot as the B channel signal by tying four D channel signals and exchanging signals, thereby improving system operation efficiency because a separate time slot is not required for the D channel signal. It has an excellent effect of easy CPU control.

Claims (1)

The first register 210 stores 8-bit data shifted by the multiplexed line clock 1 and outputs 4 2-bit data in parallel during a designated timeslot in order to enable the digital simplified switching system to exchange signals of the D channel. ) And first to fourth 2-bit registers 221 for outputting 2-bit data input in parallel by the first register to the digital transceiver unit 300 by the data clock 6. 224 and fifth to eighth two-bit registers 225 for storing and outputting two-bit data shifted by the data clock in parallel. 228) and a second register 230 for serially outputting 2-bit data input in parallel by the 2-bit registers as 8-bit data on the multiplexing line by the multiplexing line clock. D-channel exchange device of simple exchange system.