KR100207786B1 - Sampling clock generation circuit for a video tape recorder - Google Patents

Abstract

It is necessary to transmit program information data within a vertical blanking interval such as a Korean Brocasting Program System (KBPS), teletext, and caption, and to transmit program information data for detecting program information data among transmitted broadcast signals And a sampling clock generating circuit for generating a clock. In order to detect the program information data more stably and accurately, a sampling clock which is synchronized with both the horizontal synchronizing signal and the CRI pulse signal must be generated. A voltage controlled oscillator for correcting the phase of the sampling clock according to the frequency control voltage to generate the sampling clock synchronized with the horizontal synchronizing signal; A phase comparator for comparing a phase difference between the CRI pulse signal and the sampling clock as the data recognition signal is switched to a predetermined level; And a low-pass filter for converting the phase difference compared through the phase comparator to the frequency control voltage of a DC component having a predetermined level and outputting the frequency control voltage to the voltage controlled oscillator.

Description

Sampling clock generating circuit of a video tape recorder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock generation circuit of a video tape recorder (hereinafter abbreviated as 'VTR'), and more particularly to a sampling clock generating circuit of a Korean Broadcasting Program System (KBPS) And generates a sampling clock synchronized with both the horizontal synchronizing signal and the CRI pulse signal in order to more stably and accurately separate the program information data Data from the broadcast signal transmitted along with the sampling clock.

Generally, the Korean type reservation recording method refers to a method of transmitting program information data indicating a broadcasting sequence on the same day by connecting to a 16th horizontal synchronizing signal of one field of broadcasting signals for forming one screen. In this way, the user can more conveniently select the scheduled recording. When the broadcasting station sequentially transmits various program information data indicating the broadcasting order of each broadcasting station on the date, the VTR receives and stores the program information data And sequentially display the stored program information data. The Korean type reservation recording method includes various functions in addition to a sort function capable of sorting and selecting a desired broadcast program. Therefore, compared to the G-code reserved recording method in which a designated code number is searched and a corresponding code number is input, It can be said to be a reserved recording method.

For example, if a user simultaneously selects a sports program and a sort function to select a sports program to be broadcast on the same day, the sports program broadcasted on the same day is sequentially displayed for each broadcasting station or each broadcasting time. When a user moves a cursor to a program to be scheduled to be recorded, the broadcast start time and end time of the program and the broadcast station name are automatically stored in the memory of the VTR. Tuning the broadcast channel and automatically recording the corresponding broadcast content.

FIG. 1 shows the format of a reserved recording broadcast signal according to the Korean reservation recording scheme. As shown in FIG. 1, the Korean reserved recording scheme transmits program information data of a CRI (Clock Run In) pulse and 2 bytes in succession to the 16th horizontal synchronization signal. This CRI pulse signal indicates that program information data is included in the currently transmitted and received broadcast signals, and the VTR detects this CRI pulse signal and prepares to store the program information data on a storage medium.

However, in order to separate the program information data according to the Korean type reserved recording scheme from the broadcast signal, a typical VTR must generate a sampling clock synchronized with the 16th horizontal sync signal of the broadcast signal received by the VTR. A conventional sampling clock generation circuit for generating such a sampling clock is shown in FIG.

2, a phase comparator 1 for comparing phases of a horizontal synchronizing signal H-sync (here, the 16th horizontal synchronizing signal corresponds) and a divided horizontal frequency signal f _H among the broadcast signals received by the VTR A low pass filter 2 for converting the result of the comparison by the phase comparator 1 into a DC voltage and a low pass filter 2 receiving a DC voltage output from the low pass filter 2, A voltage controlled oscillator 3 for oscillating a variable oscillation frequency and a frequency divider 4 for dividing the oscillation frequency oscillated from the voltage controlled oscillator 3 into a horizontal frequency signal f _H.

The operation of the conventional sampling clock generating circuit having the above-described configuration is as follows.

A horizontal synchronizing signal (H-sync) among the broadcast signals received by the VTR is applied to the phase comparator 1. [ The phase comparator 1 compares the phase difference between the externally applied horizontal synchronizing signal H-sync and the horizontal synchronizing frequency f _H applied from the frequency divider 4 and is initially applied from the frequency divider 4 Since there is no horizontal synchronizing frequency (f _H ), there is no phase difference compared in the phase comparator (1). Therefore, the low-pass filter 2 outputs the DC voltage at the ground level to the voltage-controlled oscillator 3 since the phase difference output from the phase comparator 1 does not exist.

The voltage-controlled oscillator 3 receives a ground level DC voltage applied from the low-pass filter 2 and oscillates at an oscillation frequency of 503.5 kHz. The oscillation frequency of 503.5 kHz oscillated in this way is divided by the frequency divider 4 to 1/32 speed (15.734 kHz), and the divided horizontal synchronizing frequency f _H is outputted to the phase comparator 1. [

The phase comparator 1 then compares the phase difference between the horizontal synchronization signal H-sync and the horizontal synchronization frequency f _H output from the frequency divider 4 and outputs the compared result to a low-pass filter 2). The low-pass filter 2 converts the DC voltage value to a DC voltage value having a predetermined voltage level according to the phase difference output from the phase comparator 1, and outputs the DC voltage value to the voltage-controlled oscillator 3. The voltage-controlled oscillator 3 outputs a new oscillation frequency whose predetermined speed is varied from an oscillation frequency of 503.5 kHz set in accordance with the direct-current voltage value output from the low-pass filter 2. The new oscillation frequency thus output is finally output as a sampling clock. Therefore, among the received broadcast signals, a sampling clock synchronized with the horizontal synchronizing signal (H-sync) is generated (see FIG. 3).

The conventional sampling clock generation circuit as described above generates a sampling clock synchronized with the horizontal synchronization signal H-sync among the received broadcast signals and detects the program information data using the generated sampling clock If the frequency band of the CRI pulse signal is variable even if the sampling clock is synchronized with the horizontal synchronizing signal H-sync, a predetermined frequency band for detecting the program information data using the sampling clock is not synchronized with the program information data And the like. In this case, the program information data may not be accurately detected, which may cause an error in the reservation recording process by the Korean reservation recording method.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a sampling clock generating circuit of a VTR capable of more accurately detecting program information data transmitted by a Korean reservation recording method.

Another object of the present invention is to synchronize both the synchronization signal (H-sync) and the CRI pulse signal among the received broadcast signals in order to accurately detect the program information data from the format of the reserved recording broadcast signal transmitted by the Korean reservation recording method And a sampling clock generating circuit of the VTR for generating a sampling clock.

1 is a diagram showing a format of a reserved recording broadcast signal transmitted according to a Korean reservation recording scheme,

2 is a schematic block diagram showing a conventional sampling clock generating circuit,

3 is a sampling clock waveform generated by a conventional sampling clock generating circuit,

4 is a schematic block diagram showing a sampling clock generating circuit of the VTR according to the present invention,

FIG. 5 is a detailed circuit diagram of the voltage-controlled oscillator shown in FIG. 4,

FIG. 6 is a detailed circuit diagram of the phase comparator shown in FIG. 4,

7 is a waveform diagram for the main part of Fig.

Description of reference numerals used in the main parts of the drawings

5: Voltage controlled oscillator 6: Phase comparator

7: Low-pass filter 8: NAND gate

9: constant current source 10: switching element

11, 12: Differential amplifier

According to an aspect of the present invention, there is provided a method for transmitting program information, including the steps of transmitting predetermined program information data in a vertical blanking interval, receiving the transmitted broadcast signal, and detecting the program information data included in the received broadcast signal The apparatus of claim 1, wherein the sampling clock is synchronized with the horizontal synchronizing signal to generate a sampling clock synchronized with the horizontal synchronizing signal, Controlled oscillator; Receiving the sampling clock output from the voltage control oscillator and a data recognition signal included in the received broadcast signal and indicating a CRI pulse signal indicating that the program information data is included and a CRI pulse signal interval, A phase comparator for comparing a phase difference between the CRI pulse signal and a sampling clock output from the voltage controlled oscillator as the level of the CRI pulse signal is switched to a predetermined level; And a low pass filter for converting the phase difference compared through the phase comparator to the frequency control voltage of a DC component having a predetermined level and outputting the frequency control voltage to the voltage controlled oscillator.

According to an aspect of the present invention, in the voltage controlled oscillator, the capacitance is varied in accordance with the frequency control voltage supplied from the low-pass filter, and the horizontal synchronizing frequency output from the voltage controlled oscillator is adjusted A variable capacitance element; And a logic element for simultaneously receiving a horizontal synchronizing signal whose frequency is adjusted by the variable capacitance element and a horizontal synchronizing signal included in the received broadcast signal and performing a logical operation to output a sampling clock synchronized with the horizontal synchronizing signal .

It is preferable that the logic element is a NAND gate.

The phase comparator may further comprise: a constant current source for generating a constant current; Phase comparing means comprising a plurality of differential amplifiers and mirror transistors for comparing the phase difference between the CRI pulse signal and the sampling clock; And a switching element for switching the supply of the constant current generated from the constant current source to the phase comparison means according to the voltage level of the data recognition signal.

Hereinafter, preferred embodiments of a sampling clock generating circuit of a VTR according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a schematic block diagram showing a sampling clock generating circuit of the VTR according to the present invention.

4, a voltage-controlled oscillator (H-sync) receiving a 16-th horizontal sync signal (H-sync) and a frequency control voltage of a broadcast signal received by the VTR and generating a sampling clock synchronized with a horizontal sync signal 5, a sampling clock output from the voltage-controlled oscillator 5 and a data recognition signal indicating a frequency band of a CRI pulse signal and a CRI pulse signal among the broadcast signals received in the VTR, A phase comparator 6 for comparing the phase difference between the CRI pulse signal included in the broadcast signal received in the state of the digital broadcast signal and the sampling clock and a phase comparator 6 for comparing the frequency control voltage And a low-pass filter 7 that converts the signal to a voltage-controlled oscillator 5 described above.

The voltage-controlled oscillator 5 will now be described in detail with reference to FIG.

The output terminal of the low-pass filter 7 is connected between a pair of capacitors C1 and C2 connected in series so that the capacitance is varied according to the frequency control voltage supplied from the low-pass filter 7, The reactor L is connected in parallel to the capacitor C1 and the variable capacitor C2 and the capacitor C3 to determine the oscillation frequency of the oscillator 5. [ A NAND gate (not shown) for receiving a horizontal synchronizing signal (H-sync) of the received broadcast signal and a horizontal synchronizing frequency phase-adjusted by the frequency control voltage outputted from the low-pass filter (7) (8). Here, the reference symbol R1 is a resistor.

The phase comparator 6 will now be described in detail with reference to FIG.

The phase comparator 6 shown in Fig. 6 includes a switching element 10 for switching a constant current supplied from the current source 9 according to a data recognition signal, and a switching element 10 for generating a predetermined clock in response to the applied CRI pulse signal A first differential amplifier 11, a second differential amplifier 12 receiving a sampling clock and generating a predetermined clock, and a driving voltage Vcc applied from a constant voltage source (not shown) And a plurality of mirror transistor groups 13 for finally outputting a current corresponding to a phase difference between a clock generated in the first differential amplifier 11 and a clock generated in the second differential amplifier 12. Here, the above-described phase comparator 6 shows the structure of a known conventional differential amplifier, and thus a detailed description thereof will be omitted.

The operation of the present invention having the above-described configuration will be described with reference to FIG.

The oscillation frequency oscillated from the voltage controlled oscillator is expressed by Equation 1 below.

[Equation 1]

Here, C is set in the following equation (2).

&Quot; (2) "

First, when the received broadcast signal is in the horizontal synchronization signal H-sync period (when the logic low signal is in the logic low state), the output of the NAND gate 8 remains in a logic high state, .

Thereafter, when the horizontal synchronization signal H-sync is inverted to a logic 'high' state, an oscillation feed-back loop is formed to perform an oscillation operation, (1) and (2). At this time, the electrostatic capacity of the variable capacitor C2 is varied according to the frequency control voltage output from the low-pass filter 7, whereby the output (variable oscillation frequency) of the NAND gate 5 is supplied to the voltage controlled oscillator 5, Is input to the phase comparator 6 in synchronization with the horizontal synchronizing signal H-sync. Therefore, a sampling clock synchronized with the horizontal synchronizing signal H-sync is generated.

On the other hand, the phase comparator 6 is operated only when the data recognition signal is in a logic low state (portion C 'in FIG. 7). That is, the switching element 10 is turned on when the data recognition signal is in the logic 'low' state to perform the phase comparison operation, and the phase comparison value is maintained when the data recognition signal is in the logic 'high' state. The switching element 10 is turned on so that the constant current generated in the current source 9 is applied to the first and second differential amplifiers 11 and 12, . Therefore, the current corresponding to the phase difference between the CRI pulse signal applied to the first differential amplifier 11 and the sampling clock applied to the second differential amplifier 12 is finally output through the output terminal.

The phase difference current outputted from the phase comparator 6 is converted into a frequency control voltage of a DC component having a predetermined level by the low-pass filter 7 to adjust the capacitance of the variable capacitor C2 constituted in the voltage-controlled oscillator 5 . Thus, the sampling clock finally output through the phase comparator 6 is synchronized with both the horizontal synchronizing signal H-sync and the CRI pulse signal.

However, the sampling clock generation circuit according to the present invention is not limited to the VTR with the Korean reservation recording method, but the sampling clock generation circuit according to the present invention may be provided with a predetermined number of bits in a Vertical Blanking Interval such as Teletext and Caption. It is obvious that it is possible to easily carry out the modification to all the systems which transmit the program information data and detect the transmitted program information data.

As a result, according to the sampling clock generation circuit of the VTR according to the present invention as described above, the predetermined program information data is loaded in the vertical blanking interval such as Korean reserved recording method (KBPS), teletext, caption, And generating a sampling clock synchronized with the horizontal synchronizing signal and the CRI pulse signal in the system for detecting the transmitted program information data, there is an advantage that the transmitted program information data can be extracted more stably and accurately.

Claims (4)

An apparatus for transmitting predetermined program information data in a vertical blanking interval and receiving the transmitted broadcast signal and detecting the program information data included in the received broadcast signal, the apparatus comprising: A voltage controlled oscillator receiving a horizontal synchronizing signal and a frequency control voltage simultaneously included in the received broadcast signal and correcting a phase of the sampling clock according to the frequency control voltage to generate the sampling clock synchronized with the horizontal synchronizing signal; Receiving the sampling clock output from the voltage control oscillator and a data recognition signal included in the received broadcast signal and indicating a frequency band of the CRI pulse signal and a CRI pulse signal indicating that the program information data is included, A phase comparator for comparing the phase difference between the CRI pulse signal received as the recognition signal is switched to a predetermined level and the sampling clock output from the voltage controlled oscillator; And And a low pass filter for converting the phase difference compared through the phase comparator to the frequency control voltage of a DC component having a predetermined level and outputting the frequency control voltage to the voltage controlled oscillator. The voltage controlled oscillator according to claim 1, A variable capacitance element whose capacitance is varied in accordance with the frequency control voltage supplied from the low-pass filter and whose horizontal synchronizing frequency output from the voltage controlled oscillator is adjusted according to the variable capacitance; And And a logic element for simultaneously receiving a horizontal synchronizing signal whose frequency is adjusted by the variable capacitance element and a horizontal synchronizing signal included in the received broadcast signal and for performing a logical operation to output a sampling clock synchronized with the horizontal synchronizing signal Wherein said sampling clock generating circuit is a sampling clock generating circuit for a video tape recorder. The semiconductor memory device according to claim 2, And a NAND gate connected to the sampling clock generating circuit. The phase comparator of claim 1, A constant current source generating a constant current; Phase comparing means comprising a plurality of differential amplifiers and mirror transistors for comparing the phase difference between the CRI pulse signal and the sampling clock; And And a switching element for switching the supply of the constant current generated from the constant current source to the phase comparing means in accordance with the voltage level of the data recognition signal.