KR0162435B1 - Apparatus for displaying semi-dynamic picture image multi-screen of a television receiver - Google Patents

Abstract

The present invention relates to a technology for displaying a multi-screen picture-in-picture / picture-out picture screen. In the case of providing a plurality of quasi-synchronous sub-screens using a limited number of tuners, two technologies are required. One is a technique for controlling a sub-screen tuner at high speed, and the other is a technique for processing a plurality of video signal sources selected for PIP screen at high speed. Therefore, in the present invention, high-speed tuning is implemented using the tuning accelerator 506 and the tuning memory 503, and the sub-screen image data obtained by the high-speed tuning using the PIP generating unit is processed at a faster speed to almost complete moving pictures. It is possible to provide a large number of sub-screens near.

Description

Multi-screen quaternary display device of TV receiver

(A)-(c) of FIG. 1 is an example of a display of a PIP screen.

2 is a block diagram of a piapi processing of a general television receiver.

3 is a block diagram of automatic gain control voltage processing in a typical television receiver.

4 is an output waveform diagram of an automatic gain control voltage for each channel in a general television receiver.

5 is a block diagram of a multi-screen quaternary display device of a television receiver of the present invention.

FIG. 6 is an exemplary block diagram of a tuning accelerator in FIG.

7 is a graph of image detection AGC characteristics.

8 is a comparison diagram of an AGC waveform and a conventional AGC waveform at the time of fast channel change according to the present invention.

9 is an operation signal flow chart for the multi-screen quasi-synchronous display of the present invention.

(A) and (b) of FIG. 10 are exemplary views of display of multi-screen quasi-motion picture according to the present invention.

FIG. 11 is another exemplary block diagram of a tuning accelerator in FIG.

FIG. 12 is a block diagram of an exemplary embodiment of the IP generation unit of FIG. 5.

13 is a flowchart of a write control signal of sub-screen image data according to the present invention.

14 is a flowchart of a read / display control signal of sub-screen image data according to the present invention.

15 is a flowchart of AGC operation signal of a tuning accelerator.

* Explanation of symbols for main parts of the drawings

500A: control unit 500B: sub-screen tuning unit

500C: main screen tuning section

500D: Image switch and horizontal / vertical pulse generator

500E: Piapi generator 500F: Image processing and display

501: remote control 502: microcomputer

503: tuning memory 504: sub-screen tuner

505: intermediate frequency detector for sub picture 506: tuning accelerator

507: main screen tuner 508: main screen intermediate frequency detector

509: image switch unit 510: horizontal / vertical pulse generator

511: quasi-dong Phi Phi screen generator 512: memory

513: image switch and processing unit 514: two-dimensional display element

The present invention relates to a technology for displaying a multi-screen picture-in-picture / picture-out picture screen. In particular, the present invention provides a main screen moving picture using one tuner, and performs fast tuning with the other tuner. The present invention relates to a multi-screen quaternary display device of a television receiver adapted to obtain a sub-screen signal and process it at high speed to provide a plurality of sub-screens close to a moving picture.

In the picture-in-picture / picture-out picture (hereinafter referred to as “piapi”) display method that provides one or more low screens in addition to one main screen, a plurality of (12) screens can be displayed as shown in FIG. The method of dividing the display into sub-screens, displaying three sub-screens in one main screen as shown in (b), and displaying one sub-screen in one main screen as shown in (c). have.

The piapi display method such as (a) and (b) of FIG. 1 is used for channel searching. It receives the main screen signal source of one channel through the main screen tuner and continues to display the same screen, while on the other hand, it tunes one channel through the sub-screen tuner to receive the sub screen signal source. It is possible by repeating the process of displaying one window among a plurality of multi-screen and PIP windows and then tuning to another channel and displaying the same in another window. Reference is made in more detail.

When the viewer outputs the channel search key signal using the remote control 201 or other key input means, the microcomputer 202 recognizes the key signal and then displays the switching control signal SC1 for selecting the video signal source. The switching unit 207 is output.

Accordingly, a plurality of external video signals inputted directly to the image switch unit 207 through the main image signal MV or the line received through the main image tuner 205 and the intermediate frequency detector 2 206. One of the video signals from AV1-AVn is selected by the video switch unit 207 and then displayed on the two-dimensional display element 213 through the image processing and the piapiece switching unit 211. This screen is shown in FIG. This is the main screen of the fairy tale shown in b).

Here, the microcomputer 202 outputs a tuning control voltage to an oscillator (VCO) built in the main picture tuner 205 to control tuning for the main picture signal source, and then the tuner 205. Accurate tuning is possible by compensating for the tuning voltage on the basis of the automatic fine adjustment signal AFT2 fed back from the intermediate frequency detector 2 206 which demodulates the intermediate frequency outputted from the.

Meanwhile, the microcomputer 202 outputs a switching control signal SC1 to the image switch unit 207 to perform a channel search command through the sub-screen tuner 203 and the intermediate frequency detector 1 204. The sub-screen tuner 203 until the first high frequency signal is received while the received sub-screen video signal SV is supplied to the horizontal / vertical pulse generator 1 208 and the piapi screen generator 210. The tuning voltage supplied to is gradually increased, and the tuning voltage compensation process thereof is the same as in the main tuner 205.

The first high frequency image signal received in this way is reduced to an appropriate size to be displayed on the magnetic screen through the piapi screen generator 210, stored in the memory 209, and then two-dimensionally transmitted through the image processing and the piapi switching unit 211. Displayed on the display element 213, this screen is the "a" screen in (b) of FIG.

Thereafter, the microcomputer 202 continuously increases the tuning voltage to receive a second high frequency image signal, which is displayed on the two-dimensional display device 213 through the above process, and this screen is shown in FIG. ) Is the “b” screen.

Thereafter, the tuning voltage is continuously increased to receive the third high frequency image signal, which is displayed on the two-dimensional display device 213 through the above process, which is the screen “c” in FIG.

This channel search process is repeatedly performed a display screen of a → b → c → d → a until all frequency bands of a predetermined high frequency are searched.

As shown in (c) of FIG. 1, the piapi display method is a method of simultaneously receiving and displaying a moving picture of a main picture and a moving picture of a sub picture by using two tuners.

That is, the microcomputer 202 supplies the tuning voltage of the main screen to the main screen tuner 205, and the main screen intermediate frequency signal generated from the tuner 205 receives the intermediate frequency breaker 2 (206). Through conversion to the baseband composite video signal is transmitted to the image switch unit 207 side. In addition, one video signal is selected from the composite video signal converted to the baseband or the plurality of external video signals AV1 to AVn by the switching control signal SC1 output from the microcomputer 202, which is an image. It is displayed on the two-dimensional display element 213 through the processing and the piapiece switching unit 211, and this screen corresponds to the main screen of the moving picture.

In addition, the sub-picture baseband composite video signal is received through the sub-screen tuner 203 and the intermediate frequency detector 1 204 by the tuning voltage output from the microcomputer 202, and the received video signal. One video signal of the plurality of external video signals AV1-AVn is selected as described above, and a video signal of a reduced form is outputted by the piapi screen generator 210 and the memory 209. It is displayed on an area of the two-dimensional display element 213 through the image processing and the piapiece switching unit, which corresponds to the sub-picture of the moving picture in (C) of FIG.

On the other hand, Figure 3 shows an example of the implementation of the automatic gain control signal (AGC) of a typical television receiver, such a system can not display the picture of the piapi screen quasi-synchronous, the reason for the waveform diagram of Figure 4 It will be described below with reference to.

For example, when KBS1 broadcast signal is displayed on the main screen, and KBS2, MBC, SBS is displayed on the piapi screen in a semi-synchronized manner, KBS2 → MBC → SBS → KBS2,... The annular tuning method of is applied, and when the tuning is changed from KBS2 to MBC, the automatic gain control voltage (AGC1) of KBS2 is not immediately converted to the automatic gain control voltage (AGC2) of MBC, as shown in FIG. It has a predetermined delay time T1.

The delay time T1 is referred to as a filter time constant that can vary according to the capacity of the capacitor C. The larger the capacity of the capacitor C, the longer the delay time T1 becomes. Usually, the capacity of the capacitor C used in a television receiver is about several hundred microseconds, and in terms of time, it is about 0.1 sec to 0.5 sec.

In this quasi-donghwa method with a long delay, the break time of the quasi-donghwa itself becomes longer, so it is more correct to say that it is still rather than quasi-donghwa.

Due to the above reasons, the general Piapi display means cannot display three or more videos simultaneously using two tuners, and if one additional tuner is added to solve this problem, the cost is increased and economical to the user. There was a difficulty to burden.

Accordingly, an object of the present invention is to provide a main picture of a complete moving picture using one tuner of two tuners, perform high speed tuning with the other tuner, obtain a sub picture signal, and process the piapi signal at high speed. A multi-screen quasi-moving display device of a television receiver providing a plurality of sub-screens close to a moving picture.

5 is a block diagram of a television receiver showing an application example of the multi-screen quaternary display device of the present invention, as shown in FIG. The control unit 500A for outputting tuning frequency data and edge seed data, and the sub-picture video signal source under the control of the control unit 500A to output a baseband composite video signal, wherein the tuning of the plurality of channels is performed. The sub-screen tuning unit 500B performs high-speed tuning using the frequency data and the edge seed data, and under the control of the control unit 500A, the video signal source for the main screen is tuned and output as a baseband composite video signal. Receiving the main image tuning unit 500C, the sub-screen tuning unit 500B, and the main screen tuning unit 500C, and a plurality of external image signals AV1-AVn.An image switch and a horizontal / vertical pulse generator 500D for switching the output of the input image under the control of the control unit 500A and for generating a horizontal signal and a vertical signal of the main / sub picture. And the image data of the channel currently tuned by the sub-screen tuning unit 500C in the buffer memory through the image switch and the horizontal / vertical pulse generator 500D, and output them to the image processing and display unit 500F. After the main memory via the main memory and outputs the image processing and display unit 500F side, the video signal and the piapi for the main screen output from the image switch and the horizontal / vertical pulse generator 500D It consists of an image processing and display unit 500F for switching the sub-screen video signal output from the generation unit 500E to display the main screen and the piapi screen. If the description of Figure 6 and to refer to FIG. 9 in detail as follows.

In order to provide a large number of quasi-synchronous sub-screens using a limited number of tuners, two technologies are essential. One of them is a technique for controlling a sub-screen tuner at high speed, and the other is for a PI screen. It is a technique for processing a plurality of video signal sources selected at high speed, and the present invention intends to provide just these two techniques.

For example, using two tuners, as shown in (A) and (B) of FIG. 10, video signals of A, B, and C channels can be displayed on a sub-screen in the form of quasi-synchronization on one monitor, and The overall processing for displaying the video signal on the main screen in the form of a moving picture will be described with reference to FIGS. 5 to 9.

Tuning data of the A, B, and C channels is stored in the tuning memory 503 in the drive initialization phase of the television receiver, and the auto gain of the A, B, and C channels is stored in the acceleration memory 506A in the tuning accelerator 506. The control voltage AGC is already stored.

In addition, the broadcast program of the D channel displayed on the main screen is received by the main screen tuner 507 and the main screen intermediate frequency detector 508 and is processed through the image switch unit 509, and then the image switch and The image is processed by the processing unit 513, that is, processed into a form suitable for display and displayed on the main screen of the two-dimensional display element 514 as the same screen.

At this time, the automatic gain control voltage (AGC) for the D channel is generated by the main screen intermediate frequency detector 508 and fed back to the main screen tuner 507, the automatic fine frequency generated by the intermediate frequency detector 508 The adjustment signal (AFT) is fed back to the microcomputer 502 side, and the microcomputer 502 compensates the tuning voltage based on this, so that accurate tuning is possible.

In this state, when the viewer outputs the corresponding key signal using the remote controller 501 to set the multi-screen quasi-motion mode as shown in FIG. 10, the microcomputer 502 recognizes the key signal. After that, the switching control signal SC2 is output to the AGC switch 506B and the switch 506B is short-circuited to the fixed terminal b. At this time, the switching control signal SC5 is output to the image switch unit 509 to display the sub-screen. The output signal of the intermediate frequency detector 505 is selected. (S1)

In addition, the microcomputer 502 reads out channel data of the A channel stored in the tuning memory 503 and transmits the channel data of the A channel stored in the acceleration memory 506A. After reading the automatic gain control voltage AGC and supplying it to the automatic gain control voltage of the sub-screen tuner 504, the controller waits for a predetermined time until the channel cooling transient is stabilized.

Subsequently, the quasi-synchronized pipi screen generator 511 processes the image data of an integer multiple of the field period of the sub-screen in the PI data format and stores it in the image memory 512, and then the horizontal / vertical sync signal (H / In synchronization with V), data stored in the image memory 512 is read again, and the image signal generated through the above process is displayed on the two-dimensional display element 514 through the image switch and the processor 513. This screen is the quasi-synchronous screen of the A channel in FIG. 8 (S2-S4).

In the above description, the automatic gain control voltage AGC previously stored in the acceleration memory 506A is read and transferred to the sub-screen tuner 504.

In general, a large-capacity filtration capacitor (see C1 in FIG. 6) is used to generate an automatic gain control voltage (AGC). Therefore, the time required for the stable image signal to be generated after the tuning data is supplied to the sub-screen tuner 504 is determined by the time until the filtration capacitor C1 completes the charging. Since it takes a long time, the waiting time becomes longer in FIG. Due to this factor, the period for sampling the broadcast signal of the next A channel becomes long, and thus, the screen of the A channel of the piapi becomes a long quasi-synchronized picture.

Therefore, in order to solve this problem, the present invention employs the acceleration automatic gain control voltage means as shown in FIG. Automatic gain control voltage (AGC) data is stored in the acceleration memory 506A by the write control signal WR output from the microcomputer 502 at the same time for storing the channel data of the A channel in the tuning memory 503. Stored. The channel search is performed through the PIP screen as in the prior art, in which the AGC switch 506B is short-circuited to the fixed terminal b by the switching control signal SC2 output from the microcomputer 502.

In the same way as the sub-screen display processing of the A channel, the sub-screen display processing of the broadcast programs of the B channel and the C channel is performed so that three quasi-moving screens, which are almost not completely animated, are displayed. The screen shown in FIG. 10 is shown in FIG. 10 (S5-S7) and (S8-S10).

In other words, the automatic gain control voltage AGC outputted to the sub-screen intermediate frequency detector 505 is stored in the acceleration memory 506A in the tuning accelerator 506, and the microcomputer 502 stores the memory 506A. ) To supply the automatic gain control voltage AGC to the sub-screen tuner 504.

That is, A channel B channel C channel D channel,. In the case of applying the annular tuning method, the automatic gain control voltage (AGC) stored in the acceleration memory 506A is read as described above, and AGC1 (A channel) → AGC2 (B channel) → AGC3 (C channel) → AGC1 ( A channel),... Generates a 1: 1 matched voltage with the broadcast in the form of and supplies it to the sub-screen tuner 504.

The waveform diagram of the automatic gain control voltage (AGC) generated through this process is generated almost exactly at the same time as tuning without requiring the time T1 of the filter time constant as shown in FIG. Can be.

For this reason, the repetition time of the quasi-synchronized PIP screen shown in FIG. 10 is shortened, and if the annular tuning time is set very short, it is possible to display an almost moving picture.

The automatic gain control voltage AGC stored in the acceleration memory 506A reads the automatic gain control voltage AGC output from the intermediate frequency detector 505 for the sub-picture upon initialization of the television set. ) Is the value memorized. As another storage method, the automatic gain control voltage AGC output from the sub-screen intermediate frequency detector 505 may be read and stored in the acceleration memory 506A immediately before the tuning is changed from the B channel to the C channel. have.

Hereinafter, another embodiment of the high-speed tuning means of the sub-screen tuner and the high-speed processing means of the PIP image signal, which are the main points of the present invention, will be described in detail with reference to FIGS. 11 to 15. same.

As shown in FIG. 11, in the tuning memory (e.g., EPIROM) 503 of the television receiver, tuning frequency data (TUNE_A), edge seed data (AGC_A), and B of the A channel corresponding to the PPI window of the sub picture. It is assumed that the tuning frequency data TUNE_B of the channel, the edge seed data AGC_B, the tuning frequency data TUNE_C of the C channel, and the edge seed data AGC_C are recorded in the initialization step S101.

At this time, the D channel is tuned by the main picture tuning unit 500C, and the image signal of the D channel is displayed on the two-dimensional display element 514 through the image switch unit 509, the image switch, and the processing unit 513. It is a state.

The sub-screen tuner 504 tunes the A channel (S101), and the multi-screen moving picture generation controller 701 switches the image switch unit 509 to transfer the video signal of the channel to the IP generation unit 500E. The control signal SC5 is output, whereby the output terminal of the sub-screen intermediate frequency detector 505 is connected to the write processor 702 through the image switch unit 509.

The write processor 702 records the digital image data of the A channel reduced in the horizontal / vertical direction in the image buffer memory 703A in units of one field or one frame (S101). 701 outputs control signals SC1 and SC2 to the write processor 702 and the image buffer memory 703A.

In addition, the multi-screen moving picture controller 701 causes the sub-screen tuner 504 to tune the B channel using the tuner control signal TCS (S103), and sets the flag to "1" (S104). Wait until the flag becomes " 0 " again (S105).

The flag is set to " 0 " again by performing a memory read operation as shown in Fig. 14 (S205, S210, S215). Thereafter, the write processor 702 records the video signal of the B channel in the image buffer memory 703A in units of fields or frames (S102), and the multi-screen moving picture controller 806 tunes the C channel (S103). Then, the flag is set to "1" (S104), waits until it becomes "0" again by performing the memory read operation of FIG. 14 (S105), and then records the image information of the C channel to the image buffer memory 703A ( In step S102, the sub-screen tuner 504 performs tuning for channel A again (S103).

As a result, if the above process is continued, the sub-screen tuning unit 500B performs A, B, C, A, B, C,... Tuning is continued in a circular pattern of " ", waits until the flag becomes " 0 ", and then records compressed video data in the video buffer memory 703A.

The flag is a communication parameter that connects the write operation control and the read operation control. The flag is set to '1' in the write operation control unit, that is, the multi-screen moving image generation controller 806, so that a new video signal is transmitted to the read operation control unit. This is to inform that it is stored in the image buffer memory 703A. Further, in the read operation control section, the flag is set to "0" (S205, S210, S215) because all the contents of the image buffer memory 703A are transferred to the main memory 703B side. This is to inform the write operation control unit to write to the memory 703A.

In this way, the video signal is written to the image buffer memory 703A using the flag, and the contents of the image buffer memory 703A are read out and transferred to the main memory 703B by the handshake method. As a result, a high-speed quasi-synchronous PIP screen can be generated.

Meanwhile, referring to FIGS. 12 and 14, a description will be given of how the sub-screen video signal can be read and processed to display the sub-screen in the form of quasi-synchronous. As follows.

The main memory 703B of the IP generation unit 500E is divided into regions corresponding to A, B, and C channels, and the image buffer memory 703A has an A channel as described in the above write operation. The data of channel B and channel C are sequentially stored, and the input selector 704 selects one of the output of the image buffer memory 703A and the output of the main memory 703B, and delivers it to the image restoration processor 705. This operation is performed because the multi-screen moving image generation controller 701 controls the clock signal of the IP memory 703 and the selection operation of the input selector 704 using the control signals SC2 and SC3. It becomes possible.

First, in FIG. 10, the sub-screen of the A channel is displayed by the following display operation.

In other words, if the flag is set to "1" in the A channel area centering on the vertical pulse (V) on the main screen (S201), if it is set to "1", the image data stored in the image buffer memory 703A is A. It is checked whether the data of the channel (S202), and as a result, in the case of the image data of the A channel, the output signal of the image buffer memory 703A is supplied to the image restoration processor 705 through the input selector 704 to receive the tenth image. The content of the A channel area of the main memory 703B is updated in two dimensions in the A channel window of FIG. 3A and is updated with new image data, that is, the image data currently displayed in the A channel window.

If this is not done, the image data generated in the A channel region of the main memory 703B is transmitted to the image restoration processor 705 through the input selector 704 so that the previous image is displayed in the window of the A channel.

After transmitting the image data as described above (S204), the flag is set to " 0 ", which causes the write operation controller to transmit all the data of the A channel stored in the image buffer memory 703A to the main memory 703B. This is to inform the video buffer memory 703A to capture the video data of the channel and record the data in one field unit or frame unit.

In FIG. 10, the sub-screen of the B channel is displayed by the following display operation.

That is, it is checked whether the flag is set to "1" in the B channel area centering on the vertical pulse (V) of the main screen (S206). If it is set to "1", the image data stored in the image buffer memory 703A is B. It is checked whether the data of the channel (S207). As a result, in the case of the image data of the B channel, the output signal of the image buffer memory 703A is supplied to the image restoration processor 705 through the input selector 704. The content of the B channel area of the main memory 703B is updated with the new image data, that is, the image data currently displayed in the current B channel window.

After transmitting the image data as described above (S204), the flag is set to '0', which causes the write operation controller to transmit all the data of the B channel stored in the image buffer memory 703A to the main memory 703B. This is to inform the video buffer memory 703A to capture the video data of the channel and record the data in one field unit or frame unit.

In FIG. 10, the sub-screen of the C channel is displayed by the following display operation.

That is, it is checked whether or not the flag is set to "1" in the C channel region centering on the vertical pulse (V) of the main screen (S211). If it is set to "1", the image data stored in the image buffer memory 703A is C. It is checked whether the data of the channel (S212), and as a result, in the case of the image data of the C channel, the output signal of the image buffer memory 703A is supplied to the image restoration processor 705 through the input selector 704 to be the tenth. The contents of the C channel region of the main memory 703B are updated in two dimensions in the C channel window of FIG. 3A and are updated with new image data, that is, the image data displayed in the current channel window.

After transmitting the image data as described above (S204), the flag is set to '0', which causes the write operation controller to transmit all the data of the C channel stored in the image buffer memory 703A to the main memory 703B. This is to inform the video buffer memory 703A to capture the video data of the channel and record the data in one field unit or frame unit.

In this way, the PPI screen generation in the A channel region → the PIP screen generation in the B channel region → the PIP screen generation in the C channel region → the Papi screen generation in the A channel region based on the vertical pulse of the main screen in time. If the cycle is repeated, the quasi-synchronized PIP of Fig. 10A is displayed.

If the above operation principle is applied, on the basis of the horizontal pulse of the main screen as a temporal reference, a pipi screen generation in the A channel region → a pipi screen generation in the B channel region → a pipi screen generation in the C channel region → Piapi screen generation,… If the cycle is repeated, the quasi-synchronized PI as shown in (B) of FIG. 10 is displayed.

In addition, in the write operation control, the operation of step 103 (S103) does not perform the tuning control for cyclically tuning the sub-screen tuner 504 as described above (i.e., fixes the A channel), and the multi-screen moving picture generation controller 701 controls the video switch unit 509 to cyclically select the outputs of the external input signals AV1, AV2, and the sub-screen intermediate frequency detector 505, and the cyclically selected video data When the image buffer memory 703A and the main memory 703B are controlled to be sequentially stored in the main memory 703B based on the input time of the vertical pulse, the moving picture of the D channel is displayed on the main screen, The contents of the AV1, AV2, and A channels are displayed in the form of quasi-synchronous.

Hereinafter, a high speed tuning process for displaying a quasi-donghwa sub-screen in a plurality of sub-screen windows will be described.

The automatic gain control voltage AGC supplied to the sub-screen tuner 504 for the A, B, and C channels having different electric field strengths becomes VA, VB, and VC in FIG. In the case of performing the cyclic tuning using the conventional method, since the video signal is stabilized after 0.5 seconds or more after tuning, the video signal for the sub picture must be recorded in the image buffer memory 703A after 0.5 seconds has elapsed. For this reason, data that has been tuned less than twice a second cannot be displayed on multiple screens. Therefore, when the existing AGC method is applied, the PIP display speed is very slow, and thus there is no static or multiplication.

In order to solve this problem, in the present invention, as shown in FIG. 11, tuning frequency data (TUNE_A, B, C) of each channel and age data (AGC_A, B, By recording C) and operating it as shown in FIG. 15, high-speed tuning is possible.

A write control process for high speed tuning is as follows.

The microcomputer 702 checks whether the current acceleration mode (for example, a multi-screen quasi-synchronization generation mode) (S301), and if the acceleration mode is selected, displays the tuning frequency data (TUNE_A, B, C) of the channel. In addition, the data of the corresponding channel of the tuning memory 503 is read (S302), which is transmitted to the sub-screen tuner 504 through the D / A converter 604 through the control teeth 603. Delivered. In this way, the automatic gain control voltage AGC is supplied to the sub-screen tuner 504 immediately after the tuning control, thereby enabling high-speed tuning.

The age data AGC_A, B, C of each channel is stored in the tuning memory 503 upon initialization in the television receiver as described below.

Since the edge-seed operation in the initialization mode is not the acceleration mode, the comparator 602 compares the output of the low-pass filter 601 with the output value of the current D / A converter 604 (S304) and performs the operation of the D / A converter 604. If the output value is larger, the current age data is decreased (S306). On the contrary, if the output value of the D / A converter 604 is smaller, the current age data is increased (S305). The analog signal is converted into an analog signal through the / A converter 604 (S307), supplied to the sub-screen tuner 504, and recorded in the corresponding channel of the tuning memory 503. (S308)

Thereafter, the comparator 602 compares the new output of the D / A converter 604 with the output of the low pass filter 601 and adjusts the age data as described above. Is carried out.

Through this process, a desired level of automatic gain control voltage (AGC) is generated and applied to the sub-screen tuner 504, and at the same time, the age data of the current channel is stored in the corresponding address of the tuning memory 503. Using the same method, B, C,… Channel data can be recorded during the initialization process.

As a result, an image buffer memory 703A and a main memory 703B having a large number of times the number of IP windows are installed to temporarily store data of a field or frame size of a newly input image in the image buffer memory 703A. Steps S204, S209, and S214 display the data in the main memory 703B at the same time as the display time based on the horizontal and vertical pulses of the main screen. If new image data is not stored in the image buffer memory 703A, the previous image data stored in the main memory 703B is read out and displayed in the window of the IP (S203), (S208), (S211). ), The display speed of quasi-donghwa is greatly increased, and flickering is eliminated during multi-screen navigation as in the existing multi-screen, so that stable quasi-synchronization can be realized.

In addition, a handshake method using a flag as shown in Figs. 13 and 14 is adopted for the control operation of reading and writing PIP image data to realize PAI animation. That is, by notifying the read control unit using a flag that the image buffer memory 703A has finished recording new image data, the waiting time until new image data is displayed in the PI window is reduced, and the read and display control unit By using the flag 0 to notify the write control unit to capture data, the time for capturing new data and writing it to the image buffer memory 703A at the time when the image data is transferred to the main memory is greatly shortened.

As described in detail above, the present invention displays a main picture broadcast using a single tuner as a moving picture, performs fast tuning with another tuner, obtains a sub picture signal, and processes it at high speed while maintaining a stable state. It has the effect of providing a subpicture that is almost a fairy tale.

Claims (9)

In order to quickly tune the sub-screen signal source, the control unit 500A stores a plurality of tuning frequency data and edge seed data and outputs them at a desired time point, and receives the control unit of the control unit 500A. And a sub-screen tuning unit 500B for performing high-speed tuning using the tuning frequency data and the edge seed data of the plurality of channels in tuning the video signal source for output to the baseband composite video signal. The video data of the channel currently tuned by the sub-screen tuning unit 500C through the horizontal / vertical pulse generating unit 500D is temporarily stored in the buffer memory and output to the image processing and display unit 500F, and then through the main memory. Multi-screen quasi-synchronization of the television receiver comprising the image processing and the piapi generator 500E outputted to the display unit 500F. Display devices. 2. The control apparatus 500A of claim 1, wherein the control unit 500A sets a tuning memory 503 for storing a plurality of tuning frequency data and edge seam data for each channel in a driving initialization step of a television receiver, and sets the sub picture mode according to an external control command. And a microcomputer (502) for reading out the tuning frequency data and the edge seed data stored in the tuning memory (503). The sub-screen tuning unit 500B according to claim 1, wherein the sub-screen tuning unit 500B controls the sub-screen tuner 504 for tuning the high-frequency image signal source for sub-screens under the control of the control unit 500A, and the sub-screen tuner 504. The sub picture intermediate frequency detector 505 for demodulating the baseband composite video signal and the sub picture automatic gain for each channel output from the sub picture intermediate frequency detector 505. And a tuning accelerator 506 which stores the control voltage ACC and supplies it to the sub-screen tuner 504 immediately after the read control signal is input from the control unit 500A at the time of tuning. Multi-screen quaternary display device. 4. The tuning accelerator 506 stores the age data under the control of the microcomputer 502 while storing one broadcast channel data, and controls the microcomputer 502 during the channel tuning. And a baseband composite video signal output from the sub-screen intermediate frequency detector 505 under the control of the microcomputer 502 or from the memory 506A. A multi-screen quaternary display device of a television receiver comprising an AGC switch (506B) for selecting output age data to be supplied to a sub-screen tuner (504). 4. The tuning accelerator 506 is supplied from the D / A converter 604 to the sub-screen tuner 504 on the basis of the age value returned from the sub-screen intermediate frequency detector 505. Comparing the age value is repeated in an endless cycle, the comparator 602 to set the age data to the desired value, and in the initialization step to select the age data output from the comparator 602 D / A The controller 603 outputs the transducer 604 to the tuning memory 503 and selects and outputs the stored age data in the acceleration mode, and the analog data output from the controller 603 is analog. A multi-screen quaternary display device for a television receiver comprising a D / A converter (604) for converting a signal into a sub-screen tuner (504). 2. The PIP generator 500E outputs various control signals based on a horizontal synchronous signal or a vertical synchronous signal to process a plurality of sub-screen image signals continuously input in a cyclic format. And a write processor 702 for storing, in the image buffer memory 703A, sub-picture image data which are sequentially reduced in the horizontal / vertical direction and inputted in the image buffer memory controller 701, and controls the controller 701. A video buffer memory 703A which stores the sub-picture image data of the currently tuned channel to the input selector 704, and stores the sub-picture image data in the corresponding area of the main memory 703B, and a preset number of sub-screen image data. And a main memory 703B for storing the image data as image data of the currently tuned channel output from the image buffer memory 703A, and an image buffer under the control of the controller 701. A television receiver comprising an input selector 704 which selectively receives the image data output from the memory 703A and the image data output from the main memory 703B and transfers them to the two-dimensional display element 514. Screen semi-synchronized display device. 7. The multi-screen quaternary display device according to claim 6, wherein a flag is used to indicate that all of the image data of the image buffer memory (703A) has been transmitted to the input selector (704) side. 7. The multi-screen quaternary display device according to claim 6, wherein the image buffer memory (703A) stores image data in field units. 7. The multi-screen quaternary display device according to claim 6, wherein the image buffer memory (703A) stores image data in units of frames.