KR100202664B1 - Forming method for metal wiring - Google Patents
Forming method for metal wiring Download PDFInfo
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- KR100202664B1 KR100202664B1 KR1019960029703A KR19960029703A KR100202664B1 KR 100202664 B1 KR100202664 B1 KR 100202664B1 KR 1019960029703 A KR1019960029703 A KR 1019960029703A KR 19960029703 A KR19960029703 A KR 19960029703A KR 100202664 B1 KR100202664 B1 KR 100202664B1
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- polymer
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- metal
- hard mask
- metal wiring
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 52
- 239000002184 metal Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 20
- 229920000642 polymer Polymers 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000000460 chlorine Substances 0.000 claims abstract description 11
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052801 chlorine Inorganic materials 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000001465 metallisation Methods 0.000 claims abstract description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims 2
- 238000005260 corrosion Methods 0.000 abstract description 7
- 230000007797 corrosion Effects 0.000 abstract description 7
- 238000012805 post-processing Methods 0.000 abstract description 2
- 230000007774 longterm Effects 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- -1 amine compound Chemical class 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 125000003698 tetramethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 금속배선 형성방법에 관한 것으로, 다량의 폴리머가 발생함으로써 임계치수(Critical cimension)의 조절이 어려워지고, 폴리머의 제거를 위한 장시간의 습식 후처리는 메탈 침해를 유발시키며, 폴리머의 클로린 캡춰(Chlorine capture) 현상으로 부식(Corrosion) 특성이 더욱 나빠지는 종래의 문제를 해결하기 위하여, 금속배선층 및 하드마스크를 증착하는 단계와, 이후 하드마스크를 식각하는 단계와, 이후 현상용액에서 폴리머를 제거하는 단계와, 이후 금속배선층을 식각하는 단계와, 이후 후처리를 하는 단계로 금속배선을 형성하는데, 이로써 하드마스크 식각 후 현상용액으로 폴리머를 제거하므로 후속 금속배선 식각시 임계치수의 조절이 용이하고, 폴리머에 의한 클로린 캡춰 현상이 감소되어 메탈의 부식을 방지할 수 있는 효과가 있다.The present invention relates to a metal wiring forming method, it is difficult to control the critical dimension (Critical Cimension) by the generation of a large amount of polymer, the long-term wet post-treatment for the removal of the polymer causes metal intrusion, chlorine capture of the polymer In order to solve the conventional problem of worsening corrosion characteristics due to chlorine capture, depositing a metallization layer and a hard mask, and then etching the hard mask, and then removing the polymer from the developer solution. And forming the metal wiring by etching the metal wiring layer and then post-treatment, thereby removing the polymer with the developing solution after etching the hard mask. In addition, the chlorine capture phenomenon by the polymer is reduced, thereby preventing the corrosion of the metal.
또한, 금속배선 식각 후 단시간의 후처리를 요하므로 메탈 침해가 거의 없고 후속하는 절연막을 완벽하게 증착할 수 있게 되어 소자의 신뢰도를 향상시킬 수 있는 효과가 있다.In addition, since the post-processing for a short time after the etching of the metal wire is required, there is almost no metal intrusion and the subsequent insulating film can be completely deposited, thereby improving the reliability of the device.
Description
제1도의 (a) 내지 (c)는 종래 금속배선 형성방법의 공정수순도.(A)-(c) of FIG. 1 is a process flowchart of the conventional metal wiring formation method.
제2도는 제1도의 (b)에 있어서, 폴리머가 하드마스크의 측벽이나 상부에 다량으로 잔존함을 보여주는 상부평면도(In-line SEM사진).FIG. 2 is a top plan view (b) of FIG. 1 (b) showing that the polymer remains in a large amount on the sidewall or top of the hard mask (In-line SEM photograph).
제3도의 (a) 내지 (d)는 본 발명 금속배선 형성방법의 공정수순도.(A) to (d) of FIG. 3 are process flow charts of the metal wiring forming method of the present invention.
제4도는 제3도의 (c)에 있어서, 현상용액에서 폴리머가 제거된 후의 상부평면도(In-line SEM사진).4 is a top plan view of (c) of FIG. 3 after the polymer is removed from the developing solution (In-line SEM photograph).
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11 : 기판 12 : 필드산화막11 substrate 12 field oxide film
13 : 게이트산화막 14 : 폴리실리콘13 gate oxide film 14 polysilicon
15 : TiN 게이트 16 : 하드마스크15 TiN gate 16: hard mask
17 : 감광막 18 : 폴리머17 photosensitive film 18 polymer
본 발명은 금속배선 형성방법에 관한 것으로, 특히 하드마스크를 이용하여 금속배선 형성시 하드마스크 식각후 그 측벽 및 하부메탈의 표면에 잔존하는 폴리머를 현상용액을 사용하여 제거하는 공정을 추가함으로써, 메탈식각 후 임계치수(Critical demension) 조절을 용이하게 하고 후처리 시간을 단축하여 메탈 침해(attack)를 최소화시킬 수 있는 데에 적당하도록 한 금속배선 형성방법에 관한 것이다.The present invention relates to a metal wiring forming method, and in particular, by adding a step of removing a polymer remaining on the surface of the sidewall and the lower metal using a developing solution after etching the hard mask using a hard mask, The present invention relates to a method for forming a metal wiring, which is suitable for minimizing metal attack by facilitating control of critical dimensions after etching and shortening post-treatment time.
통상적으로 알루미늄 금속배선 형성시, 감광막 대신 옥사이드나 나이트라이드층의 하드마스크가 널리 이용되고 있다.In general, when forming aluminum metal wiring, a hard mask of an oxide or a nitride layer is widely used instead of a photosensitive film.
이는, 현재 알루미늄 식각에 쓰이는 대부분의 식각장비에서 알루미늄과 감광막의 선택비는 1.5:1을 넘지 않는 반면에, 하드마스크 사용시에는 알루미늄과 하드마스크의 선택비를 10:1정도까지 올릴 수 있다.This means that the selectivity of aluminum and photoresist is not more than 1.5: 1 in most of the etching equipment used in aluminum etching, whereas the selection ratio of aluminum and hardmask can be increased to about 10: 1 when using hard mask.
따라서, 감광막의 두께를 1이하로 사용하여 노광공정을 용이하게 할뿐아니라 감광막에 대한 선택비가 나쁜(1.5:1이하) 장비에서도 알루미늄 침해없이 금속배선을 형성할 수 있다.Therefore, the thickness of the photoresist film 1 It can be used as below to facilitate the exposure process and to form metal wires without intruding into aluminum even in equipment having poor selectivity to the photoresist (less than 1.5: 1).
또한, 티타늄나이트라이드(TiN) 게이트 형성시에는 파티클 감소 및 공정의 청결유지 측면에서 하드마스크를 이용하고 있다.In addition, when forming a titanium nitride (TiN) gate, a hard mask is used in terms of particle reduction and process cleanliness.
상기와 같은 경우 하드마스크 하부의 메탈이 TiN게이트나 Al배선의 ARC TiN층의 경우를 예를 들어보면 우선, 플루오린(Fluorine) 플라즈마에서 하드마스크를 식각해야하는데 이때 상당량의 TiFx계통의 폴리머가 하드마스크의 측벽이나 상부에 잔존하며, 이어서 메탈 식각이 진행되면 더 많은 양의 폴리머가 형성되며 이의 제거를 위해 습식으로 후처리를 해야한다.In the above case, for example, when the metal under the hard mask is a TiN gate or an ARC TiN layer of an Al wiring, the hard mask must be etched in a fluorine plasma. Residual on the sidewalls or top of the mask, followed by metal etching, results in the formation of more polymer, which must be wet-treated to remove it.
일반적 후처리 용액은 ACT나 EKC등 아민계통의 화합물이나 암모니아수와 초산의 혼합용액을 사용한다.As a general post-treatment solution, an amine compound such as ACT or EKC, or a mixed solution of ammonia water and acetic acid is used.
그러나, 다량의 폴리머 제거를 위해 후처리 용액이 장시간 사용되는 경우에는 심각한 메탈 침해(attack)를 유발한다. 특히, 0.35이하의 금속배선 형성시에는 후처리 용액에 의한 메탈 침해(attack)가 더욱 더 심해진다.However, when the aftertreatment solution is used for a long time to remove a large amount of polymer, it causes serious metal attack. Specifically, 0.35 In forming the metal wirings below, metal attack by the post-treatment solution becomes even more severe.
그러면, 종래의 금속배선 형성방법에 대해 제1도를 참조하여 구체적으로 설명하면 다음과 같다.Next, a method of forming a conventional metal wiring will be described in detail with reference to FIG. 1.
금속배선층으로 TiN게이트나 Al배선의 ARC TiN층을 사용할 경우를 예를 들어보면 먼저, 금속배선층인 TiN게이트(5) 및 하드마스크(6)를 증착하고 제1도의 (a)에 도시한 바와 같이 감광막(7)을 패터닝하여 노광작업을 실시한다.In the case of using the TiN gate or the ARC TiN layer of the Al wiring as the metal wiring layer, for example, first, the TiN gate 5 and the hard mask 6, which are the metal wiring layers, are deposited, and as shown in FIG. The photosensitive film 7 is patterned to perform an exposure operation.
이후, 제1도의 (b)에 도시한 바와 같이, CF4나 CHF3및 C2F6등의 플루오린 플라즈마내에서 하드마스크(6)를 식각하는데, 이때 하드마스크(6)의 측벽이나 상부에 다량의 폴리머(8)가 잔존한다.Then, as shown in (b) of FIG. 1, the hard mask 6 is etched in a fluorine plasma such as CF 4 or CHF 3 and C 2 F 6 , wherein the sidewalls or top of the hard mask 6 A large amount of polymer 8 remains in the.
제2도는 폴리머(8)가 하드마스크(6)의 측벽이나 상부에 다량으로 잔존함을 보여주는 상부평면도(In-line SEM사진)이다.2 is a top plan view (in-line SEM photograph) showing that the polymer 8 remains in large quantities on the sidewalls or top of the hard mask 6.
그 다음, 제1도의 (c)에 도시한 바와 같이, 하부 금속배선층인 TiN게이트(5) 및 폴리실리콘(4)을 클로린 플라스마에서 식각한다.Then, as shown in (c) of FIG. 1, the TiN gate 5 and the polysilicon 4, which are lower metal wiring layers, are etched in chlorine plasma.
이때는, 부식(Corrosion)방지를 위하여 식각과 동시에 In-situ 처리를 한다.In this case, in-situ treatment is performed simultaneously with etching to prevent corrosion.
그러나, 이와같이 형성한 금속배선의 측벽 및 상부에 폴리머가 잔존하게 되는데, 이는 임계치수(Critical dimension)의 조절을 어렵게 한다.However, the polymer remains on the sidewalls and the top of the metal wiring thus formed, which makes it difficult to control the critical dimension.
따라서, 폴리머의 제거를 위해 장시간 습식 후처리를 진행시켜야 하는데, 이는 심각한 메탈 침해(attack)를 유발시키며 이로인해 후속 절연층의 증착시 스탭커버리지(Step coverage)의 불량으로 공극(Void)이 형성되어 소자특성 및 신뢰도를 악화시키는 문제를 갖는다.Therefore, wet post-treatment must be performed for a long time to remove the polymer, which causes serious metal attack, thereby forming voids due to poor step coverage during subsequent deposition of the insulating layer. There is a problem that deteriorates device characteristics and reliability.
또한, 다량의 폴리머에 의한 클로린 캡춰(Chlorine capture) 현상으로 메탈의 부식(Corrosion) 특성이 더욱 나빠지게 된다.In addition, the chlorine capture phenomenon caused by a large amount of polymer further worsens the corrosion property of the metal.
이처럼, 종래의 금속배선 형성방법은 금속배선층에 다량의 폴리머가 발생함으로써 임계치수(Critical dimension)의 조절이 어려워지고, 폴리머의 제거를 위한 장시간의 습식 후처리는 메탈 침해(attack)를 유발시키며, 폴리머의 클로린 캡춰(Chlorine capture) 현상으로 메탈의 부식(Corrosion)특성이 더욱 나빠지는 문제를 갖는다.As such, in the conventional metallization method, a large amount of polymer is generated in the metallization layer, making it difficult to control the critical dimension, and a long wet post-treatment for removing the polymer causes metal attack. Chlorine capture of the polymer has a problem that the corrosion property of the metal is worse.
본 발명은 상기와 같은 문제를 해결하기 위하여 창안된 것으로, 문제가 되는 폴리머를 하드마스크 식각후에 현상용액으로 잔류 폴리머를 제거하고 메탈식각을 하는 것으로, 메탈식가 후에 잔존하는 폴리머의 양을 최소화하여 후처리 시간을 단축시킴으로써 메탈 침해(attack)의 극소화 및 금속배선층의 임계치수를 용이하게 조절할 수 있도록 한 금속배선 형성방법을 제공함에 그 목적이 있다.The present invention was devised to solve the above problems, by removing residual polymer with a developing solution after etching the polymer in question after hard mask etching, and metal etching, to minimize the amount of polymer remaining after the metal It is an object of the present invention to provide a method for forming a metal wiring to minimize the metal attack and to easily control the critical dimension of the metal wiring layer by shortening the processing time.
상기와 같은 목적을 달성하기 위한 본 발명 금속배선 형성방법은 제3도에 도시한 바와 같이, 금속배선층 및 하드마스크를 증착하는 단계와, 이후 하드마스크를 식각하는 단계와, 이후 현상용액에서 폴리머를 제거하는 단계와, 이후 금속배선층을 식각하는 단계와, 이후 후처리를 하는 단계로 이루어지는 것으로, 이와같은 본 발명에 대해 첨부도면을 참조하여 좀 더 상세히 설명하면 다음과 같다.In order to achieve the above object, the present invention provides a method for forming a metal wiring, as shown in FIG. 3, depositing a metal wiring layer and a hard mask, etching the hard mask, and then polymer in a developer solution. Removing, and then etching the metal wiring layer, and after the step of the post-treatment, as described in more detail with reference to the accompanying drawings for the present invention as follows.
본 발명은 하드마스크 식각 후 생성되는 폴리머를 1차적으로 현상액으로 제거하고 이어서 메탈식각을 하므로 메탈식각시의 폴리머 양이 줄어들고, 후처리 시간이 크게 단축되어 메탈 침해(attack)를 상당히 줄일 수 있도록 한 것이다.According to the present invention, the polymer produced after the hard mask etching is first removed with a developer and then the metal is etched, thereby reducing the amount of polymer during metal etching and significantly reducing the post-treatment time, thereby significantly reducing metal attack. will be.
금속배선층으로 TiN게이트나 TiN이 반사방지층으로 형성된 Al배선 및 반사방지층으로 쓰는 텅스텐 배선을 포함하는 경우를 예를 들어보면 먼저, 금속배선층인 TiN게이트(15) 및 하드마스크(16)를 증착하고 제3도의 (a)에 도시한 바와 같이 감광막(17)을 패터닝하여 노광작업을 실시한다.For example, the metal wiring layer includes a TiN gate or an Al wiring formed of an antireflection layer and a tungsten wiring used as an antireflection layer. First, the TiN gate 15 and the hard mask 16, which are metal wiring layers, are deposited. As shown in Fig. 3A, the photosensitive film 17 is patterned to perform exposure work.
이후, 제3도의 (b)에 도시한 바와 같이, CF4나 CHF3및 C2F6등의 플루오린 플라즈마내에서 하드마스크(16)를 Ti가 포함되는 금속배선층이 드러날 때까지 식각한 후 감광막(17)을 제거하는데, 이때 하드마스크(16)의 측벽 및 상부에는 다량의 폴리머(18)가 잔존하게 된다.Thereafter, as shown in FIG. 3 (b), the hard mask 16 is etched in a fluorine plasma such as CF 4 or CHF 3 and C 2 F 6 until the metal wiring layer including Ti is exposed. The photoresist film 17 is removed, and a large amount of polymer 18 remains on the sidewalls and the top of the hard mask 16.
그리고, 제3도의 (c)에 도시한 바와 같이, 하드마스크(16)의 측벽 및 상부에 잔존하는 폴리머(18)를 현상용액(Developer)에서 제거한다.Then, as shown in FIG. 3C, the polymer 18 remaining on the sidewalls and the upper portion of the hard mask 16 is removed from the developer.
이때, 상기 현상용액은 2.38%의 티엠에이에이치(Tetramethyl Ammoniun Hydroxide)를 사용하여 15초 이내의 단시간에 폴리머(18)를 제거한다.In this case, the developing solution removes the polymer 18 in a short time within 15 seconds by using 2.38% of TEM (Tetramethyl Ammoniun Hydroxide).
제4도는 현상용액에서 폴리머(18)가 제거된 후의 상부평면도(In-line SEM)이다.4 is a top plan view (In-line SEM) after the polymer 18 is removed from the developing solution.
이후, 제3도의 (d)에 도시한 바와 같이, TiN 게이트(15) 및 폴리실리콘(14)의 하부 금속배선층을 클로린(Chlorine) 플라즈마에서 식각하는데, 부식(Corrosion)방지를 위하여 식각과 동시에 In-situ 처리를 한다.Subsequently, as shown in (d) of FIG. 3, the lower metal wiring layers of the TiN gate 15 and the polysilicon 14 are etched in a chlorine plasma, and simultaneously In is etched to prevent corrosion. -situ processing
이처럼, 폴리머(18)를 현상용액에서 제거함으로써 폴리머(18)의 양이 크게 줄어 습식 후처리 공정이 단시간에 이루어질 수 있게 된다.As such, by removing the polymer 18 from the developing solution, the amount of the polymer 18 is greatly reduced, and the wet post-treatment process can be performed in a short time.
즉, 후처리에 필요했던 시간이 종래의 1/4정도로 줄일 수 있다.That is, the time required for post-treatment can be reduced to about 1/4 of the conventional one.
따라서, 메탈 침해(attack)를 최소로 할 수 있으며 이는, 후속 절연막을 증착할 때 공극(Void)의 형성을 방지할 수 있게 되어 소자의 신뢰도가 향상된다.Therefore, metal attack can be minimized, which makes it possible to prevent the formation of voids when depositing a subsequent insulating film, thereby improving the reliability of the device.
상술한 바와 같이, 본 발명은 하드마스크 식각 후 현상용액으로 폴리머를 제거하므로 후속 금속배선 식각시 임계치수의 조절이 용이하고, 폴리머에 의한 클로린 캡춰 현상이 감소되어 메탈의 부식을 방지할 수 있는 효과가 있다.As described above, since the present invention removes the polymer with the developing solution after etching the hard mask, it is easy to control the critical dimension during the subsequent metallization etching, and the chlorine capture phenomenon by the polymer is reduced to prevent corrosion of the metal. There is.
또한, 금속배선 식각 후 단시간의 후처리를 요하므로 메탈 침해가 거의 없고 후속하는 절연막을 완벽하게 증착할 수 있게 되어 소자의 신뢰도를 향상시킬 수 있는 효과가 있다.In addition, since the post-processing for a short time after the etching of the metal wire is required, there is almost no metal intrusion and the subsequent insulating film can be completely deposited, thereby improving the reliability of the device.
Claims (5)
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| KR1019960029703A KR100202664B1 (en) | 1996-07-23 | 1996-07-23 | Forming method for metal wiring |
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| KR1019960029703A KR100202664B1 (en) | 1996-07-23 | 1996-07-23 | Forming method for metal wiring |
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| KR100824853B1 (en) * | 2006-12-27 | 2008-04-23 | 동부일렉트로닉스 주식회사 | Method of making semiconductor device |
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| KR100824853B1 (en) * | 2006-12-27 | 2008-04-23 | 동부일렉트로닉스 주식회사 | Method of making semiconductor device |
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