KR100200880B1 - Method for forming a contact of a semiconductor device - Google Patents

Abstract

The present invention discloses a metal wiring method with improved step coverage. The present invention provides a semiconductor substrate including a MOS transistor; Forming a first interlayer insulating film on the semiconductor substrate; etching the first interlayer insulating film to expose a junction region between the gate electrodes of the MOS transistor; Forming a second conductive layer patterned to contact the junction region; Depositing a second interlayer insulating layer on the resultant; depositing a second interlayer insulating layer to expose a portion where the second conductive layer is in contact with the semiconductor substrate; Forming a third conductive layer in contact with the exposed second conductive layer; Depositing and flowing an interlayer planarization film over the entire structure; etching the flowed interlayer planarization film until the third conductive layer surface is exposed; and forming a metal interconnect to contact the third conductive layer. It features.

Description

Metal wiring formation method of semiconductor device

1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device.

2A to 2E are cross-sectional views of respective process sequences for explaining the method for forming metal wirings of the semiconductor device of the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 3 gate electrode

5: first interlayer insulating film 6: Vss line

7 second interlayer insulating film 8 third polysilicon film for buffer

9 interlayer planarization film 10 metal wiring

Technical Field of the Invention

The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, to a method for forming a metal wiring of a semiconductor device that can improve step coverage during metal wiring of an S-RAM device.

[Private Technology]

In general, SRAM is a volatile memory along with a DRAM (dynamic random access memory). Unlike DRAM, SRAM does not need to recharge periodically stored information, and is easier to design and has less potential problems. It is a very popular memory device because it can drive the device at high speed, low power consumption and simple operation.

This SRAM consists of a doped first polysilicon forming a gate electrode, a doped second polysilicon forming a Vss line, and a doped third polysilicon used as a load resistor, of which the Vss line A portion of the second polysilicon connected to is connected to the metal interconnection film to apply power to the device.

Herein, a method of contacting a conventional second polysilicon and a metal wiring film will be described. As shown in FIG. 1, a gate electrode 3 formed of a gate oxide film 2 and a doped first polysilicon is formed on a semiconductor substrate. And a spacer 4 on both sides of the gate electrode 3, a first interlayer insulating film is formed on the entire structure, and then selectively etched to expose the substrate region between the gate electrodes, and then the doped second polysilicon film is formed. After the deposition, the second polysilicon film is partially etched to form a buffer layer 6 for contact between the metal and the substrate. Then, although not shown in the drawings, a third polysilicon film (not shown) for forming a load device is formed, and after a load resistor or thin film transistor is formed, a BPSG film which is an interlayer planarization film over the entire structure. 9 is deposited to a predetermined thickness and flows. Thereafter, the buffer layer 6 is etched to expose. Then, the metal wiring 10 is formed and contacted with the buffer layer 6.

[Technical problem to be achieved]

However, according to the conventional method as described above, a serious step occurs during the contact process between the metal wiring 8 and the contact buffer layer 6, resulting in a problem of deterioration of the metal wiring characteristics of the device. In addition, the load device is formed between the second polysilicon film and the metal wiring for forming the Vss line, so that the interlayer insulating film has a relatively thick thickness between the second polysilicon film and the metal wiring. . As a result, the depth of the contact hole is deepened, and thus, there is a difficulty in effectively depositing a metal wiring.

Accordingly, the present invention is to solve the above-mentioned conventional problems, by interposing a buffer polysilicon film in the high step portion between the second polysilicon film and the metal wiring, and at the same time by adjusting the appropriate hole depth during contact hole etching, It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device that can improve step coverage and increase metal wiring characteristics of an SRAM.

[Configuration and Function of Invention]

In order to achieve the above object of the present invention, the present invention provides a semiconductor substrate comprising a MOS transistor; Forming a first interlayer insulating layer on the semiconductor substrate; Etching the first interlayer insulating layer to expose a junction region between the gate electrodes of the MOS transistors; Forming a second conductive layer patterned to contact the junction region; Depositing a second interlayer insulating film over the resulting product; Depositing a second interlayer-insulating film to expose a portion where the second conductive layer is in contact with the semiconductor substrate; Forming a third conductive layer for the buffer to be in contact with the exposed second conductive layer; Depositing and flowing an interlayer planarization film over the entire structure; Depositing and flowing an interlayer planarization film over the entire structure; Etching the flowed interlayer planarization layer until the third conductive layer surface for the buffer is exposed; And forming a metal wire to contact the third conductive layer for the buffer.

The present invention also provides a semiconductor substrate including a MOS transistor; Forming a conductive layer for a buffer on a contact predetermined portion of the surface of the semiconductor substrate; Depositing an interlayer insulating film on top of the result; Etching the interlayer insulating layer to expose the buffer conductive layer to form a contact hole; And forming the metal wiring in contact with the buffer conductive layer.

According to the present invention, the third polysilicon for the buffer is formed between the second polysilicon film and the metal wiring, and the metal wiring can be effectively formed by reducing the step difference of the contact hole by the thickness of the third polysilicon film.

EXAMPLE

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views of respective process sequences for explaining a method for forming metal wirings of a semiconductor device according to the present invention. As shown in FIG. 2A, an SRAM is formed in the semiconductor substrate 1. In order to form the transistor, by a known method, a gate electrode 3 formed of the gate insulating film 2 and the doped first polysilicon and sidewall spacers 4 are formed on both sides of the gate electrode.

Then, as shown in FIG. 2B, the first interlayer insulating film 5 is formed by a known deposition method on the entire structure, for electrical insulation between the lower transistor and the conductive layer to be formed later. The interlayer insulating film 5 is etched to expose a portion of the substrate between the gate electrodes 3. Subsequently, a doped second polysilicon film is deposited on the entire surface of the structure to a predetermined thickness, and the second polysilicon film is partially etched by a patterning process to form the Vss line 6 and the contact buffer layer.

Thereafter, FIG. 2C is a cross-sectional view in which the buffer conductive layer 8 according to the present invention is formed, and after the second interlayer insulating film 7 is formed to a predetermined thickness on the resultant surface of the semiconductor substrate, the second interlayer insulating film 7 is formed on the Vss line. The predetermined portion is etched so that the contacted portion between the 6 and the substrate 1 is exposed. Subsequently, a doped third polysilicon film 8 for the buffer layer is deposited. At this time, the third polysilicon film 8 has a recessed portion due to the lower step, and the third polysilicon for the buffer is deposited and patterned simultaneously with the formation of the third polysilicon film for the load device without a separate process.

Subsequently, as shown in FIG. 2D, a BPSG film 9, which is an interlayer planarization film, is deposited on the entire structure and flows at a high temperature to have a flat surface. Subsequently, the BPSG film 9 is etched to expose the contact portions of the lower second polysilicon film and the third polysilicon film. Then, most of the BPGS film 9 is removed, and is embedded in the groove portion surrounded by the third polysilicon generated due to the lower step. Accordingly, the contact hole formed in the BPSG film 9 has a flat surface and is provided with a lower end of the hole, and the step coverage is improved by interposing the third polysilicon film between the second polysilicon film and the metal wiring.

Subsequently, as shown in FIG. 2E, metal wirings are formed on the entire structure surface, thereby completing metal wiring with improved desired step coverage.

[Effects of the Invention]

As described in detail above, according to the present invention, the third polysilicon for the buffer is formed between the second polysilicon film and the metal wiring, and the metal wiring is effectively reduced by reducing the step difference of the contact hole by the thickness of the third polysilicon film. Can be achieved.

The present invention is not limited to the above embodiment.

The above embodiment has been described by limiting the gate electrode material, the Vss line forming material, and the buffer layer to the first, second, and third polysilicon, but the present invention may be equally applicable to other conductive layers other than polysilicon. In addition, although the BPSG film has been described as an example of the interlayer planarization film in the present invention, any other film having excellent planarization characteristics and fluidity may be used in various ways, and the present invention has been described with reference to SRAM. It will be appreciated by those skilled in the art that the same applies to all the semiconductor devices that make up the wiring via the conductive layer at the contact portion in order to improve the step coverage of the hole.

Claims (5)

Providing a semiconductor substrate on which a MOS transistor is formed; Forming a first interlayer insulating layer on the semiconductor substrate; Etching the first interlayer insulating layer to expose a junction region between the gate electrodes of the MOS transistors; Forming a second conductive layer patterned to contact the junction region; Depositing a second interlayer insulating film over the resulting product; Etching the second interlayer insulating film to expose a portion where the second conductive layer is in contact with the semiconductor substrate; Forming a third conductive layer for the buffer to be in contact with the exposed second conductive layer; Depositing and flowing an interlayer planarization film over the entire structure; Etching the flowed interlayer planarization layer until the third conductive layer surface for the buffer is exposed; And forming a metal wiring to contact the third conductive layer for the buffer. The method of claim 1, wherein the first, second, and third conductive layers are doped polysilicon films. The method of claim 1, wherein the interlayer planarization film is an insulating film having fluidity. 4. The method for forming metal wirings of a semiconductor device according to claim 1 or 3, wherein the interlayer planarization film is a BPSG film. Providing a semiconductor substrate on which a MOS transistor is formed; Forming a conductive layer for a buffer on a contact predetermined portion of the surface of the semiconductor substrate; Depositing an interlayer insulating film on top of the result; Etching the interlayer insulating film to expose the buffer conductive layer to form a contact hole; And forming metal wires so as to contact the buffer conductive layer.