KR100200571B1 - Apparatus for multi-/demulti-plexing of frame data in an electronic exchange - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an all-electronic exchange, and in particular, when a high-speed serial 64-channel data line is matched in a switch network, the multiplexed and demultiplexed serial 4.096 Mbps 32 slot highway data into parallel 8-bit 16.382 Mbps frame data is used for communication. The present invention relates to a frame data multiplexing / demultiplexing apparatus of an electronic switching system capable of matching to a furnace system.

Conventional electronic switchboards should increase the number of separate multiplexing processing units when the capacity increase of the time switch / link unit is required. As a result, an increase in the slot highway cable is required. There is a problem that an additional circuit must be installed.

The present invention can solve the 2K channel by the configuration of the 1K capacity slot highway connection system in the conventional electronic switchboard, improve the data bandwidth per line of the slot highway, improve the switching speed of the frame data and SDH / SONET It can easily accommodate STM-1 data link matching.

Description

Frame Data Multiplexing / Demultiplexing Device of Electronic Switching System

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an all-electronic exchange, and more particularly, when a slot high-way (SHW) serial 64-channel data line is matched in a switch network, 32-bit serial data of 4.096 Mbps is stored in parallel 8-bit 16.382 Mbps. The present invention relates to an apparatus for multiplexing / demultiplexing frame data of an electronic switching system, which can be multiplexed and demultiplexed with frame data so as to be matched with a call path system.

As can be seen in the accompanying drawings, Figure 1, an access switching system (100) comprising a device unit (10) and a time switch / link unit (20), and central data. It consists of an interconnection network system 200 consisting of a link unit 220, a space switch unit 230 and a network synchronizer 210, the time switch / link unit 20 is a multiplex processing unit 21, a time switch The part 22 and the data link part 23 are provided. The access switching system 100 is a sub-system that is responsible for external matching of an electronic switchboard such as a subscriber or a trunk board, and the interconnection network system 200 is a sub-interface in which resources for providing the access switching system 100 are interconnected. System. At this time, the network synchronizer signal applied to the interconnect network system 200 is a signal supplied to match the timing synchronization between the entire telephone line system and the network.

Referring to the operation of the present invention configured as described in detail as follows.

The network synchronizer 210 is responsible for the network synchronizer in the switch network. The central data link unit 220 and the space switch unit 230 receive a sync clock and a sync frame pulse from the network synchronizer 210, and time switch / The link unit 20 receives the synchronization clock from the central data link unit 220 connected thereto. Using the frame signal and the clock received from the data link unit 23 in the time switch / link unit 20, the time switch unit 22 and the multiplexing unit 21 process the time switching and data multiplexing into the frame data. In addition, the multiplexing processor 21 transmits a signal of 4.096 MHz / 8 KHz necessary for serial slot highway data matching to the device unit 10. At this time, the device unit 10 transmits / receives 32 channel PCM data to the multiplex processing unit 21 in the time switch / link unit 20 using a frame synchronization signal of 8 KHz. The multiplexing processor 21 time-division-multiplexes 32 serial channels of 2.048 Mbps PCM data received from the device unit 10 into frame data of 8.192 Mbps in parallel and transmits / receives them to the switch network link. Done. The reverse frame data demultiplexing goes through a process necessary for PCM data transmission to the device unit 10.

In the conventional all-electronic exchange as described above, the frame data structure required for matching to the switch network has a frame unit of 8 KHz. At this time, the frame data accommodating 32 channels of the existing 32 slot highway has 1K channel capacity. Therefore, when the capacity increase is demanded at the time switch / link part, a separate multiplexing part must be increased. Accordingly, an increase in the slot highway cable is required. Therefore, an additional data delay compensation circuit is installed according to the system installation area and the cable length. There is a problem that must be done.

The present invention has been made in view of the above-described problems. When the capacity of the switch network needs to be increased through the matching of 64 channels of all electronic switchboards, multiplexing / slot matching of 64 channels of the slot highway can be performed without additional installation. An object of the present invention is to provide a demultiplexing device.

In order to achieve the above object, the present invention includes a network synchronizer for outputting a network synchronizer in charge of a network in the switch network; A central data link unit configured to receive a data signal applied from an access switching system according to a synchronization clock applied from the network synchronizer; An all-electronic exchanger including a space switch unit for matching data from the central data link unit, wherein the 64-channel serial data applied from the slot highway is converted into 64-channel 8-bit parallel data and output. A serial / parallel converter; A latch unit for latching 8-bit parallel data applied from the serial / parallel conversion unit according to an applied control signal; A multiplexer for multiplexing each bit to generate parallel time-division data from 8-bit parallel data applied from the latch unit; A shift register unit configured to perform a shift and delay for aligning an output of data multiplexed and applied to each bit from the multiplexer; A frame synchronous latch unit for aligning and outputting data applied from the shift register unit into a synchronous pulse and a clock applied from the network synchronizer unit through the central data link unit in order to map a data structure corresponding to switch network synchronization; And a control signal generation unit for outputting a control signal to the latch unit, the multiplexing unit, the shift register unit, and the frame synchronization latch unit.

1 is a configuration of a frame data multiplexing / demultiplexing apparatus of a conventional all-electronic exchange

Block diagram.

2 is a frame data multiplexing / demultiplexing apparatus of an electronic switching system according to the present invention;

Construction block diagram.

3 is a timing diagram of 64 channel serial data in a slot highway.

Explanation of symbols on the main parts of the drawings

10: device portion 20: time switch / link portion

21: multiplexing processing unit 22: time switch unit

23: Data link part 30-0 to 30-31: Serial / parallel conversion part

40-0 to 40-31: latch section 50-0 to 50-31: multiplexing section

60-0 to 60-31: shift register section 70: frame sync latch section

80: control signal generator 100: access switching system

200: interconnection network system 210: network synchronization unit

220: central data link unit 230: space switch unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Frame data multiplexing / demultiplexing apparatus of an electronic switching system according to the present invention, as shown in Figure 2 attached, parallel / parallel conversion unit (30-0 ~ 30-31), latch unit (40-0 ~ 40) -31), multiplexing sections 50-0 to 50-31, shift register sections 60-0 to 60-31, frame synchronous latch section 70, and control signal generation section 80.

The serial / parallel converters 30-0 to 30-31 convert the 64 channels of serial data applied from the slot highway into 8 bits of parallel data of 64 channels for each latch unit 40-0 to 40-31. Will output The latch units 40-0 to 40-31 store 8-bit parallel data applied from the serial / parallel conversion units 30-0 to 30-31 to the control signals applied from the control signal generator 80. Latch accordingly. The multiplexers 50-0 to 50-31 multiplex each bit to generate parallel time division data from 8 bits of parallel data applied from the latch units 40-0 to 40-31 and shift shift unit 60-31. 0 to 60-31). The shift register sections 60-0 to 60-31 perform a shift and delay for aligning the output of the data multiplexed by the respective bits from the multiplexing sections 50-0 to 50-31 to the frame synchronization latch section. Output to 70. The frame synchronizer latch unit 70 is configured from the network synchronizer unit 210 to map the data applied from the shift register units 60-0 to 60-31 to a frame structure that conforms to the switch network synchronization. The output signal is aligned and output as a sync pulse and a clock applied through 220. The control signal generator 80 includes a latch unit 40-0 to 40-31, a multiplexing unit 50-0 to 50-31, a shift register unit 60-0 to 60-31, and a frame synchronization latch unit ( Output control signal to 70) side.

Referring to the operation of the present invention configured as described in detail as follows.

As shown in FIG. 3, the serial data of the PCM 64 channel from the slot highway is continuously applied to the serial / parallel conversion units 30-0 to 30-31 as the frame synchronization signal is applied. 64 channel serial data from 0 to slot highway 31 are continuously converted into parallel data through respective serial / parallel conversion units 30-0 to 30-31 corresponding thereto. At this time, each of the serial / parallel converters 30-0 to 30-31 is an 8-bit data converter, which is continuously converted by a clock FS (Frame Synchronization) that is bit-synchronous with serial data. As can be seen in FIG. 3A, one channel is accurately latched into parallel channel data by a latch signal applied from the control signal generation unit 80 at the time of complete serial / parallel conversion. Conversion from serial / parallel conversion section 0 (30-0) to serial / parallel conversion section 31 (30-31) and latch section 0 (40-0) to latching section 31 (40-31) in the same manner as described above. After the data of all channels are continuously converted in parallel, the latched parallel 8-bit data is applied to each of the multiplexing units 50-0 to 50-31 corresponding to each bit to generate parallel time division data. The data of 32 slot highways related to bit 0 are received from the multiplexer 0 (50-0) to perform 32: 1 multiplexing. That is, the multiplexer 0 (50-0) receives only 32 bits 0 from 8-bit parallel data applied from 32 slot slots and outputs them by time division multiplexing. Similarly, each of the multiplexers 50-1 through 50-31 corresponding to bits 1 through 7 performs the initial multiplexing process. At this time, since the data string multiplexed at 32: 1 has a dummy value at the critical point of each time slot, each multiplexer 50-0 to 50-31 according to the control signal of the control signal generator 80 is used. When the shift registers 60-0 to 60-31 are used in the shift registers 60-0 to 60-31 to apply the output to the frame synchronizer latch 70, the frame synchronizer latch 70 receives the time division and the data. In order to map the aligned parallel data into a frame structure corresponding to the synchronization of the switch network, the synchronization is output from the network synchronizer 210 using a synchronization pulse and a clock through the central data link unit 220. Accordingly, frame data of 2048 channel structure in the form of parallel 8-bit 16.384Mbps can be obtained from the 64 channel serial PCM data applied from 32 slot slots.

On the other hand, in order to demultiplex 2K frame data in the opposite direction to serial PCM data, the serial / parallel conversion units 30-0 to 30-31 in FIG. 2 are replaced with parallel / serial conversion units, and the multiplexer 50 The data processing may be performed by exchanging -0 to 50-31) with a demultiplexer, that is, a 1:32 demultiplexer.

As described above, the present invention can solve the 2K capacity channel by the configuration of the 1K capacity slot highway connection system in the conventional electronic switchboard, thereby improving the data bandwidth per line of the slot highway, the switching speed of the frame data It can easily accommodate enhancements and STM-1 datalink matching of SDH / SONET.

Claims (1)

A network synchronizer 210 which is responsible for the network synchronizer in the switch network and outputs a network synchronizer signal; A central data link unit 220 for receiving a data signal applied from an access switching system 100 according to a synchronization clock applied from the network synchronizer 210; In an all-electronic switch having a space switch unit 230 for matching the call path data applied from the central data link unit 220, 64 channels of serial data applied from the slot highway are used. Serial / parallel conversion units 30-0 to 30-31 for converting and outputting bit parallel data; A latch unit 40-0 to 40-31 for latching 8-bit parallel data applied from the serial / parallel conversion units 30-0 to 30-31 in accordance with a control signal applied thereto; A multiplexing unit (50-0 to 50-31) for multiplexing each bit to generate parallel time division data from parallel data of 8 bits applied from the latch units (40-0 to 40-31); Shift registers 60-0 to 60-31 for performing shifts and delays to align output of data multiplexed from the multiplexers 50-0 to 50-31 for each bit; In order to map the data applied from the shift registers 60-0 to 60-31 into a frame structure conforming to the switch network synchronization, the data is applied from the network synchronizer 210 through the central data link unit 220. A frame synchronous latch unit 70 for aligning and outputting the synchronous pulses and clocks; Control signals are sent to the latch portions 40-0 to 40-31, the multiplexing portions 50-0 to 50-31, the shift register portions 60-0 to 60-31, and the frame synchronization latch portion 70. Frame data multiplexing / demultiplexing apparatus for an electronic switch, characterized in that it comprises a control signal generator (80) for outputting.