KR100199100B1 - Apparatus for decoding digital audio signals - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio signal decoding apparatus, and the conventional apparatus has a problem in that it is expensive and takes up a lot of area because many devices need to be used. In order to solve this problem, the present invention selects a table according to the bit rate and sampling frequency output from the header information decoding unit and decodes it when a flag is generated according to the count signal to output the BPC signal. Wow; A scale factor decoding unit for receiving an output signal of the bit batch data decoding unit and decoding and outputting a scale factor; Receives the signal (gr) and the signal (Tableselect) from the bit batch data decoding unit, and controls the signal (splstart) and signal (datainen) from the scale factor decoding unit through the ROM table to decode and output the sample data A data decoding unit; Invented a digital audio signal decoding device composed of a calculation unit for outputting the PCM data by calculating the output signal of the sample data decoding unit and the scale factor decoding unit, through the operation of the decoding of the compressed audio data format, The signal flow of the system applied as the basic circuit structure can be simplified and the area and bit size can be reduced by adding state machine, ROM table and simple control circuit.

Description

Digital audio signal decoding device

1 is a block diagram of a conventional digital audio signal decoding apparatus.

(A) of FIG. 2 is a structural diagram of a compressed bitstream of layer1.

(b) is a structural diagram of a compressed bitstream of layer2.

3 is a detailed block diagram of the bit layout data decoding unit and the sample data decoding unit in FIG.

4 is a format structure diagram of audio sample data.

5 is a detailed block diagram of the bit layout data decoding unit of the present invention.

6 is a detailed block diagram of a sample data decoding unit of the present invention.

7 is a grouping flow chart in sample data decoding.

8 is an input / output diagram of a romble for decoding grouping data.

* Explanation of symbols for main parts of the drawings

100: bit batch data decoding unit 200: sample data decoding unit

300: scale factor decoding unit 400: calculation unit

500: subband filter unit 110: table selection unit

120: Counter 130: Bit Batch Data Decoder

140: BPC converter 150: memory address generator

160: RAM 210: State Machine

220: lead address generation unit 230: light address generation unit

240: spl decoder 250: laysbl mode light unit

The present invention relates to a digital audio signal decoding apparatus. In particular, the digital audio signal decoding apparatus selects a table based on header information during bit layout data decoding, and converts the Nlevel output from the ROM into GPBC (Group Bits per Codeword). The present invention provides a digital audio signal decoding apparatus capable of reducing bit size and area.

FIG. 1 is a block diagram of a conventional digital audio signal decoder. When the formatted bitstream is input from the header information decoding unit, the bit layout data decoding unit 100 decodes and outputs the bit layout information.

In this case, the sample data decoding unit 200 decodes and outputs the sample data from the output signal of the bit batch data decoding unit 100, and the scale factor decoding unit 300 decodes and outputs the scale factor.

Then, the calculation unit 400 receives the output signals of the sample data decoding unit 200 and the scale factor decoding unit 300 and calculates and outputs them.

The subband filter unit 500 filters the output signal of the operation unit 400 and outputs PCM data.

At this time, a bitstream formatted in the layer1 method as shown in (a) of FIG. 2 or a bitstream formatted in the layer2 method as shown in (b) of FIG. 2 is input to the bitstream.

FIG. 3 is a detailed block diagram of the bit layout data decoding unit 100 and the sample data decoding unit 200.

First, a case in which a bitstream formatted in the layer1 method as shown in FIG. 2A is input will be described as an example.

The ROM 110 receiving the nbal signal from the header information decoding unit and the count signal from the counter 120 outputs a corresponding signal (group flag, nlevel).

That is, the ROM 110 converts the nlevel signal or bit per codeword (BPC) according to channels and subbands.

The nlevel signal is processed by the feedback loop of the ROM 240 and the multiplexer 230 three times to process the quotient and the remainder, and is then output as a signal sppl.

In addition, according to the value of the nlevel signal, the valid bit of the barrel shifter 210 is decoded through the state machine 220, and another loop is formed by grouping or nongrouping to form a sample value of the nlevel signal. Decode

At this time, in the case of the bit strip formatted in the layer 2 method, the subband value is decoded only within the bound.

4 is a format structure diagram of audio sample data. As shown in FIG. 4, each subband is included in 12 granules, and one subband has two channels of left and right when stereo.

However, in the case of mono, there is only one channel, in the joint mode (Joint Mode), there are two channels before the bound and only one channel after the bound.

At this time, in one channel, there are three samples in the case of the layer 2 method in the case of non-grouping, and one sample code in the case of grouping.

The layer2 audio data consists of three samples for one BPC value or one compressed sample code. One sample code is made of three samples, stored in a buffer and then calculated.

As described above, the conventional apparatus has a problem in that it is expensive and takes up a lot of area because many devices must be used.

An object of the present invention is to solve the problems of the prior art by selecting the table by the header information during decoding of the batch data in the digital audio data decompression process, and then converting the N level output by the ROM into GPBC. The present invention provides a digital audio signal decoding apparatus capable of reducing an area.

The digital audio signal decoding apparatus for achieving the object of the present invention is to select a table according to the bit rate and sampling frequency output from the header information decoding unit, and if the flag is generated according to the count signal, the bit is decoded to output the BPC signal A batch data decoding unit 100; A scale factor decoding unit 300 which receives the output signal of the bit batch data decoding unit 100 and decodes and outputs the scale factor; Receives the signal (gr) and the signal (Tableselect) from the bit batch data decoding unit 100, and controls the signal (splstart) and signal (datainen) from the scale factor decoding unit 300 through the ROM table to sample data A sample data decoding unit 200 for decoding and outputting the sample data; Comprising an output signal of the sample data decoding unit 200 and the scale factor decoding unit 300 is composed of a calculation unit 400 for outputting PCM data.

If the present invention is described with an embodiment as follows.

The overall block diagram and operation are as shown in FIG. Therefore, only the bit batch data decoding unit and the sample data decoding unit of the present invention will be described. 5 is a detailed block diagram of the bit layout data decoding unit 100 according to the present invention. As shown in FIG. Generating table selection unit 110; A counter 120 for outputting counter signals cnt2, cnt3 and cnt4 for generating a flag; A bit batch data decoder (130) for receiving the output signal of the table selecting unit (110) and decoding the bit batch data; A BPC converter 140 for converting the output signal of the bit batch data decoder 130 into a BPC signal; A memory address generator 150 for generating a memory address according to a flag signal of the bit batch data decoder 130; The RAM 160 stores data of the BPC converter 140 according to the address of the memory address generator 150.

The operation of the bit batch data decoding unit 100 configured as described above is as follows.

First, referring to the schematic operation, when header information (layer, bri, fsi, mode, modeext) is input, layer1 or layer2 is determined.

In case of layer1, nbal 4 bits allocated to 32 subbands are decoded to be converted to BPC and stored in RAM.

However, in the case of layer2, the table selector 110 selects a table according to the bit rate (4 bits) and the sampling frequency (2 bits). The mode (2 bits) and mode-ext (2 bits) determine the single, stereo or joint stereo mode.

If the joint stereo mode, the audio performance is increased and the bit rate is reduced to determine the bound to transmit.

When the bit allocation table is determined as described above, cnt2 sent from the counter 120 to decode the nbal signal (2, 3, 4 bits) allocated to each subband from the input bitstream after the signal (bital-start) , cnt3, cnt4 signal is controlled to be recognized according to the table.

A table selector generates a flag based on the cnt2, cnt3, and cnt4 signals, which are output signals of the counter 120, which decodes data in parallel from a serially input bitstream.

The data signal nbal decoded by the table selector 110 is decoded by the bit layout data decoder 130. The data signal nbal has a value of 0-15 and is used for quantization, which is a spectral component of each subband. Converts to an nlevel signal in the range 0-65535 of an unsigned integer.

After one table is determined, the number of cases of each nlevel signal coming out according to the index of the nbal signal for 32 subbands is 512.

At this time, the BPC conversion unit 140 receives the nlevel signal, converts it, outputs the grouping signal and the BPC signal, and writes it to the RAM 160.

The BPC converter 140 configures five function tables for converting the decoded nlevel signal into a BPC signal. The five function tables determine the function according to layer information, that is, layer1 or layer2.

On the other hand, the memory address generation unit 150 generates an address by selecting a table.

In this manner, after bit batch data decoding is completed, scale factor decoding is performed, and then decoding of sample data is started.

FIG. 6 is a detailed block diagram of the sample data decoding unit 200 according to the present invention. As shown therein, a signal (Tableselect) is input from a signal (gr) and a bit arrangement, and a signal (splstart) is output from the scale factor decoding unit. And a state machine 210 which receives a signal (datainen) capable of knowing whether data is valid and controls accordingly; A read address generator 220 generating a read address signal according to the output signal of the state machine 210; A light address generator 230 for generating a write address signal according to the output signal of the state machine 210; A multiplexer (240) for selecting and outputting an output signal of the read address generator (220) or the write address generator (230) according to the control signal of the state machine (210); A spl decoder 250 for decoding the spl signal according to the control signal of the state machine 210; The output signal of the multiplexer 240 and the output signal of the spl decoder 250 are input to constitute a laysbl mode light unit 260 for reading a sample and outputting signals (splramwin, ramaddr, wrspl, web, splend). .

The sample data decoding unit 200 configured as described above should receive and decode the header information (layer, mode, bri, fsi, mode-exe) output from the header information decoding unit when decoding the sample data. Since the table selection is determined in response to the header information in step 100), the table selection determined by the bit batch data decoding unit 100 is processed as an input to reduce the loss.

First, the state machine 210 is divided into a grouping flow and a non-grouping flow by a grouping signal of MSB 1 bit of the GBPC value read from the bit batch data decoding unit 100.

If nlevel is 3, 5, or 9 in the bitmap table, three consecutive samples are encoded into one codeword for one subband, and one codeword (5, 7, 10 bits) encoded is sample data. When decoding the codeword by recognizing the grouping in the decoding process, it generates three samples again.

In this case, the relationship between the codeword Cm (m = 3,5,9) and three consecutive subsamples S [0], S [1], S [2] in encoding is

to be.

And the algorithm applied in decoding

to be.

Conventionally, in FIG. 3, when an unsinged integer codeword is determined, in the case of grouping, the multiplexer and the ROM may be configured to generate three feedback loops to enable sample decoding of the quotient and the rest.

However, in the present invention, first, the gr signal, which knows 12 granules, and the tableselect signal in the bit arrangement are input from the state machine 210, and the splstart signal and data output from the scale factor decoding unit 300 are valid. It receives the datainen signal which can know whether it is known and controls accordingly.

According to the output signal of the state machine 210, the read address generator 220 and the write address generator 230 outputs the read or write address signal accordingly.

In this case, the multiplexer 240 selects and outputs an output signal of the read address generator 220 or the write address generator 230 according to the control signal of the state machine 210.

The spl decoder 250 receives the control signal of the state machine 210 and decodes the spl signal.

Then, the laysbl mode write unit 260 receives the output signal of the multiplexer 240 and the output signal of the spl decoder 250, reads a sample, and outputs signals (splramwin, ramaddr, wrspl, web, and splend).

The three sample generations for the grouping consisted of a simple ROM table as shown in FIG. 8, which shows the input / output diagram of the ROM table for decoding the grouping data. It is controlled by the output flag of 210 to sequentially generate three samples. The bit representations of the input and output are shown in ##.

The generated sample is stored in a buffer by an address generated by the write address generator 230.

In the non-grouping flow, the state machine 210 sequentially decodes the 16-bit datain signal by three correction signals. The LB latches the MSB from the 16-bit datain signal by the number of bits corresponding to the BPC.

If the BPC is zero, the samples of the subbands are stored as zero for filtering.

7 is a comparison of sizes of three generated samples [0], [1], and [2] for one codeword of a grouping flow.

As described above, in the decoding of the compressed audio data format, the present invention simplifies the signal flow of the system applied as the basic circuit structure by adding a state machine, a ROM table, and a simple control circuit, and reduces the area and bit size. It has an effect.

Claims (3)

A bit batch data decoding unit for selecting a table according to the bit rate and sampling frequency output from the header information decoding unit, decoding the flag when the flag is generated according to the count signal, and outputting the BPC signal; A scale factor decoding unit which receives an output signal of the bit batch data decoding unit and decodes and outputs a scale factor; Receives the signal (gr) and the signal (Tableselect) from the bit batch data decoding unit, and controls the signal (splstart) and signal (datainen) from the scale factor decoding unit through the ROM table to decode and output the sample data A data decoding unit; And a calculation unit for outputting PCM data by calculating an output signal of the sample data decoding unit and the scale factor decoding unit. 2. The apparatus of claim 1, wherein the bit layout data decoding section comprises: a table selection section for selecting a table according to a bit rate (4 bits) and a sampling frequency (2 bits) and generating a flag according to a count signal; A counter for outputting counter signals cnt2, cnt3, cnt4 for generating a flag; A bit batch data decoder which receives the output signal of the table selector and decodes the bit batch data; A BPC converter for converting the output signal of the bit batch data decoder into a BPC signal; A memory address generator for generating a memory address according to a flag signal of the bit batch data decoder; And a RAM for storing data of the BPC converter according to the address of the memory address generator. The method of claim 1, wherein the sample data decoding unit receives a signal (gr) and a signal (Tableselect) from the bit batch data decoding unit, and receives a signal (splstart) and a signal (datainen) from the scale factor decoding unit according to A state machine for controlling; A read address generator for generating a read address signal according to the output signal of the state machine; A write address generator for generating a write address signal according to the output signal of the state machine; A multiplexer for selecting and outputting an output signal of the read address generator or the write address generator according to the control signal of the state machine; A spl decoder for decoding the spl signal according to the control signal of the state machine; And a laysbl mode light unit configured to output a signal (splramwin, ramaddr, wrspl, web, splend) by reading the output signal of the multiplexer and the output signal of the spl decoder.