KR100201413B1 - Sample decoding of digital audio decoder - Google Patents

Abstract

The present invention relates to a sample decoding circuit of a digital audio decoder, and in particular, to add a simple control circuit and replace it with a simple ROM table to improve the integration rate and the processing speed of the circuit. The present invention is a RAM 202 for outputting the codeword information (BPC) to the control signal (REN) and the address (ADDR) of the address generation block 201, and the code for each frequency band of the RAM (202) State machine control for outputting ROM address RADDR with input information switching block 203 for converting word information BPC into group division information NBPC and output information NBPC of this information switching block 273 A block 204, a first sample decoding block 205 for performing group decoding by reading the data according to the ROM address RADDR of the state machine control block 204, and non-group decoding by the request signal REQ. The second sample decoding block 206 performs the selection, and selects one of the output data of the first and second sample decoding blocks according to the most significant bit MSB of the group division information NBPC, thereby obtaining the final sample data Sdata. The multiplexer 207 outputting the multiplication unit 207 and bit allocation data Bi are converted into parallel data. A control block 208 for converting and outputting to the first and second sample decoding blocks and controlling the state machine control block 274 and the first and second sample decoding blocks 205 and 206 to perform a sample decoding operation. ).

Description

Sample Decoding Circuit of Digital Audio Decoder

The present invention relates to a digital audio decoder, and more particularly, to a sample decoding circuit of a digital audio decoder which simply constitutes a circuit for decoding compressed audio data.

In general, when the analog signal is converted into a digital signal and transmitted, the bit rate is high and the bandwidth is large. Therefore, a technique for reducing the bit rate is required. For this purpose, the encoder applies a mathematical conversion algorithm of the digital audio signal.

The encoder applying this technique divides the input audio signal into arbitrary frequency bands and converts the signals into time / frequency domains, and encodes coefficient data of the converted blocks and transmits them in one frame structure.

In addition, the digital audio decoder applies MPEG technology, which is a standard specification of a compressed audio signal, which is applied to the storage of the digital signal and the sound transmission on the digital channel, and is adaptive to the digital audio signal allocated to the frequency domain. It has to do with bit allocation, which enables quantization.

In general, a digital audio decoder outputs bit allocation data Bi and codeword information BPC by dividing and decoding data Di of a bit stream by frequency band, as shown in the block diagram of FIG. A sample decoding circuit 102 for decoding the bit allocation data Bi according to the codeword information BPC of the bit allocation unit 101, and outputting the sample data Sdata, and this sample. A quantizer 103 for requantizing the sample data Sdata of the decoding circuit 102 and a scale for extracting a scale factor as an input from the output signal of the bit allocation unit 101 and outputting the scale factor to the quantizer 103. A factor decoding unit 105 and a subband filter unit 104 for subband filtering the output signal of the quantization unit 103 to output PCM data Dout.

The operation of such a general digital audio decoder is described as follows.

First, when the data (Din) formatted by the encoder is input to the bit stream condition, the bit allocation unit 101 detects the header information, divides the data into frequency bands, decodes the divided data, and allocates the bit allocation data and the codeword information (BPC). Bits per Codeuurd) is output to the sample decoding circuit 102 and the scale factor decoding unit 105.

In this case, the sample decoding circuit 102 decodes the bit allocation data according to the output information BPC of the bit allocation unit 101 and outputs sample data Sdata to the quantization unit 103. 105 decodes the scale factor as the input of the bit allocation data and outputs the decoded scale factor to the quantization unit 103.

Accordingly, when the quantization unit 103 requantizes the sample data Sdata of the sample decoding circuit 102 with the output signal of the scale factor decoding unit 105 as input, the subband filter 104 performs subband filtering to perform the PCM. Data Dout is output.

The conventional sample decoding circuit includes registers 111 to 113 for sequentially storing bit allocation data Bi, a register 114 for temporarily storing codeword information BPC, as shown in FIG. A multiplexer 116 for selectively outputting one of sample data Cm before decoding and output data of the register 111, a register 117 for storing output data of the multiplexer 117, and the register ( ROM (ROM) 115 for outputting the sample data Cm before decoding with input of the output data of 114) and the sample data S [i] to be decoded with the output data of the register 118 as input. And a multiplexer 118 that selects one of the output data S [i] of the ROM 115 and the output data of the register 113 to output sample data Sdata.

Referring to the operation of the prior art as follows.

First, the codeword information BPC by bit-allocating and decoding the input data Di of the bit stream condition is stored in the register 114, and the bit allocation data Bi is stored in the register 111 and sequentially registered. 112) (113).

At this time, the ROM 115 outputs the sample data Cm before decoding to the multiplexer 110 by the output information BPC of the register 114.

Accordingly, the multiplexer 115 selects one of the output data of the register 111 and the output data Cm of the ROM 115 and stores it in the register 117.

At this time, the ROM 115 outputs sample data S (i) by inputting the output data of the register 117.

Therefore, the sample data Sdata is decoded by the multiplexer 118 selecting and outputting one of the output data of the register 113 and the output data S [i] of the name 115.

In the above, the loop is formed by the codeword information (BPC) of each frequency band to decode the final sample data value.

For example, in a decoding operation in which three samples are configured for one frequency section according to codeword information (BPC) or three samples are encoded into one compressed data, three feedback loops are generated to make one sample. Will form.

The algorithm applied in this case is as follows.

for (i = 0; i3; i ++)

{S [i] = Cm% BPC

Cm = Cm DIV BPC}

Here, S (i): sample data to be decoded, Cm: sample data before decoding which is 3, 5, 9 bits,%: quotient, and DIV: remainder by division.

However, such a prior art has a problem that the integration area is increased by using many elements in the system design for the digital signal processing, and the design is complicated and the processing speed is reduced.

The present invention improves the circuit integration rate and processing speed by adding a simple control circuit and replacing the structure of the system adapted to the basic circuit structure in decoding the compressed audio data with a simple ROM table in order to improve the disadvantage of the prior art. It is an object to provide a sample decoding circuit of a digital audio decoder devised to improve.

1 is a block diagram of a general digital audio decoder.

2 is a block diagram of a conventional sample decoding circuit.

3 is a block diagram of an embodiment according to the present invention.

4 is a detailed block diagram of an information switching block in FIG.

5 is a detailed block diagram of the first sample decoding block in FIG.

* Explanation of symbols for main parts of the drawings

201: address generation block 202: RAM

203: information switching block 204: state machine control block

205,206: sample decoding block 207,216: multiplexer

208: control block 211 to 215: function converter

217: selection signal generator 221: ROM

In order to achieve the above object, the present invention is operated by an address generation block that generates bit enable data and an address frame according to header information as input of bit allocation data, and a chip enable signal of the address generation block. Data storage means for outputting codeword information in an area designated by an address, an information switching block for converting codeword information for each frequency band of the data storage means into group classification information, and output information of this information switching block; A state machine control block for performing a state machine operation to output a ROM address, a first sample decoding block for generating three samples according to the ROM address of the state machine control block and performing group decoding of parallel input data; A second sample decoding block for performing non-group decoding of parallel input data, and said group A multiplexer for selecting one of the output data of the first and second sample decoding blocks according to the most significant 1 bit of minute information and outputting the final sample data, converting bit allocation data into parallel data, and converting the state machine control block and It consists of a control block for controlling the first and second sample decoding blocks.

Hereinafter, the present invention will be described in detail with reference to the drawings.

According to an embodiment of the present invention, as shown in the block diagram of FIG. 3, the control signal REN and the address ADDR according to the header information bri, psi, iode, and mode-ext are inputted with the bit allocation data Bi. Is generated by the address generating block 201 and the control signal REN of the address generating block 201, and outputs the codeword information BPC in the region designated by the address ADDR. RAM) 202, an information switching block 203 for converting codeword information (BPC) for each frequency band of the RAM 202 into group division information (NBPC) as an input, and this information switching block 203 A state machine control block 204 for outputting a ROM address RABDR by performing a state machine operation with the output information NBPC of FIG. 3 and a ROM address of the state machine control block 204. A first sample decoding block 205 for generating two samples and performing group decoding of parallel input data; A second sample decoding block 206 for performing non-group decoding of parallel input data by a signal REQ, and the first and second sample decoding blocks according to the most significant bit MSB of the group division information NBPC. A multiplexer 207 which selects one of the output data of the output data of 205 and 206 and outputs it as the final sample data Sdata; and converts the bit allocation data Bi into parallel data, and converts the state machine control block 204 and The control block 208 controls the first and second sample decoding blocks 205 and 206.

As shown in the block diagram of FIG. 4, the information switching block 203 includes function converters 211 to 215 for converting code information for each frequency band of the RAM 202 into inputs for group classification, respectively; A multiplexer 216 for selecting one of the output information of the function converters 211 to 215 and outputting it as group division information (NBPC), and a selection signal generator 217 for outputting a selection signal to the multiplexer 216. do.

As shown in the block diagram of FIG. 5, the first sample decoding block 205 includes a ROM 221 for outputting data in a region designated by the output address RADDR of the state machine control block 204; The shifter 222 outputs three sample data S [0], S [1], and S [2] by performing a shift operation on the output data of the ROM 221.

Referring to the operation and effect of the embodiment of the present invention configured as described above are as follows.

The address generation block 201 reads the header information bri, fsi, mode, and mode-ext to generate the control signal REN and the address ADDR by inputting the bit allocation data Bi. The control signal REN is enabled to output codeword information BPC for each frequency band in a region designated by the address ADDR.

The bitword per codeword (BPC) is a value generated by an index value allocated for 32 frequency bands and indicates the number of bits of an actual sample.

In this case, the information conversion block 203 receives the output information BPC of the RAM 202 and the multiplexer 216 selects the function converters 211 to 215 converting codeword information of the corresponding frequency band into group classification information. The output signal of the signal generator 217 selects one of the output information of the function converters 211 to 215 and outputs it as group division information (NBPC) that can distinguish a group from a nongroup. .

The function converters 211 to 215 have the same characteristics as the corresponding frequency bands, and the most significant bit MSB of the group division information NBPC acts as a signal for selecting final sample data.

The control block 208 converts the bit allocation data Bi into parallel data as an input and outputs a sample start signal, an interval signal, and a request signal REQ.

Therefore, the state machine control block 204 that receives the group division information (NBPC) of the information switching block 203 receives the state of the group division information (NBPC) according to the sample start signal and the section signal of the control block 208. The machine operation is performed to output the ROM address RADDR to the first sample decoding block 205.

In this case, the first sample decoding block 205 outputs 12-bit data of the corresponding region from the ROM 221 receiving the ROM address RADDR, and the shifter 222 receiving the 12-bit data is controlled by the control block 208. The shift operation is performed by inputting parallel data at S3 to sequentially output three pieces of sample data S [0], S [1], and S [2].

That is, three sample data S [0], S [1], and S [2] are sequentially decoded by generating three flags by decrypting the 12-bit data of the ROM 221.

Here, if the number of input bits is 5, 7, 10 bits in group decoding, the number of three sample bits after decoding is increased to 6, 9, 12 bits.

In addition, the second sample decoding block 206 decodes 16-bit data according to the request signal REQ of the control block 208 by inputting parallel data.

Accordingly, the multiplexer 207 selects one of the output data of the first and second sample decoding blocks 205 and 206 by the most significant bit MSB of the group division information NBPC of the information switching block 209. Output sample data.

As described in detail above, the present invention has the effect of improving the integration rate of the circuit and improving the processing speed by adding a simple control circuit and replacing it with a simple ROM table.

Claims (4)

An address generation block for generating the control signal REN and the address ADDR according to the header information bri, fsi, mode, mode-ext with the bit allocation data Bi as an input; Data storage means for enabling the control signal REN to output codeword information BPC in a region designated by the address ADDR, and codeword information BPC for each frequency band of the data storage means. An information switching block for switching to division information (NBPC), a state machine control block for outputting a ROM address (RADDR) by performing a state machine operation on the output information (NBPC) of the information switching block, and this state machine control A first sample decoding block that reads data by the ROM address RADDR of the block to perform group decoding, a second sample decoding block which performs non-group decoding by the request signal REQ, and the group classification information NBPC Best of) A multiplexer that selects one of the output data of the first and second sample decoding blocks according to the bit MSB and outputs the final sample data Sdata, and QUSGHKS the bit allocation data Bi as parallel data. And a control block for outputting to the first and second sample decoding blocks and controlling the state machine control block 204 and the first and second sample decoding blocks 205 and 206 to perform a sample decoding operation. Sample decoding circuit of digital audio decoder. The information converting block according to claim 1, wherein the information switching block includes first to fifth function converters for converting code information for each frequency band of the data storage means into group classification information as inputs, and the outputs of the first to fifth function converters. And a multiplexer which selects one of the pieces of information and outputs it as group division information (NBPC), and a selection signal generator for outputting a selection signal to the multiplexer. The sample decoding circuit of a digital audio decoder according to claim 2, wherein the first to fifth function converters have the same characteristics as the corresponding frequencies. The ROM of claim 1, wherein the first sample decoding block shifts the ROM outputting data in a region designated by the output address RABDR of the state machine control block, and shifts the output data of the ROM into input. And a shifter for outputting three sample data (S [0], S [1], S [2]) by performing the following steps.