KR100197993B1 - Dual column redundancy circuit of a semiconductor memory device - Google Patents

Abstract

The present invention relates to a dual column redundancy circuit, and more particularly, to a dual column redundancy circuit for compensating for a defect occurring in a repaired column line again. A brow block selection fuse box means for selecting a block, a first repair column selection fuse box means for replacing with a repair column line when a normal column line selection signal is applied, and an output signal of the first repair column selection fuse box part; A third delay circuit means for outputting to the input terminals of the third and fourth end circuit portions by delaying a predetermined time and a read operation enable signal and a write operation enable signal as inputs; 2 read and write operation circuit means, and an output signal of the third delay circuit portion Third end circuit means for outputting a first repair column line selection signal by inputting an output signal of the second read and write operation circuit portion and an output signal of the second repair column fuse box portion, and the third delay circuit portion; Fourth end circuit means for outputting a second repair column line selection signal by inputting an output signal, an output signal of the second read and write operation circuit part, and another output signal of the second repair column fuse box part; The repair column line is also defective, and a low signal on the first node is input to one input terminal of the third and circuit part to replace the second repair column line, thereby disabling the first repair column line selection signal and then on the second node. A high signal is input to one input terminal of the fourth end circuit portion to enable the second repair column line selection signal. 2 provided with a repair column fuse box means.

Description

Dual Column Redundancy Circuit in Semiconductor Memory Devices

1 is a repair column redundancy circuit according to the prior art.

2 is a dual column redundancy circuit diagram according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

3-1: First Repair Column Selection Fuse Box Part

10: second repair column selection fuse box portion

7: first lead and write operation circuit

7-1: Second lead and write operation circuit

5: first delayed inverter section 6: second delayed inverter section

5-1: Third delay inverter section 8: First logic circuit section

9: 2nd logic circuit part 8-1: 3rd logic circuit part

9-1: 4th logic circuit part A: read operation enable signal

B: Write operation enable signal

RYi0: first repair column line selection signal

RYi1: second repair column line selection signal

Vcc: power supply voltage Vss: ground voltage

F: Fuse for second repair MP1: PMOS transistor

MN1 to MN2: NMOS transistor

IV1 to IV23: Inverter NR1 to NR3: Noah gate

ND1 to ND4: NAND gate

The present invention relates to a dual column redundancy circuit of a semiconductor memory device, and more particularly, to a dual column redundancy circuit for replacing a repaired column line with another repair column line when a defect occurs.

In general, a redundancy operation is performed through a repair fuse box to compensate for a defect in any normal word line or any normal column line of the semiconductor memory device.

FIG. 1 is a repair column redundancy circuit diagram according to the prior art, wherein the brow block selection fuse box parts 1 and 2 for selecting an arbitrary sub block by a word line selection signal, and a normal column line selection signal are provided. When applied, the repair column selection fuse box parts 3 and 4 for replacing with the repair column line, and the output signal of the repair column selection fuse box parts 3 and 4 are delayed for a predetermined time so that the first logic circuit part 8 and The first delay inverter unit 5 and the second delay inverter unit 6 for outputting to the input terminal of the second logic circuit unit 9, the read operation enable signal A and the write operation enable signal B The first read and write operation circuit 7 for outputting the logically calculated value as an input to the input terminal of the first logic circuit section 8 and the input terminal of the second logic circuit section 9 to perform the column-side operation. The first or second delay inverter unit A first or second end circuit section 8, 9 for outputting a repair column line selection signal by inputting the output signal of (5, 6) and the output signal of the first read / write operation circuit section 7 as an input. do.

Hereinafter, the operation according to the configuration will be described.

For example, when the corresponding address fuses of the brow block selection fuse box unit 1 and the repair column selection fuse box unit 3 are cut, first, the word line selection signal is selected to select the brow block selection fuse box unit 1 and the brow block selection unit. When input to the fuse box 2, a high signal is output at the output terminal of the brow block selection fuse box unit 1, and a low signal is output at the output terminal of the brow block selection fuse box unit 2. do. Subsequently, when a normal column line selection signal is input to the repair column selection fuse box unit 3 and the repair column selection fuse box unit 4, a high signal is output to an output terminal of the repair column selection fuse box unit 3. A low signal is output to an output terminal of the repair column select fuse box unit 4.

Subsequently, the high signal of the repair column select fuse box unit 3 is delayed by the first delay inverter unit 5 for a predetermined time, and then a high signal is input to the input terminal of the first logic circuit unit 8. The low signal of the repair column select fuse box unit 4 is delayed by the second delay inverter unit 6 for a predetermined time, and then a low signal is input to the input terminal of the second logic circuit unit 9. Subsequently, a low, which is an enable signal A during a read operation, and a high, which is an enable signal B, during a write operation, are input to an input terminal of the first read and write operation circuit 7 to perform the read operation. Low, which is the enable signal A, is connected to three inverters IV5, IV6, and IV7 connected in series, and a high signal is applied to one of the first and second noah gates NR1 and NR2. The high signal, which is input to the input terminal and the enable signal B during a write operation, passes through two inverters IV8 and IV9 connected in series and a high signal is transmitted to the first NOR gate NR1 and the second. A low signal is input to the input terminals of the tenth inverter IV10 and the eleventh inverter IV11, respectively, by being input to one input terminal of the NOR gate NR2. The low signal input to the input terminals of the tenth inverter IV10 and the eleventh inverter IV11 is inverted by the tenth inverter IV10 and the eleventh inverter IV11, respectively, and thus a high signal. Is input to the input terminals of the first NAND gate ND1 and the second NAND gate ND2. As a result, a high signal that is an output signal of the first read and write operation circuit 7 and a high signal of the first delay inverter 5 are input to the first logic circuit 8. The logic operation is performed to output the first repair column line selection signal. On the other hand, the high signal, which is an output signal of the first read and write operation circuit unit 7, and the low signal, which is an output signal of the second delay inverter unit 6, are connected to the second logic circuit unit 9. It is input to the logic operation and outputs a low signal so that it does not generate a signal for selecting a repair column line. Similarly, when the address fuses of the brow block selection fuse box portion 2 and the repair column selection fuse box portion 4 are cut off, the output signal of the second logic circuit portion 9 becomes high and the Since the output signal of the first logic circuit unit 8 becomes low and the repair process through the second logic circuit unit 9 is performed, the description thereof will be omitted.

However, if a repair occurs even in the repair column line described above, since the fuse is cut in the conventional column redundancy circuit, a signal for enabling the repair column line in which the defect occurs is continuously operated to prevent further repair. do. That is, the conventional column repair method has a problem in that the repair of the device itself can not be performed any more if the replaced part is also defective by performing column repair.

Accordingly, an object of the present invention is to provide a dual column redundancy circuit for compensating for a defective repair column line.

The dual column redundancy circuit of the present invention for achieving the above object comprises a brow block selection fuse box means for selecting an arbitrary brow block by a word line selection signal and a replacement column line when a normal column line selection signal is applied. A first delay column selection fuse box means, a third delay inverter means for outputting the output signal of the first repair column selection fuse box portion to the input terminals of the third end circuit portion and the fourth end circuit portion for a predetermined time, and a lead; A second read and write operation circuit for outputting a logic operation value as an input of an operation enable signal and a write operation enable signal to an input terminal of the third and circuit part and an input terminal of the fourth and circuit part for performing the column side operation. Means, an output signal of the third delay inverter unit, and the second read and write operation circuit unit. A fourth end circuit means for outputting a second repair column line selection signal by inputting an output signal and another output signal of the second repair column fuse box unit, and the first repair column line is also defective to generate a second repair column. To replace the line, the low signal on the first node is input to one input terminal of the third and circuit portion to disable the first repair column line selection signal, and the high signal on the second node to one input terminal of the fourth and circuit portion. And a second repair column fuse box means for inputting to enable the second repair column line selection signal.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a dual column redundancy circuit diagram according to an embodiment of the present invention, in which a brow block selection fuse box unit 1-1 for selecting an arbitrary brow block by a word line selection signal and a normal column line selection signal are provided. When applied, the third logic circuit unit is configured to delay the output signal of the first repair column select fuse box unit 3-1 and the first repair column select fuse box unit 3-1 for replacing the repair column line by a predetermined time. Third delay inverter section 5-1 for outputting to the input terminals of the 8-8 and the fourth logic circuit section 9-1, the read operation enable signal A and the write operation enable signal B Second read and write operation for outputting the logically calculated value to the input terminal of the third logic circuit section 8-1 and the input terminal of the fourth logic circuit section 9-1 to perform the column side operation. The circuit section 7-1 and the output signal of the third delay inverter section 5-1 An output signal of the second read / write operation circuit unit 7-1 and an output signal of the second repair column fuse box unit 10 as an input to output the first repair column line selection signal RYi0; Third logic circuit section 8-1, the output signal of the third delay circuit section 5-1, the output signal of the second read and write operation circuit section 7-1, and the second repair column fuse box section 10 A fourth logic circuit 9-1 for outputting the second repair column line selection signal RYi1 by inputting another output signal of < RTI ID = 0.0 >) < / RTI > and the first repair column line are also defective to generate a second repair column line. The low signal on the first node N1 is input to one input terminal of the third logic circuit 8-1 to disable the first repair column line selection signal RYi0. A high signal on the second node N2 is input to one input terminal of the fourth logic circuit 9-1. The second repair is a column line select signal (RYi1) configured to enable (Enable), a second column repair fuse box unit 10 for.

The third delay inverter part 5-1 is composed of two fourteenth and fifteenth inverters IV14 and IV15 connected in series.

The second read and write operation circuit 7-1 may include three inverters IV16 connected in series for delaying the read operation enable signal A for a predetermined time and outputting the same to one input terminal of the third NOR gate NR3. , IV17 and IV18 and two inverters IV19 and IV20 connected in series for outputting the write operation enable signal B to a single input terminal of the third NOR gate NR3 by a predetermined time delay. .

The second repair column fuse box 10 is connected between the power supply voltage Vcc and the first node N1 to disable the first repair column line selection signal RYi0 and to perform a second repair column line selection signal ( A second repair fuse F for enabling RYi1 and a signal on the second node N2 are applied to the gate, and are connected between the first node N1 and the ground voltage Vss to perform a second repair operation. A first NMOS transistor MN1 for transferring the ground voltage Vss to one input terminal of the third NAND gate ND3 of the third logic circuit 8-1 and a first node N1 as a gate. Signal is applied and is connected between the power supply voltage Vcc and the second node N2 to convert the power supply voltage Vcc to the first NMOS transistor MN1 and the fourth logic during a second repair operation. A first PMOS transistor MP1 for transferring to one input terminal of the fourth NAND gate ND4 of the circuit section 9-1, and the gate The signal on the first node N1 is applied and is connected between the second node N2 and the ground voltage Vss to convert the ground voltage Vss to the fourth logic circuit 9-9 during the first repair operation. A second NMOS transistor MN2 for transferring to one input terminal of the fourth NAND gate ND4 of 1).

The third logic circuit unit 8-1 may output an output signal of the third delay inverter unit 5-1, an output signal of the second read and write operation circuit unit 7-1, and the second repair column fuse box. A third NAND gate ND3 and a third NAND gate for outputting a logically calculated value as an input terminal of the 22nd inverter IV22 by inputting an output signal on the first node N1 of the unit 10 as an input; And a twenty-second inverter IV22 for inverting the output signal of ND3 and outputting the first repair column line selection signal RYi0.

The fourth logic circuit unit 9-1 may include an output signal of the third delay circuit unit 5-1, an output signal of the second read and write operation circuit unit 7-1, and the second repair column fuse box unit. A fourth NAND gate ND4 for outputting a logically calculated value by inputting the output signal on the second node N2 of (10) to an input terminal of the twenty-third inverter IV23, and the fourth NAND gate ( And a twenty-third inverter IV23 for inverting the output signal of the ND4 to output the second repair column line selection signal RYi1.

In the operation according to the above configuration, a word line selection signal is input, a high signal for selecting a brow block is output by the brow block selection fuse box unit 1-1, and the first repair column selection fuse box unit 3 is output. When a defect occurs in the first normal column line when -1) is precharged, when the normal column line selection signal for selecting the first normal column line is applied, the first repair column selection fuse box part 3- The corresponding fuse in 1) is cut off to prevent the precharged signal from falling low. Therefore, a high signal is output to an output terminal of the first repair column selection fuse box unit 3-1, and the high signal is an input terminal of the third delay inverter unit 5-1. It is an input. Subsequently, the high signal delayed by the third delay inverter unit 5-1 for a predetermined time is input to the input terminals of the third logic circuit unit 8-1 and the fourth logic circuit unit 9-1. . Subsequently, the read operation enable signal A for notifying the read operation of the second read and write operation circuit 7-1 is low, and the write operation enable signal B for notifying the write operation is high ( The read operation enable signals A are respectively inputted as high and are delayed for a predetermined time by three inverters IV16, IV17, and IV18, and a high signal is input to one input terminal of the third NOR gate NR3. The write operation enable signal B is delayed for a predetermined time by two inverters IV19 and IV20 to output a high signal to one input terminal of the third NOR gate NR3. Subsequently, each of the high read and write operation enable signals A is logically operated on the third NOR gate NR3 so that a low signal is input to an input terminal of the twenty-first inverter IV21. Inverted by the inverter IV21, a high signal is inputted to one input terminal of the third NAND gate ND3 of the third logic circuit 8-1 and the fourth NAND of the fourth logic circuit 9-1. Input is made to one input terminal of the gate ND4. On the other hand, in the first repair operation, since the second repair fuse F of the second repair column fuse box part 10 is not blown, a high signal appears at the first node N1. The second NMOS transistor MN2 is turned on so that the ground voltage Vss is input to the input terminal of the fourth NAND gate ND4 of the fourth logic circuit 9-1 through the second node N2. The high signal on the first node N1 is input to the input terminal of the third NAND gate ND3 of the third logic circuit 8-1. As a result, two high signals and one low signal input to three input terminals of the fourth NAND gate ND4 of the fourth logic circuit unit 9-1 may be applied to the fourth NAND gate ND4. The high repair signal is outputted to the output terminal of the fourth logic circuit unit 9-1 by outputting a high signal and a high signal is outputted to the output terminal of the fourth logic circuit unit 9-1. Not done. Meanwhile, three high signals input to the three input terminals of the third logic circuit unit 8-1 are logically operated by the third NAND gate ND3 to output a low signal, and a twenty-second inverter. The first repair operation is performed by inverting the output signal IV22 and outputting the high signal.

Meanwhile, the second repair operation is performed by cutting the second repair fuse F of the second repair column fuse box part 10, which will be described.

First, a word line selection signal is input, a high signal for selecting a brow block is output by the brow block selection fuse box unit 1-1, and the first repair column selection fuse box unit 3-1 is output. When the normal column line selection signal is input in the precharged state, the corresponding fuse of the first repair column selection fuse box unit 3-1 is still cut, and thus the first repair column selection fuse box unit 3-1 of A high signal is still output to the output terminal, and the high signal is delayed for a predetermined time by the third delay inverter unit 5-1, and then a high signal is output to the third logic circuit unit 8-1. ) And the fourth logic circuit section 9-1.

Similarly, the low read operation enable signal A and the high write operation enable signal B, which are input to the two input terminals of the second read and write operation circuit unit 7-1, undergo a predetermined time delay process. The third signal is input to the NOR gate NR3 and inverted by the twenty-first inverter IV21 to input a high signal to the input terminal of the third logic circuit part 8-1 and the input terminal of the fourth logic circuit part 9-1. .

On the other hand, since the second repair fuse F is cut in the second repair column fuse box part 10, a low signal appears on the first node N1, and the low signal corresponds to the first PMOS transistor ( The power supply voltage Vcc is transmitted to the second node N2 by turning on MP1. Subsequently, the high signal on the second node N2 turns on the first NMOS transistor MN1 so that the ground voltage Vss is transmitted through the first NMOS transistor MN1. The high signal on the second node N2 is input to the fourth NAND gate ND4 of the fourth logic circuit 9-1. As a result, two high signals and one low signal input to the third NAND gate ND3 of the third logic circuit unit 8-1 are logically operated by the third NAND gate ND3 so that a high signal is generated. The first repair column line is not selected by being input to the 22nd inverter IV22 and inverted by the 22nd inverter IV22 to output a low signal. Meanwhile, three high signals input to the fourth NAND gate ND4 of the fourth logic circuit unit 9-1 may be logically operated by the fourth NAND gate ND4, thereby providing a low signal. The second repair column line is selected by being input to the input terminal of the twenty-third inverter IV23 and inverted by the twenty-third inverter IV23 to output a high signal. As described above, if the dual column redundancy circuit of the present invention is implemented in a semiconductor memory device such as a DRAM, it can be repaired again even if any defect occurs in the repaired column line, thereby increasing the success rate of the repair and increasing the yield. It is effective.

Preferred embodiments of the present invention are for purposes of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

Claims (4)

A brow block selection fuse box means for selecting an arbitrary brow block by a word line selection signal, a first repair column selection fuse box means for replacing with a repair column line when a normal column line selection signal is applied, and the first A third delay circuit means for delaying an output signal of the repair column selection fuse box unit by a predetermined time and outputting the same to an input terminal of the third logic circuit unit and the fourth logic circuit unit, and a read operation enable signal and a write operation enable signal as inputs; Second read and write operation circuit means for performing the column side operation, an output signal of the third delay circuit part, an output signal of the second read and write operation circuit part, and an output signal of the second repair column fuse box part. Third logic circuit means for outputting a first repair column line selection signal as an input, and said third delay And fourth logic circuit means for outputting a second repair column line selection signal by inputting an output signal of the furnace section, an output signal of the second read and write operation circuit section, and another output signal of the second repair column fuse box section. In a dual column redundancy circuit of a semiconductor memory device, the first repair column line is also defective, so that the signal on the first node is replaced by one input terminal of the third logic circuit to replace the second repair column line. A second repair column fuse box means for inputting and disabling the first repair column line selection signal, and a signal on the second node being input to one input terminal of the fourth logic circuit portion to enable the second repair column line selection signal. Dual column redundancy circuit comprising. 2. The second repair column fuse means of claim 1, wherein the second repair column fuse means is connected between a power supply voltage and a first node to disable the first repair column line selection signal and to enable the second repair column line selection signal. A fuse on the second node is applied to the gate and is connected between the first node and the ground voltage to transfer the ground voltage to one input terminal of the third NAND gate of the third logic circuit in the second repair operation. A signal on a first node is applied to a transistor and a gate, and is connected between the power supply voltage and the second node to supply the power supply voltage to the fourth NAND gate of the first transistor and the fourth logic circuit in a second repair operation. A transistor for transferring to one input terminal, and a signal on the first node is applied to a gate and is connected between the second node and the ground voltage And a transistor for transmitting the ground voltage to one input terminal of a fourth NAND gate of the fourth logic circuit unit during a first repair operation. The third node of claim 1, wherein the first node of the second repair column fuse box unit is connected to an input terminal of a third NAND gate of the third logic circuit unit, and the second node is connected to a third NAND gate of the fourth logic circuit unit. A second repair column fuse box means, connected to one input terminal. 3. The transistor of claim 2, wherein the transistor connected between the first node and the ground voltage is an NMOS transistor and the transistor connected between the power supply voltage and the second node is a PMOS transistor and the second node and the ground voltage. The second repair column fuse box means characterized in that the transistor connected between is an NMOS transistor.