KR100197670B1 - Method for forming a contact hole of a semiconductor device - Google Patents
Method for forming a contact hole of a semiconductor device Download PDFInfo
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- KR100197670B1 KR100197670B1 KR1019960024243A KR19960024243A KR100197670B1 KR 100197670 B1 KR100197670 B1 KR 100197670B1 KR 1019960024243 A KR1019960024243 A KR 1019960024243A KR 19960024243 A KR19960024243 A KR 19960024243A KR 100197670 B1 KR100197670 B1 KR 100197670B1
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- insulating layer
- forming
- lower insulating
- semiconductor device
- contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 반도체소자의 콘택홀 형성방법에 관한 것으로, 1. 반도체기판 상부에 하부절연층을 형성하고 상기 하부절연층을 형성한 다음, 상기 하부절연층 상부에 감광막패턴을 형성하고 상기 감광막패턴을 마스크로하여 상기 반도체기판을 노출시키는 반도체소자의 콘택홀 형성방법에 있어서, 상기 반도체기판을 일정압력의 반응로에 주입하고, 상기 반응로에 H2O 베이퍼와 HF 베이퍼을 주입하여 상기 H2O 베이퍼 및 HF 베이퍼를 상기 하부절연층과 반응시킴으로써 상기 하부절연층을 등방성식각한 다음, 상기 감광막패턴을 마스크로하여 불소계 플라즈마를 이용한 식각공정으로 상기 하부절연층을 식각하여 콘택홀을 형성하고, 상기 등방성식각공정의 잔유물을 순수로 세척하여 단차 피복비가 향상된 콘택홀을 형성할 수 있어 콘택저항을 감소시키고 후속공정을 용이하게 실시하여 반도체소자의 특성 및 신뢰성을 향상시키고, 반도체소자의 수율 및 생산성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.The present invention relates to a method for forming a contact hole in a semiconductor device, comprising: 1. forming a lower insulating layer on a semiconductor substrate, forming the lower insulating layer, and then forming a photoresist pattern on the lower insulating layer, In the method for forming a contact hole of a semiconductor device to expose the semiconductor substrate as a mask, the semiconductor substrate is injected into a reactor of a constant pressure, H 2 O vapor and HF vapor is injected into the reactor to the H 2 O vapor And isotropically etching the lower insulating layer by reacting HF vapor with the lower insulating layer, and then forming the contact hole by etching the lower insulating layer by an etching process using a fluorine-based plasma using the photoresist pattern as a mask. By cleaning the residue of the etching process with pure water, it is possible to form a contact hole with improved step coverage. It is a technology that facilitates the subsequent process to improve the characteristics and reliability of the semiconductor device, improve the yield and productivity of the semiconductor device, and thereby high integration of the semiconductor device.
Description
제1도는 종래기술에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method for forming a contact hole in a semiconductor device according to the prior art.
제2a도 및 제2b도는 본 발명의 실시예에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도.2A and 2B are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,31 : 반도체기판 13,33 : 하부절연층11,31: semiconductor substrate 13,33: lower insulating layer
15,35 : 감광막패턴 17,37 : 제1언더컷15,35 photoresist pattern 17,37 first undercut
19,39 : 제2언더컷 21,41 : 콘택홀19,39: 2nd undercut 21,41: contact hole
본 발명은 반도체 소자의 콘택홀 형성방법에 관한 것으로, 건식식각공정만으로 상측부가 넓은 콘택홀을 형성하여 단차피복비를 향상시킴으로써 반도체소자의 특성을 향상시키고 그로인한 반도체소자의 신뢰성을 향상시키는 동시에 반도체소자의 고집적화를 가능하게 하는 기술에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device, and by forming a contact hole having a wide upper portion by only a dry etching process, thereby improving the step coverage ratio, thereby improving the characteristics of the semiconductor device and thereby improving the reliability of the semiconductor device. It relates to a technology that enables high integration.
점차적으로, 반도체소자가 고집적화됨에 따라 콘택홀의 에스펙트비(aspect ratio)가 증가하게 되었다.Increasingly, as the semiconductor devices are highly integrated, the aspect ratio of the contact holes increases.
그에 따라 미세패턴을 형성할 수 있는 원자외선용 감광막으로 사용하게 되었다.As a result, it has been used as a photosensitive film for far ultraviolet rays capable of forming a fine pattern.
그러나, 높은 에스펙트비로 인하여 유발되는 낮은 단차피복비 때문에, 콘택공정시 콘택홀 내부가 완전히 매립되지 않음으로써 보이드(void) 와 같은 단점을 유발하였다.However, due to the low step coverage ratio caused by the high aspect ratio, the inside of the contact hole is not completely buried during the contact process, which causes disadvantages such as voids.
최근에는, 상기 단점을 극복하기 위하여, 상측부가 넓은 콘택홀을 형성하여 단차피복비를 향상시켜 사용하였다.In recent years, in order to overcome the above disadvantages, the upper side portion has been formed to improve the step coverage ratio by forming a wide contact hole.
제1도는 종래기술에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a method for forming a contact hole in a semiconductor device according to the prior art.
먼저, 반도체기판(31) 상부에 하부절연층(33)을 형성한다. 이때, 상기 하부절연층(33)은 상기 반도체기판(31) 상부에 소자분리절연막(도시안됨), 불순물 접합층(도시안됨), 워드라인(도시안됨), 비트라인(도시안됨) 또는 캐패시터(도시안됨)를 형성하고, 전체표면상부를 비.피.에스.지. (Boro Phospho Silicate Glass, 이하에서 BPSG 라함) 절연막으로 평탄화시켜 형성한다.First, a lower insulating layer 33 is formed on the semiconductor substrate 31. In this case, the lower insulating layer 33 may include an isolation layer (not shown), an impurity bonding layer (not shown), a word line (not shown), a bit line (not shown), or a capacitor (or the like) on the semiconductor substrate 31. Not shown), and the upper surface of the B.P.G. (Boro Phospho Silicate Glass, hereinafter referred to as BPSG) It is formed by planarization with an insulating film.
그 다음에, 상기 하부절연층(33) 상부에 감광막패턴(35)을 형성한다.Next, a photosensitive film pattern 35 is formed on the lower insulating layer 33.
이때, 상기 감광막패턴(35)은 상기 하부절연층(33) 상부에 감광막을 도포하고 콘택마스크(도시안됨)를 이용한 노광 및 현상공정을 실시하여 형성한다.In this case, the photoresist layer pattern 35 is formed by applying a photoresist layer on the lower insulating layer 33 and performing an exposure and development process using a contact mask (not shown).
그리고, 상기 감광막패턴(35)을 마스크로 하여 상기 하부절연층(33)을 소정두께 등방성식각함으로써 상기 감광막패턴(35)의 하부로 상기하부절연층(33)이 측면식각되어 형성된 제1언더컷 (under cut)(37)과 제2언더컷(39)을 형성한다. 이때, 상기 등방성식각공정은 습식방법으로 실시한다.The first undercut formed by side etching the lower insulating layer 33 under the photosensitive film pattern 35 by isotropically etching the lower insulating layer 33 using the photosensitive film pattern 35 as a mask. under cut 37 and a second undercut 39 are formed. At this time, the isotropic etching process is performed by a wet method.
여기서, 상기 감광막패턴(35)이 리프팅(lifting) 될 수도 있으며, 그 원인은 다음과 같다.Here, the photoresist pattern 35 may be lifted, and the causes thereof are as follows.
반도체소자가 고집적화됨에 따라 콘택홀 사이의 간격이 좁아지고 상기 하부절연층인 BPSG 절연막의 평탄성을 향상시키기 위하여 불소와 인등의 불순물농도를 증가시키게 되었다. 이로 인하여, 상기 BPSG 절연막과 감광막의 접착불량이 발생하고, 상기 접착불량은 콘택식각공정중 습식식각공정시 식각용액이 상기 접착불량된 부분으로 측면확산되는 모세관 현상을 과도하게 유발하여 상기 제1언더컷(37)과 제2언더컷(39)이 연결시킴으로써 상기 감광막패턴(35)이 리프팅된다.As semiconductor devices have been highly integrated, impurity concentrations such as fluorine and phosphorus have been increased to narrow the gap between contact holes and to improve the flatness of the lower insulating layer, the BPSG insulating film. As a result, poor adhesion between the BPSG insulating film and the photoresist film occurs, and the poor adhesion causes the capillary phenomenon in which the etching solution is laterally diffused into the poorly bonded portion during the wet etching process during the contact etching process. The photosensitive film pattern 35 is lifted by the connection between the 37 and the second undercut 39.
그 다음에, 상기 감광막패턴(35)을 마스크로하여 상기 하부절연층(33)을 이방성식각함으로써 콘택홀(41)을 형성한다.Next, the contact hole 41 is formed by anisotropically etching the lower insulating layer 33 using the photoresist pattern 35 as a mask.
상기한 바와 같이 종래기술에 따른 반도체소자의 콘택홀 형성방법은, 습식방법의 등방성식각공정시 감광막패턴이 리프팅되어 후속공정을 진행하기가 어렵게 되고, 건식방법만으로 콘택홀을 형성하면 단차피복비의 문제가 대두되되, 반도체소자가 고집적화됨에따라 상기 리프팅 현상을 더욱 자주 발생되어 반도체소자의 수율 및 생산성이 저하시키며, 반도체소자의 특성 및 신뢰성이 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method of forming a contact hole of a semiconductor device according to the prior art, the photoresist pattern is lifted during the isotropic etching process of the wet method, making it difficult to proceed with the subsequent process. However, as the semiconductor device is highly integrated, the lifting phenomenon occurs more frequently, which lowers the yield and productivity of the semiconductor device, deteriorates the characteristics and reliability of the semiconductor device, and thereby makes it difficult to integrate the semiconductor device.
따라서, 본 발명은 상기한 문제점을 해결하기 위하여, H20 베이퍼(vapor) 그리고 HF 베이퍼나 BOE 베이퍼를 이용하여 등방성식각공정을 실시하여 식각용액으로 인하여 발생되는 과도한 모세관 현상을 방지함으로써 용이하게 콘택홀을 형성할 수 있어 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 수율 및 생산성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 콘택홀 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems, the present invention can be easily contacted by performing an isotropic etching process using H 2 0 vapor and HF vapor or BOE vapor to prevent excessive capillary phenomenon caused by the etching solution. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of forming a hole, thereby improving characteristics and reliability of the semiconductor device, improving yield and productivity of the semiconductor device, and enabling high integration of the semiconductor device.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 콘택홀 형성방법은, 반도체기판 상부에 하부절연층을 형성하고 상기 하부절연층을 형성한 다음, 상기 하부절연층 상부에 감광막패턴을 형성하고 상기 감광막패턴을 마스크로하여 상기 반도체기판을 노출시키는 반도체소자의 콘택홀 형성방법에 있어서, 상기 반도체기판을 일정압력의 반응로에 주입하는 공정과, 상기 반응로에 H20 베이퍼와 HF 베이퍼을 주입하여 상기 H20 베이퍼 및 HF 베이퍼를 상기 하부절연층과 반응시킴으로써 상기 하부절연층을 등방성식각하는 공정과, 상기 감광막패턴을 마스크로 하여 불소계 플라즈마를 이용한 식각공정으로 상기 하부절연층을 식각하여 콘택홀을 형성하는 공정과, 상기 등방성식각공정의 잔유물을 순수로 세척하는 공정을 포함하는 것이다.In order to achieve the above object, a method of forming a contact hole in a semiconductor device according to the present invention may include forming a lower insulating layer on an upper surface of a semiconductor substrate, forming the lower insulating layer, and then forming a photoresist pattern on the lower insulating layer. A method of forming a contact hole in a semiconductor device exposing the semiconductor substrate using a photoresist pattern as a mask, the method comprising: injecting the semiconductor substrate into a reactor at a constant pressure; and injecting H 2 0 vapor and HF vapor into the reactor; Isotropically etching the lower insulating layer by reacting the H 2 0 wafer and the HF wafer with the lower insulating layer; and etching the lower insulating layer by an etching process using a fluorine-based plasma using the photoresist pattern as a mask. Forming a step, and washing the residue of the isotropic etching step with pure water.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2a도 및 제2b도는 본 발명의 실시예에 따른 반도체소자의 콘택홀 형성방법을 도시한 단면도이다.2A and 2B are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 하부절연층(13)을 형성한다.First, a lower insulating layer 13 is formed on the semiconductor substrate 11.
이때, 상기 하부절연층(13)은 상기 반도체기판(11) 상부에 소자분리절연막(도시안됨), 불순물 접합층(도시안됨), 워드라인(도시안됨), 비트라인(도시안됨) 또는 캐패시터(도시안됨)를 형성하고, 전체표면상부에 비.피.에스.지. (Boro Phospho Silicate Glass, 이하에서 BPSG 라함) 절연막을 4000 ~ 8000Å 정도의 두께로 증착하고 이를 평탄화시켜 형성한다.In this case, the lower insulating layer 13 may include a device isolation insulating film (not shown), an impurity junction layer (not shown), a word line (not shown), a bit line (not shown), or a capacitor on the semiconductor substrate 11. Not shown) and the B.S.G. (Boro Phospho Silicate Glass, hereinafter referred to as BPSG) An insulating film is formed by depositing a thickness of about 4000 ~ 8000Å and planarizing it.
그 다음에, 상기 하부절연층(13) 상부에 감광막패턴(15)을 형성한다. 이때, 상기 감광막패턴(15)은 상기 하부절연층(13) 상부에 감광막을 도포하고 콘택마스크(도시안됨)를 이용한 노광 및 현상공정을 실시하여 형성한다. (제2a도)Next, a photosensitive film pattern 15 is formed on the lower insulating layer 13. In this case, the photoresist pattern 15 is formed by applying a photoresist on the lower insulating layer 13 and performing an exposure and development process using a contact mask (not shown). (Figure 2a)
그리고, 상기 감광막패턴(15)을 마스크로 하여 상기 하부절연층(13)을 2000 ~ 3000Å 정도의 두께로 등방성식각하여 제1,2언더컷(17,19)을 형성한다. 이때, 상기 등방성식각공정은 식각공정을 실시하는 반응로 내부압력을 0.1 파스칼(Pa) 이하의 진공으로 유지하고, 상기 반도체기판(11)을 반응로에 로딩(loading) 한다. 그리고, 상기 반응로에 H20 베이퍼를 주입하며 압력을 1 ~ 1000 파스칼(Pa)로 유지한다. 그 다음에, HF 베이퍼를 주입하여 상기 H2O 베이퍼와 HF 베이퍼가 상기 하부절연층(13)을 반응시킴으로써 실시한 것이다.The first and second undercuts 17 and 19 are formed by isotropically etching the lower insulating layer 13 to a thickness of about 2000 to 3000 m 3 using the photoresist pattern 15 as a mask. In this case, the isotropic etching process maintains the internal pressure of the reactor in which the etching process is performed at a vacuum of 0.1 Pascal (Pa) or less, and loads the semiconductor substrate 11 into the reactor. In addition, H 2 0 vapor is injected into the reactor to maintain a pressure of 1 to 1000 Pascals (Pa). Subsequently, HF vapor is injected, and the H 2 O vaporizer and the HF vaporizer react with the lower insulating layer 13.
여기서, 상기 등방성식각공정은 HF : H2O 의 분압비를 30 : 1 에서 1 : 50 까지로 하여 실시한다. 그리고, 상기 하부절연층(13)과의 반응식은 다음과 같다.Here, the isotropic etching process is carried out with a partial pressure ratio of HF: H 2 O from 30: 1 to 1:50. The reaction formula with the lower insulating layer 13 is as follows.
여기서, 상기 HF 베이퍼는 BOE 베이퍼를 대신 사용할 수도 있다.(제2a도)Here, the HF vapor may be used instead of the BOE vapor (Fig. 2a).
그 다음에, 상기 감광막패턴(15)을 마스크로하여 상기 하부절연층(13)을 이방성식각하되, 불소계 플라즈마를 이용하여 실시하여 상기 반도체기판(11)을 노출시키는 콘택홀(21)을 형성한다.Next, the lower insulating layer 13 is anisotropically etched using the photoresist pattern 15 as a mask, and a contact hole 21 is formed to expose the semiconductor substrate 11 by using fluorine-based plasma. .
그리고, 상기 등방성식각공정시 발생한 식각잔유물(도시안됨)을 순수(DI)를 이용하여 제거한다. (제2b도)Then, the etching residue (not shown) generated during the isotropic etching process is removed using pure water (DI). (Figure 2b)
본 발명의 다른 실시예는, 상기 H20 베이퍼와 HF 베이퍼를 동시에 반응로에 주입하여 등방성식각공정을 실시하고 후속공정으로 콘택홀을 형성한다.In another embodiment of the present invention, the H 2 0 wafer and the HF vapor are simultaneously injected into the reactor to perform an isotropic etching process and to form a contact hole in a subsequent process.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 콘택홀 형성방법은, 고집적화된 반도체소자에서 감광막패턴을 마스크로하는 등방성식각공정시 식각용액에 의한 모세관 현상을 방지하여 과도한 측면식각을 억제함으로써 상기 감광막패턴의 리프팅을 방지하여 후속공정을 용이하게 할 수 있어 용이하게 콘택홀을 형성하여 반도체소자의 특성 및 신뢰성을 향상시키고, 반도체소자의 수율 및 생산성을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 잇점이 있다.As described above, the method of forming a contact hole in a semiconductor device according to the present invention prevents capillary phenomenon caused by an etching solution during an isotropic etching process using a photoresist pattern as a mask in a highly integrated semiconductor device, thereby suppressing excessive side etching. It is possible to facilitate the subsequent process by preventing the lifting of the pattern to easily form the contact hole to improve the characteristics and reliability of the semiconductor device, to improve the yield and productivity of the semiconductor device, thereby enabling high integration of the semiconductor device There is an advantage.
Claims (5)
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