KR100195877B1 - Method of manufacturing transistor - Google Patents
Method of manufacturing transistor Download PDFInfo
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- KR100195877B1 KR100195877B1 KR1019960056414A KR19960056414A KR100195877B1 KR 100195877 B1 KR100195877 B1 KR 100195877B1 KR 1019960056414 A KR1019960056414 A KR 1019960056414A KR 19960056414 A KR19960056414 A KR 19960056414A KR 100195877 B1 KR100195877 B1 KR 100195877B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000004065 semiconductor Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims description 14
- 238000009792 diffusion process Methods 0.000 claims 1
- 239000000203 mixture Substances 0.000 abstract description 4
- 238000001465 metallisation Methods 0.000 abstract 1
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 2
- 238000011105 stabilization Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
본 발명은 콤포지션방법을 이용하여 부위별로 단차를 제거하여 금속배선 공정을 안정화하는 바이폴라 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method for fabricating a bipolar transistor that stabilizes a metallization process by removing a step by region using a composition method.
상술한 목적을 달성하기 위하여, 본 발명의 바이폴라 트랜지스터의 제조방법은 반도체 기판상에 베이스 영역이 형성될 부분이 노출되도록 제1 절연막을 형성하는 단계와, 반도체 기판상의 노출된 영역에 소정의 도전형을 갖는 불순물을 이온주입하여 베이스 영역을 형성하는 단계와, 베이스 영역과 일정간격이 떨어진 반도체 기판상의 제1 절연막을 식각하여 콜렉터 영역이 형성될 부분의 상기 반도체 기판을 노출시키는 단계와, 반도체 기판의 상부에 제2 절연막을 형성하는 단계와, 제2 절연막을 식각하여 베이스 영역의 일부와 상기 콜렉터 영역이 형성될 부분의 반도체 기판을 노출시키는 단계와, 반도체 기판의 노출된 영역에 베이스 영역과는 상반된 도전형을 갖는 불순물을 이온주입하는 단계와, 반도체 기판상에 제3 절연막을 형성하는 단계와, 이온주입된 불순물을 확산시켜 베이스 영역내에 에미터 영역을 형성함과 동시에 베이스 영역과 일정간격이 떨어진 반도체 기판에 콜렉터 영역을 형성하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of manufacturing a bipolar transistor including: forming a first insulating layer on a semiconductor substrate to expose a portion where a base region is to be formed; Exposing the semiconductor substrate at a portion where a collector region is to be formed by etching the first insulating film on the semiconductor substrate spaced apart from the base region by a predetermined distance; Etching the second insulating film to expose a portion of the base region and a portion of the semiconductor substrate in which the collector region is to be formed; and forming a second insulating film on the exposed region of the semiconductor substrate, Implanting an impurity having a conductivity type; forming a third insulating film on the semiconductor substrate; Diffusing the implanted impurity on at the same time as forming the emitter region in the base region and forming a collector region in the semiconductor substrate on which the base region and spaced apart.
Description
제1도는 종래의 바이폴라 트랜지스터의 레이아웃도.FIG. 1 is a layout diagram of a conventional bipolar transistor; FIG.
제2도는 제1도의 a-a'선에 따른 바이폴라 트랜지스터의 단면도.FIG. 2 is a cross-sectional view of the bipolar transistor taken along line a-a 'of FIG. 1; FIG.
제3도 (a)-(g)는 제2도의 바이폴라 트랜지스터의 제조공정 단면도.3 (a) - (g) are cross-sectional views of the manufacturing process of the bipolar transistor of FIG. 2;
제4도는 본 발명의 실시예에 따른 바이폴라 트랜지스터의 레이아웃도.FIG. 4 is a layout diagram of a bipolar transistor according to an embodiment of the present invention; FIG.
제5도는 제4도의 b-b'선에 바이폴라 트랜지스터의 단면도.5 is a cross-sectional view of a bipolar transistor taken along the line b-b 'of FIG. 4;
제6도 (a)-(f)는 제5도의 바이폴라 트랜지스터의 제조공정 단면도.6 (a) - (f) are sectional views of the manufacturing process of the bipolar transistor of FIG. 5;
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
31 : 반도체 기판 32 : 산화막31: semiconductor substrate 32: oxide film
33 : 베이스 영역 34 : 도핑되지 않은 산화막33: base region 34: undoped oxide film
35 : 감광막 36 : 마스크35: photosensitive film 36: mask
37 : PSG 막 38 : 에미터 영역37: PSG film 38: Emitter region
39 : 콜렉터 영역 40-42 : 콘택39: collector region 40-42: contact
43-45 : 금속전극43-45: metal electrode
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 콤포지션방법을 이용하여 부위별로 단차를 제거하여 금속배선공정을 안정화하는 바이폴라 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a bipolar transistor that stabilizes a metal wiring process by removing a step by region using a composition method.
일반적으로, 반도체 장치의 제조공정시 단차가 발생했을 때, 발생된 단차를 부분적으로 줄이기 위한 별도의 설계를 하지 않고 전체적으로 막을 제거하거나 또는 그대로 방치하는 방법을 채택하였다.Generally, when a step is generated in the manufacturing process of a semiconductor device, a method of removing the film entirely or leaving it as it is without adopting a separate design for partially reducing the generated step.
제1도는 종래의 바이폴라 트랜지스터의 레이아웃도를 도시한 것이고, 제2도는 제1도의 a-a'선에 따른 단면도를 도시한 것이다. 제1도 및 제2도를 참조하면, 반도체 기판(11)에 서로 다른 도전형을 갖는 베이스 영역(13)과 콜렉터 영역(19)이 일정간격을 두고 형성된다. 베이스 영역(13)에는 콜렉터 영역(19)과 동일 도전형의 에미터 영역(18)이 형성된다. 기판상에는 에미터 영역(18), 베이스 영역(13) 및 콜렉터 영역(19)에는 각각의 콘택(20-22)을 통해 연결되는 금속전극(23-25)이 형성된다. 그리고, 기판(11)상에는 금속전극(23-25)과 기판(11)간 절연을 위한 절연막들(12, 14, 17)이 형성되어 단차가 형성된다. 베이스 영역(13) 및 에미터 영역(18) 상부의 기판상부보다는 콜렉터상부의 기판이 보다 급격한 단차를 갖는다. 도면중 참조번호 26은 콤포지션(composition)영역을 나타낸다.FIG. 1 is a layout view of a conventional bipolar transistor, and FIG. 2 is a cross-sectional view taken along line a-a 'of FIG. 1. Referring to FIGS. 1 and 2, a base region 13 and a collector region 19 having different conductivity types are formed in the semiconductor substrate 11 at regular intervals. In the base region 13, an emitter region 18 having the same conductivity type as that of the collector region 19 is formed. On the substrate, the emitter region 18, the base region 13, and the collector region 19 are formed with metal electrodes 23-25 connected to each other via the respective contacts 20-22. Insulating films 12, 14, and 17 for insulation between the metal electrode 23-25 and the substrate 11 are formed on the substrate 11 to form a step. The base region 13 and the substrate above the collector above the emitter region 18 have a more abrupt step. Reference numeral 26 in the figure denotes a composition area.
상기한 바와같은 구조를 갖는 종래의 바이폴라 트랜지스터의 제조방법을 제3도를 참조하여 설명하면 다음과 같다.A method of manufacturing a conventional bipolar transistor having the above structure will be described with reference to FIG.
제3도(a)를 참조하면, 반도체 기판(11)상에 통상의 방법으로 베이스영역(13)을 형성한다. 즉, 산화막과 같은 절연막(12)을 형성한 다음 식각공정을 통해 절연막(12)을 식각하여 베이스가 형성될 영역의 기판(11)을 노출시키고, 이어서 기판(11)의 노출부분에 소정의 불순물을 이온주입시켜 베이스 영역(13)을 형성한다.Referring to FIG. 3 (a), a base region 13 is formed on a semiconductor substrate 11 in a conventional manner. That is, the insulating film 12 such as an oxide film is formed and then the insulating film 12 is etched through the etching process to expose the substrate 11 in the region where the base is to be formed. Then, The base region 13 is formed.
다음, 기판(11)상에 도핑되지 않은 산화막(UDO) (14)을 형성하고 그위에 감광막(15)을 도포한다. 마스크(16)를 이용한 사진식각공정을 하여 에미터 영역과 콜렉터 영역이 형성될 부분의 산화막(14)이 노출되도록 감광막(15)을 패터닝하면 제3도(b)와 같이 된다.Next, an undoped oxide film (UDO) 14 is formed on the substrate 11, and the photosensitive film 15 is coated thereon. The photolithography film 15 is patterned such that the oxide film 14 of the portion where the emitter region and the collector region are to be formed is exposed through a photolithography process using the mask 16, as shown in FIG. 3 (b).
이어서, 감광막(15)을 마스크로 하여 노출된 산화막(14)을 1차로 식각하여 에미터 영역이 형성될 부분의 기판(11)의 베이스영역(13)을 노출시킴과 동시에 콜렉터 영역이 형성될 부분의 절연막(12)을 제3와(c)와 같이 노출시킨다.Next, the oxide film 14 exposed by using the photoresist film 15 as a mask is first etched to expose the base region 13 of the substrate 11 at the portion where the emitter region is to be formed, The insulating film 12 of FIG.
1차식각공정후 노출된 절연막(12)을 2차로 식각하여 콜렉터 영역이 형성될 부분의 기판을 제2도(d)와 같이 노출시킨 다음 남아있는 감광막(15)을 제거하면 제3도(e)와 같이 된다. 에미터 영역의 콜렉터 영역을 형성하기 위하여 노출된 기판으로 베이스영역과는 반대의 도전형을 갖는 불순물을 이온주입한다.After the first etching process, the exposed insulating film 12 is secondarily etched to expose the substrate where the collector region is to be formed, as shown in FIG. 2 (d), and then the remaining photoresist film 15 is removed. ). An impurity having a conductivity type opposite to that of the base region is implanted into the exposed substrate to form a collector region of the emitter region.
이어서 제3도(f)와 같이, 기판(11)상에 화학기상증착법으로 PSG막(Phospho Silicate Glass)(17)를 증착한 다음, 이온주입된 불순물을 확산시키면 제3도(g)와 같이 베이스 영역(13)내에 에미터영역(18)이 형성되고, 베이스 영역과 소정의 거리를 두고 기판(11)내에 콜렉터 영역(19)이 형성된다.Next, as shown in FIG. 3F, a PSG film (Phospho Silicate Glass) 17 is deposited on the substrate 11 by a chemical vapor deposition method. Then, when the ion implanted impurity is diffused, An emitter region 18 is formed in the base region 13 and a collector region 19 is formed in the substrate 11 at a predetermined distance from the base region.
다음으로 에미터, 베이스 및 콜렉터 영역의 콘택을 위하여 PSG막(17)을 식각하여 콘택(20-22)을 형성한 다음 메탈공정을 진행하여 에미터전극(23), 베이스 전극(24) 및 콜렉터 전극(25)을 형성하면, 제2도와 같은 종래의 바이폴라 트랜지스터가 제조된다.Next, the PSG film 17 is etched to form the contacts 20-22 for the contact of the emitter, base and collector regions, and then the metal process is performed to form the emitter electrode 23, the base electrode 24, When the electrode 25 is formed, a conventional bipolar transistor such as the second diagram is manufactured.
이와 같은 종래의 방법으로 바이폴라 트랜지스터를 제조하면, 부분적으로 단차가 높은 부위가 발생시 부분적으로 단차를 제거한 다음 공정을 진행하기 때문에 그리고 에미터 영역과 콜렉터 영역을 노출시키기 위하여 산화막과 절연막을 식각하므로 식각시간이 길어지는 문제점이 있었다. 또한, 설계패턴의 부위별 각종막의 두께를 고려하지 않음으로써 막단차로 인한 메탈 안정화 대책이 힘들고, 나아가서 에칭시 오버에칭 및 미스에칭으로 인한 불량이 발생하는 문제점이 있었다.When the bipolar transistor is manufactured by the conventional method as described above, when a portion having a high step is partially formed, the oxide film and the insulating film are etched to expose the emitter region and the collector region, There was a problem that this was lengthened. In addition, there is a problem in that it is difficult to take measures against metal stabilization due to the step of the film because the thickness of various films for each part of the design pattern is not taken into consideration, and furthermore, defects due to overetching and misetching occur during etching.
따라서, 본 발명의 목적은 반도체 웨이퍼가 가공시 부위별 단차를 제거하여 주므로써 이후의 식각공정시 식각시간을 단축시켜 공정스루풋(throughput)을 향상시킬 수 있는 바이폴라 트랜지스터의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a bipolar transistor capable of improving process throughput by shortening an etch time in a subsequent etching process by removing a step of a semiconductor wafer during processing.
본 발명의 다른 목적은 부분적인 막단차를 제거하여 주므로써, 이후의 메탈공정을 안정화시킬 수 있는 바이폴라 트랜지스터의 제조방법을 제공하는 데 그 목적이 있다.It is another object of the present invention to provide a method of manufacturing a bipolar transistor capable of stabilizing a subsequent metal process by removing a partial film step.
상술한 목적을 달성하기 위하여, 본 발명의 바이폴라 트랜지스터의 제조방법은 반도체 기판상에 베이스 영역이 형성될 부분이 노출되도록 제1 절연막을 형성하는 단계와, 반도체 기판상의 노출된 영역에 소정의 도전형을 갖는 불순물을 이온주입하여 베이스 영역을 형성하는 단계와, 베이스 영역과 일정간격이 떨어진 반도체 기판상의 제1 절연막을 식각하여 콜렉터 영역이 형성될 부분의 상기 반도체 기판을 노출시키는 단계와, 반도체 기판의 상부에 제2 절연막을 형성하는 단계와, 제2 절연막을 식각하여 베이스 영역의 일부와 콜렉터 영역이 형성될 부분의 반도체 기판을 노출시키는 단계와, 반도체 기판의 노출된 영역에 베이스 영역과는 상반된 도전형을 갖는 불순물을 이온주입하는 단계와, 반도체 기판상에 제3 절연막을 형성하는 단계와, 이온주입된 불순물을 확산시켜 베이스 영역내에 에미터 영역을 형성함과 동시에 베이스 영역과 일정간격이 떨어진 반도체 기판에 콜렉터 영역을 형성하는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of manufacturing a bipolar transistor including: forming a first insulating layer on a semiconductor substrate to expose a portion where a base region is to be formed; Exposing the semiconductor substrate at a portion where a collector region is to be formed by etching the first insulating film on the semiconductor substrate spaced apart from the base region by a predetermined distance; Etching the second insulating film to expose a portion of the base region and a portion of the semiconductor substrate in which the collector region is to be formed; forming a second insulating film on the exposed region of the semiconductor substrate, Forming a third insulating film on the semiconductor substrate, forming a second insulating film on the semiconductor substrate, And forming an emitter region in the base region by diffusing the impurities and forming a collector region in the semiconductor substrate separated from the base region by a predetermined distance.
상기 목적 외에 본 발명의 다른 목적 및 잇점들은 후술될 본 발명의 실시예에 대한 상세한 설명을 통하여 명확하게 드러나게 될 것이다.Other objects and advantages of the present invention will become apparent from the following detailed description of the embodiments of the present invention.
이하 제4도 내지 제6도를 참조하여 본 발명의 바람직한 실시예에 대하여 상세히 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 4 to 6.
제4도는 본 발명의 실시예에 따른 바이폴라 트랜지스터의 레이아웃도를 나타낸 것이고, 제5도는 제4도의 b-b'선에 따른 바이폴라 트랜지스터의 단면도를 도시한 것이다.FIG. 4 is a layout view of a bipolar transistor according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view of a bipolar transistor taken along line b-b 'of FIG.
제4도 및 제5도를 참조하면, 본 발명의 실시예에 따른 바이폴라 트랜지스터는 반도체 기판(31)에 서로 다른 도전형을 갖는 베이스 영역(33)과 콜렉터 영역(39)이 일정간격을 두고 형성된다. 베이스 영역(33)에는 콜렉터 영역(39)과 동일 도전형의 에미터 영역(38)이 형성된다. 기판상의 에미터 영역(38), 베이스 영역(33) 및 콜렉터 영역(39)에는 각각의 콘택(40-42)을 통해 연결되는 금속전극(43-45)이 형성된다. 그리고, 기판(31)상에는 금속전극(43-45)과 기판(31)간의 절연을 위한 절연막들(32, 34, 37)이 형성되어 단차가 형성된다. 베이스 영역(33) 및 에미터 영역(38)상부의 기판과 마찬가지로 콜렉터 상부의 기판은 완만한 단차를 갖는다. 도면중 참조번호 46은 콤포지션(composition) 영역을 나타낸다.4 and 5, a bipolar transistor according to an embodiment of the present invention includes a base region 33 and a collector region 39 having different conductivity types formed on a semiconductor substrate 31 at regular intervals do. In the base region 33, an emitter region 38 having the same conductivity type as that of the collector region 39 is formed. The emitter region 38, the base region 33 and the collector region 39 on the substrate are formed with the metal electrodes 43-45 connected through the respective contacts 40-42. Insulating films 32, 34 and 37 for insulation between the metal electrodes 43 to 45 and the substrate 31 are formed on the substrate 31 to form a step. Like the substrate above the base region 33 and the emitter region 38, the substrate above the collector has a gentle step. Reference numeral 46 in the figure denotes a composition area.
상기한 바와같은 구성을 갖는 바이폴라 트랜지스터의 제조공정을 제6도 (a)-(f)를 참조하여 설명하면 다음과 같다.The manufacturing process of the bipolar transistor having the above-described structure will be described with reference to FIGS. 6 (a) to 6 (f).
제6도(a)를 참조하면, 반도체 기판(31)상에 산화막과 같은 절연막(32)을 형성한 다음 식각공정을 통해 콜렉터 영역이 형성될 부분의 기판상에 형성된 절연막(32)을 식각하여 베이스 영역이 형성될 부분의 기판뿐만 아니라 콜렉터 영역의 기판을 노출시킨다. 이어서 절연막(32)을 형성한 다음 식각하여 베이스가 형성될 영역의 기판(31)만 노출시키고, 이어서 노출된 기판(31)으로 소정의 불순물을 이온주입시켜 베이스 영역(33)을 형성한다.6 (a), an insulating film 32 such as an oxide film is formed on a semiconductor substrate 31, and then an insulating film 32 formed on a substrate where a collector region is to be formed is etched through an etching process Thereby exposing the substrate of the collector region as well as the substrate of the portion where the base region is to be formed. Subsequently, an insulating film 32 is formed and then etched to expose only the substrate 31 in the region where the base is to be formed. Then, a predetermined impurity is ion-implanted into the exposed substrate 31 to form the base region 33.
이와같이 본 발명의 실시예에서는 콜렉터 영역이 형성될 부분의 기판상에 형성된 절연막(32)에 의해 형성되는 단차를 부분적으로 먼저 제거하여 준다음 그다음의 후속공정을 진행하게 된다.As described above, in the embodiment of the present invention, the step formed by the insulating film 32 formed on the substrate where the collector region is to be formed is partially removed first, followed by the subsequent process.
다음, 기판상에 도핑되지 않은 산화막(UDO) (34)을 형성하고 그위에 감광막(35)을 도포한다. 마스크(36)를 이용한 사진식각공정을 하여 에미터 영역과 콜렉터 영역이 형성될 부분의 산화막(34)이 노출되도록 감광막(35)을 패터닝하면 제6도(b)와 같이 된다.Next, an undoped oxide film (UDO) 34 is formed on the substrate, and the photosensitive film 35 is coated thereon. 6 (b) when the photoresist film 35 is patterned so that the oxide film 34 at the portion where the emitter region and the collector region are to be formed is exposed through the photolithography process using the mask 36. [
이어서, 감광막(35)을 마스크로 하여 노출된 산화막(34)을 식각하여 에미터 영역이 형성될 부분의 기판(31) 즉, 베이스영역(33)의 소정부분을 노출시킴과 동시에 콜렉터 영역(39)이 형성될 부분의 기판(31)을 제6도(c)와 같이 노출시킨다.The exposed oxide film 34 is then etched using the photoresist film 35 as a mask to expose a predetermined portion of the substrate 31 or the base region 33 where the emitter region is to be formed and the collector region 39 Is exposed as shown in FIG. 6 (c).
본 발명의 실시예에서는 제6도(a)의 베이스 영역(33)을 형성하는 공정에서 콜렉터 영역(39)이 형성될 부분의 기판상에 형성된 절연막(32)을 미리 식각하여 주므로써, 제6도(c)의 식각공정에서 종래와는 달리 산화막(UDO)을 식각하기 위한 식각공정만이 진행된다.In the embodiment of the present invention, in the step of forming the base region 33 in FIG. 6 (a), the insulating film 32 formed on the substrate at the portion where the collector region 39 is to be formed is etched in advance, Unlike the conventional etching process, only the etching process for etching the oxide film (UDO) proceeds.
산화막(34)의 식각공정후 제6도(d)와 같이 노출시킨 다음 남아있는 감광막(35)을 제거한 다음, 에미터 영역(38)과 콜렉터 영역(39)을 형성하기 위하여 노출된 기판으로 베이스영역(33)과는 반대의 도전형을 갖는 불순물을 이온주입한다.After the oxide film 34 is etched as shown in FIG. 6 (d), the remaining photoresist film 35 is removed, and then the exposed substrate is exposed to form the emitter region 38 and the collector region 39. An impurity having a conductivity type opposite to that of the region 33 is ion-implanted.
이어서, 제6도(e)와 같이, 기판(31)상에 화학기상증착법으로 PSG막(37)를 증착한 다음, 이온주입된 불순물을 확산시키면 제3도(f)와같이 베이스 영역(33)내에 에미터영역(38)이 형성되고, 베이스 영역과 소정의 거리를 두고 기판(31)내에 콜렉터 영역(39)이 형성된다.6 (e), the PSG film 37 is deposited on the substrate 31 by chemical vapor deposition, and then the ion-implanted impurity is diffused. Then, as shown in FIG. 3 (f) And a collector region 39 is formed in the substrate 31 at a predetermined distance from the base region.
마지막으로, 에미터, 베이스 및 콜렉터 영역(38, 33, 39)의 콘택을 위하여 PSG막(37)을 식각하여 콘택(40-42)을 형성한 다음 메탈공정을 진행하여 에미터전극(43), 베이스 전극(44) 및 콜렉터 전극(45)을 형성하면, 제5도와 같은 본 발명의 실시예에 따른 바이폴라 트랜지스터가 제조된다.Finally, the contact 40-42 is formed by etching the PSG film 37 for the contact of the emitter, base and collector regions 38, 33 and 39, and then the metal process is performed to form the emitter electrode 43, The base electrode 44 and the collector electrode 45, a bipolar transistor according to the embodiment of the present invention as shown in FIG. 5 is manufactured.
상기한 바와같은 본 발명에 따르면, 콜렉터 영역에서 형성되는 단차를 식각공정전에 미리 부분적으로 제거하여 주므로써, 이후의 식각공정시 식각시간을 반으로 단축시켜 공정스루풋을 향상시킬 수 있을 뿐만 아니라 이후의 금속공정을 안정화시켰다. 이에 따라 막단차가 큰 부분에서의 금속안정화에 따른 메탈스텝커버리지 등과 같은 불량발생을 사전에 방지할 수 있으며, 칩손실을 방지할 수 있는 이점이 있다.According to the present invention as described above, since the step formed in the collector region is partially removed before the etching process, it is possible to shorten the etching time in the subsequent etching process to improve the process throughput, The metal process was stabilized. As a result, defects such as metal step coverage due to metal stabilization at a portion having a large film step can be prevented in advance, and chip loss can be prevented.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의하여 정하여져야만 한다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.
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