KR100192572B1 - A reducing method of program stress in the semiconductor memory device - Google Patents

Abstract

1. the technical field to which the invention described in the claims belongs;

A method of reducing program stress in an electrically erasable and programmable nonvolatile semiconductor memory device having cells having a NAND structure.

2. The technical problem to be solved by the invention;

The present invention provides a method for reducing program stress caused by bulk bias.

3. Summary of the Solution of the Invention;

A method for reducing stress of a cell string according to a program voltage of a nonvolatile semiconductor memory, the method comprising: applying a negative bias of the cell string before applying the program voltage to the cell, and then applying the program voltage to the cell string. The summary is to apply to the selected cell.

4. Significant use of the invention;

A method for reducing program stress in a semiconductor memory device.

Description

Program stress reduction method of semiconductor memory device

1 is a circuit diagram of a cell string of a NAND structure EEPROM shown for explaining a conventional program method.

2 is an equivalent cross-sectional view of a floating gate memory cell for explaining the program stress reduction of the present invention.

3 is a circuit diagram of a cell string according to an embodiment of the present invention.

4 is a waveform diagram of a simulation according to FIG.

The present invention relates to an electrically erasable and programmable nonvolatile semiconductor memory device, and more particularly, to a method for reducing program stress of an electrically erasable and programmable nonvolatile semiconductor memory device having pins having a NAND structure.

In general, all memory transistors in a NAND unit have a floating gate formed on the channel region between the source and drain regions via a gate oxide film, and a control gate formed on the floating gate through an intermediate insulating film.

1 is a circuit diagram of a cell string of a NAND structure EEPROM shown for explaining a conventional program method. The concept of program stress will first be described with reference to FIG. 1, and will be described with specific examples. Figure 1 illustrates program stress. In the case of the transistor M2, Vcc is applied to the bit line BL2, and a width of 30us is applied to the selected word line W / L5 and a stepping type pulse is increased by 0.5V from 14.5V to 19V. When the pass voltage Vpass of about 7 to 8 V is applied to W / L0 to W / L4 and W / L6 to W / L7, the transistor M4 applied to the string select line SSL is turned off, and the source, Voltages Vs and Vd applied to the drain are induced about 6 to 7 V over the entire string. The voltage difference between Vs and Vd of 6 to 7V and the floating gate prevents electrons from tunneling and is not sufficiently programmed. In practice, however, some tunneling current flows and the threshold voltage is converted accordingly. As described above, when the threshold voltage Vth of the cell programmed as data 1 is converted to the programmed direction (0 state), the program is subjected to program stress. On the other hand, if the pass voltage Vpass is increased, Vs and Vd become higher due to self boosting, thereby reducing program stress. However, in case of transistor M3, if the pass voltage Vpass voltage is repeatedly applied too high, The threshold voltage of M3 is converted to the programming direction. This is called a pass voltage stress.

If the pass voltage is high, Vs and Vd are increased by the self boosting, so that the program stress is less. However, since the voltage is applied to the non-selected word line, the pass voltage stress is relatively high.

Therefore, a solution with adequate margins that reduces both program stress and pass voltage stress must be found.

The above program stress and pass voltage stress are also well described in the prior art, and thus detailed descriptions thereof will be omitted.

On the other hand, in order to program the selected memory transistor in the NAND module, the program operation is performed after temporarily erasing all the memory transistors in the selected block. The erase operation of the memory cells is performed by applying 0V to all control gates and applying a high voltage (about 20V) to the P-type well region and the N-type substrate. Thus, electrons are uniformly emitted from the floating gate of all the memory transistors. As a result, the threshold hold voltage of each memory transistor becomes a negative voltage (about -3V), and the binary logic 1 is stored. The operation of programming the memory transistors with data 0 applies 0V to the bit line, Vcc to the gate of the transistor of the string select line SSL, high voltage (about 20V) to the gate of the selected memory transistor, and the transistor of the ground select line GSL of FIG. Is applied to the gate of the unselected memory transistor 0V and the voltage of 7V which is the intermediate voltage. When programming to data 1 (keeping the erased state of the memory cell), a program protection voltage Vcc is applied to the corresponding bit line, and the program operation of the selected memory transistor is prevented. This programming operation does not uniformly inject electrons from the P-type well into the floating gate through the gate oxide film, so that partial stress of the thin gate oxide film does not occur.

As described above, in the related art, a high level voltage is applied to a gate during programming and 0 V is applied to a bulk.

In this case, when the data is programmed to 1, the cells in which the back pattern is erased (when all cells including the selected cells in the string are erased) are coupled so that the source and drain voltages Vss and Vdd of the selected cell transistor are lower than the program protection voltage. It was ringing and I got a lot of program stress.

The program prevention technique for such a program operation is described in detail in the preceding document 93-00390, so the detailed operation description thereof is omitted in the present invention. To solve this problem, a negative bias is applied to the bulk to lower the junction capacitance of the source and drain nodes of the cell transistor, thereby reducing the total capacitance of the source and drain.

Therefore, an object of the present invention for solving the above problems is to increase the Vss, Vdd voltage by increasing the coupling voltage of the source and drain nodes by the control gate when the capacitance value of the source and drain is small This program provides a way to reduce stress.

Another object of the present invention is to provide a method for reducing program stress caused by bulk bias.

According to the technical idea of the present invention for achieving the above object, in the method for reducing the program stress of the cell string according to the program voltage of the nonvolatile semiconductor memory: Before the program voltage is applied to the cell The program stress is reduced by applying a negative bias to the cell string and then applying the program voltage to selected cells of the cell string.

Hereinafter, with reference to the accompanying drawings a detailed description of the present invention will be described in detail.

2 is an equivalent cross-sectional view of a floating gate memory cell for explaining the program stress reduction of the present invention. Referring to FIG. 2, a cell structure of an electrically erasable and programmable memory semiconductor is shown in FIG. As for the program of the cell, when the high voltage is applied to the control gate 204 and 0 V is applied to the source and the drain, electrons of the pocket P well: B 201 are moved to the floating gate 205 by FN tunneling. Is in the programmed state, and the control gate 204 is set to 0V, the source 203, and the drain 202 are floating, and about + 20V is applied to the pocket P well. Of electrons exit, which is the erased state.

Overall, the largest capacitance value is C1, and the largest capacitance value is C1, C4 = C8, C3 = C7, C5 = C6. Applying a high voltage to the control gate 204 and applying a negative bias to the bulk instead of 0V during programming according to the present invention will widen the junction depletion layer of the source and drain and thus the junction capacitances C4 and C8. ) Becomes small and the voltages of the source: S 203 and the drain: D 202 are increased by charge sharing of C3 and C4.

3 is a circuit diagram of a cell string according to an embodiment of the present invention.

Referring to FIG. 3, it can be seen that applying a negative bias to the bulk increases each source drain voltage more than applying 0V to the bulk.

4 is a waveform diagram of a simulation according to FIG.

Referring to Figure 4, the simulation conditions are Vcc = 2.8V, temperature = 100 ℃. And, this simulation was based on the worst case state, i.e., back pattern (M3-M4, M6-M7) = erased state (threshold voltage = -3V), M2 = programmed state (threshold voltage). = 1.5V), the selected cell = M5 (stringing), and the program voltage was applied 9 pulses by increasing the step voltage by 0.5V from 14.5V to 18.5V. The worst reason when the cell connected to W / L0 is programmed is that the charge from the bitline is not properly fed into the string.

The first selected transistor M5 is an erased transistor (Vth = -3V), and the threshold voltage increases after programming to data 1. The simulation results show that when programmed as Data 1, the stronger the negative voltage applied to the bulk, the larger the Vth conversion. The simulation was set to -5V when the bulk was 0V. If the pass voltage is 6V, the program voltage stress is reduced by about -0.1V (Vth).

Claims (3)

A method for reducing program stress of a cell string according to a program voltage of a nonvolatile semiconductor memory, the method comprising: applying a negative bias to the cell string before the program voltage is applied to the cell, and then applying the program voltage to the cell string. Applying to selected cells of the to reduce program stress. The method of claim 1, wherein the semiconductor memory is a flash memory having a NAND cell structure. 2. The method of claim 1 wherein the cell string has a folded bitline structure.