JP3827531B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device such as a flash memory having a triple well structure and capable of erasing data.
[0002]
[Prior art]
Conventionally, ETOX (registered trademark of Intel Corporation) is the most commonly used flash memory. FIG. 7 shows a schematic cross-sectional view of a memory cell of this ETOX type flash memory.
[0003]
FIG. 7 is a cross-sectional view showing a first conventional example of a flash memory cell having a floating gate structure. As shown in FIG. 7, this flash memory cell has a floating gate structure, and includes a P-type semiconductor substrate P-Sub, a drain D and a source S formed in the P-type semiconductor substrate P-Sub, a drain D and a source. A floating gate FG provided on the P-type semiconductor substrate P-Sub between S via a tunnel oxide film R1, and a control gate CG provided on the floating gate FG via an interlayer insulating film R2. Have
[0004]
The data writing operation in the flash memory will be described. During writing (programming), a positive voltage (for example, DC8V) is applied to the control gate CG, a positive voltage (for example, DC5V) is applied to the drain D, and the source A reference voltage (for example, 0 V) is applied to the S and P type semiconductor substrates P-Sub.
[0005]
As a result, a large amount of current flows from the drain to the source in the channel layer, channel hot electrons are generated in the portion where the electric field near the drain region is high, and electrons are injected into the floating gate FG. As a result, the threshold voltage of the memory cell is raised, and the memory cell is brought into a write state. Generally, a flash EEPROM (Electrically Erasable and Programmable Read Only Memory) has a function capable of being electrically written (programmed) and erased (erasured).
[0006]
Next, a data erasing operation in the flash memory will be described. During erasing (erasing), a negative voltage (for example, DC-9V) is applied to the control gate CG, and a positive voltage (for example, DC 5V) is applied to the source S. Then, a reference voltage (for example, 0 V) is applied to the P-type semiconductor substrate P-Sub, and the drain D is opened.
[0007]
As a result, a tunnel current is generated, electrons are extracted from the floating gate FG to the source region, the threshold voltage of the memory cell is lowered, and the memory cell is brought into an erased state.
[0008]
However, in this erase operation, a BTBT (Band To Band Tunneling) current flows due to a potential difference between the source S and the P-type semiconductor substrate P-Sub, and hot holes and hot electrons are generated at the same time. Among these, hot electrons flow in the direction of the drain D or the P-type semiconductor substrate P-Sub, but the hot holes are drawn toward the tunnel oxide film R1 and trapped in the tunnel oxide film R1. This hot hole trap is said to deteriorate the reliability of the tunnel oxide film R1 and the like.
[0009]
In order to solve the problem of deterioration of the tunnel oxide film R1, for example, Japanese Patent Laid-Open No. 4-229655 proposes a data erasing method using a nonvolatile semiconductor memory device, which is shown in FIG.
[0010]
FIG. 8 is a cross-sectional view showing a second conventional example of a flash memory cell. In FIG. 8, this flash memory cell includes a P-type semiconductor substrate P-Sub, a deep N well DW disposed in the P-type semiconductor substrate P-Sub and having a conductivity type opposite to that of the P-type semiconductor substrate P-Sub, and a deep P well PW surrounded by N well DW and separated from P type semiconductor substrate P-Sub, drain D and source S formed in P well PW, and P type semiconductor substrate between drain D and source S A floating gate FG provided on the P-Sub via the tunnel oxide film R1 and a control gate CG provided on the floating gate FG via the interlayer insulating film R2.
[0011]
The difference between the second conventional example and the first conventional example is in the well structure. Between the P-type semiconductor substrate P-Sub and the P-well PW having the channel layer, the opposite conductivity type (N-type) is used. This is a well structure having a deep N well DW, which is called a triple well structure.
[0012]
In this data erasing method in the flash memory, the source S and the drain D are opened (opened), and a reference voltage (for example, 0 V) is applied to the control gate CG and the P-type semiconductor substrate P-Sub. By applying a positive voltage to the deep N-well DW, electrons are not drawn from the floating gate FG to the source region as in the first conventional example, but instead of being pulled to the P-well PW by the FN (Fowler-Nordheim) tunnel phenomenon. By extracting electrons to the formed channel layer, the threshold voltage of the memory cell is lowered. This is called channel erasure (channel erase).
[0013]
The channel layer is formed under the tunnel oxide film R1 between the source S and the drain D in the P well PW. In this case, since the potentials of the source S and the P well PW are equal, the electric field is not concentrated at the boundary portion between the source S and the P well PW, and therefore no BTBT current is generated, so that hot holes to the tunnel oxide film R1 are generated. No trapping occurs, and the tunnel oxide film R1 does not deteriorate.
[0014]
Next, a third conventional example using a memory cell structure (triple well structure) similar to that in FIG. 8 and having an erase method different from the second conventional example will be described. In this data erasing method, the source S and the drain D are opened (opened), the P-type semiconductor substrate P-Sub is set to the ground potential (GND potential), and a positive voltage is applied to the P well PW and the deep N well DW. In addition, by applying a negative voltage to the control gate CG, electrons are extracted from the floating gate FG to the P well PW.
[0015]
Even in this erasing method, since the potentials of the source S and the P well PW are equal, the electric field is not concentrated at the boundary portion between the source S and the P well PW, and therefore no BTBT current is generated. Hot hole traps do not occur and the tunnel oxide film R1 does not deteriorate.
[0016]
In the flash memory having the triple well structure as in the second and third conventional examples, a positive voltage is applied to the P well PW in order to draw electrons from the floating gate FG to the channel layer formed in the P well PW. ing.
[0017]
On the other hand, in order to electrically isolate the P well PW and the P-type semiconductor substrate P-Sub, a deep N well DW is formed between them to surround the P well PW. The potential relationship between the P well PW and the deep N well DW is always the potential V of the deep N well DW as shown in the following relational expression so as not to be forward biased._DWIs the potential V of the P well PW_PWIt is necessary to make it above.
[0018]
V_PW≦ V_DW
On the other hand, the distribution of threshold voltages of the memory cells in the flash memory is shown in FIG. 9, where the horizontal axis indicates the threshold voltage Vth of the memory cells and the vertical axis indicates the number of memory cells. In FIG. 9, a memory cell having a threshold voltage of 0.8V to 3.0V is in an erased state, and a memory cell having a threshold voltage of 4.5V or higher is in a written state (programmed state).
[0019]
Potential relationship between P well PW and deep N well DW (V_PW≦ V_DW) Has been proposed in Japanese Patent Application Laid-Open No. 11-149789. Here, the gate voltage V is applied to the control gate CG when the erase voltage is applied._CGAs well as applying a negative voltage, the source S and drain D are open. Well voltage V to P well PW and N well DW_PW, V_DWThe application timing will be described with reference to FIG.
[0020]
As shown in FIG. 10, the erase operation is generally performed by repeatedly applying an erase pulse and verifying. First, during the erase pulse application operation, the gate voltage V is applied to the control gate CG._CGAs a negative voltage (for example, -9V) is applied, the source S and the drain D are opened, and the well voltage V is applied to the P well PW and the N well DW._PW, V_DWA positive voltage (for example, 6V) is applied.
[0021]
Next, verification is performed. In the verification, it is verified whether or not the threshold voltage of the memory cell is lowered to a threshold voltage Vth in a predetermined erase state (for example, 0.8 V to 3.0 V in FIG. 9) by application of the erase pulse. Is. During the verify operation, the gate voltage V is applied to the control gate CG._CGFor example, 6.0 V is applied, and the well voltage V is applied to the source S, P well PW and N well DW._PW, V_DWA reference voltage of 0 V is applied, for example, 1 V is applied to the drain D, and the current flowing from the drain D through the memory cell to the source S is detected to determine the erased state.
[0022]
When the threshold voltage of the memory cell becomes equal to or lower than a predetermined voltage Vth (for example, 3.0 V), it is determined that the memory cell is in the erased state, and the subsequent erase pulse application is stopped. If the memory cell has not yet reached the erased state (for example, 3.0 V or less in FIG. 9), an erase pulse is further applied until the memory cell enters the erased state. In this way, by repeating the erase pulse application operation and the verify operation, a predetermined erase state (for example, 0.8 V to 3.0 V in FIG. 9) is brought.
[0023]
In the repetition of the erase pulse application operation and the verify operation, the potential V of the P well PW_PWAnd the potential V of the deep N well DW_DWIs always V_PW≦ V_DWNeed to be satisfied. Therefore, in the well bias switching circuit that supplies voltages to the P well PW and the N well DW, at the start of the erase pulse application,_PW≦ V_DWAs shown in FIG. 10, first, a positive voltage V is applied to the deep N-well DW, as shown in FIG._DWThen, after a lapse of a certain time (DtimeR), a positive voltage V is applied to the P well PW._PWIs operated to apply.
[0024]
Further, when the P-well PW and the deep N-well DW are discharged (because the reference voltage is shifted to 0 V, for example) when the Belphi operation is started after the application of the erase pulse (Etime) is completed, FIG. As shown in FIG. 4, the potential V of the P well PW_PWFirst, and after a certain time (DtimeF), the potential V of the deep N-well DW_DWDischarge. This ensures that V always_PW≦ V_DWIt is possible to maintain this relationship.
[0025]
Here, an outline of an algorithm for an erase operation of a general flash memory including the above-described erase pulse application and verification will be described with reference to FIG. As shown in FIG. 11, the flash memory erasing algorithm is roughly composed of three tasks 1 to 3. In the erase operation, the entire block or the entire block is erased collectively.
[0026]
First, task 1 consists of preconditions and verification. The precondition is that the erase time for each bit differs depending on the data stored when the erase pulse is applied, and the erase is performed in order to meet the conditions of each memory cell in order to prevent the occurrence of overerased cells. All the memory cells in the memory cell array are temporarily set to the programmed state.
[0027]
That is, the state of a memory cell to be erased by data stored in each memory cell is a cell in a write state (threshold voltage Vth is 4.5 V or more) or an erase state (threshold voltage is 0.8 V). ~ 3.0V) cells are mixed, and if an erase pulse is applied as it is, there is a possibility that an overerased cell in which the threshold voltage of a memory cell having a low threshold voltage is lowered to a negative value will appear. is there. In order to prevent this, first, writing (programming) is performed in order to align the threshold voltage conditions of the memory cells to be erased. This writing is performed by applying the above-mentioned various voltages as a write pulse, but repeatedly performing the write pulse application and verify while verifying the threshold voltage, and all the memory cells to be erased. Is set to a predetermined threshold voltage (for example, 4.5 V or more).
[0028]
Next, task 2 is to bring the threshold voltage of the memory cell to, for example, 3.0 V or lower while alternately performing erase voltage application and verification for applying an erase pulse to the memory cell array.
[0029]
Finally, task 3 consists of post-conditioning and verification in which a programming voltage level program pulse is applied to repair an over-erased memory cell.
[0030]
This is because when the erase pulse is applied in task 2, the threshold voltage is rapidly lowered due to variations in the erase characteristics of the memory cell, and a memory cell having a negative threshold voltage (excess erase) may occur. There is a relief, and the memory cell is soft-programmed (lightly written) so that the threshold voltage becomes 0.8 V or higher. This is also verified, and the processing of task 3 is performed while verifying the threshold voltage value.
[0031]
In this way, the block to be erased or the memory cells in all the blocks are stored within the predetermined threshold voltage (0.8 V to 3.0 V), and the erase algorithm is terminated.
[0032]
[Problems to be solved by the invention]
In the erase operation of task 2 in the erase algorithm of the flash memory, an erase pulse is repeatedly applied to the memory cell until the threshold value of the memory cell after erasure falls within a predetermined threshold voltage. That is, the operations from “application of erase pulse voltage” to “verify” and further from “application of erase pulse voltage” to “verify” are repeated several times.
[0033]
Therefore, in the channel erase method shown in the second conventional example and the third conventional example, when the control method (erase algorithm) of Japanese Patent Laid-Open No. 11-149781 is used, the above V_PW≦ V_DWAs shown in FIG. 10, the voltage V is applied to the P well PW and the deep DW before and after the erase pulse is applied._PW, V_DWDelay time (DtimeR + DtimeF) is applied every time. For example, while the erase pulse application time Etime is 4 msec, the delay time (DtimeR + DtimeF) is about 20 μsec to 40 μsec.
[0034]
That is, there is an extra overhead when applying an erase pulse that occupies the majority of a series of erase sequences (tasks 1 to 3) of the flash memory, which has the problem that the time for the entire erase operation increases. .
[0035]
Further, since it is necessary to set the two delay times (DtimeR + DtimeF) as short as possible and reliably, the voltage V is applied to the P well PW and the deep N well DW, respectively._PW, V_DWThe structure of the well bias switching circuit for supplying the current becomes complicated, and the circuit scale is large.
[0036]
The present invention solves the above-mentioned conventional problems, and the voltage relationship (V) between the P well PW and the deep N well DW with a simple circuit configuration._PW≦ V_DWThe semiconductor memory device can reduce the erase time by eliminating the overhead of charging and discharging time to the deep N well surrounding the memory cell when the erase pulse is applied. And
[0037]
[Means for Solving the Problems]
  A semiconductor memory device according to the present invention includes a second conductivity type first well region disposed in a first conductivity type semiconductor substrate, a first conductivity type second well region disposed in the first well region, and In the semiconductor memory device having the memory cell having the source region and the drain region of the second conductor formed in the second well region, before the write operation is performed after the erase command is performed on the memory cell, A voltage equal to or higher than the voltage applied to the second well region during the erase operation is supplied to the first well region, and the voltage supplied to the first well region isBy repeating erase voltage application and erase verifyUntil the memory cell is in an erased state at least below a predetermined threshold voltageWithout dischargingThe well voltage control means for holding is provided, and thereby the above object is achieved. The memory cell in this case has a floating gate and a control gate which are electrically insulated on a semiconductor substrate between the source region and the drain region.
[0038]
Preferably, the well voltage control means in the semiconductor memory device of the present invention applies a voltage equal to or higher than a voltage applied to the second well region during the erase operation of the memory cell before executing the write operation after executing the erase command to the memory cell. The first well region is supplied first.
[0039]
Further, preferably, the well voltage control means in the semiconductor memory device of the present invention uses the voltage supplied to the first well region in the erased state of the memory cell in the overerased state (predetermined threshold voltage, for example, DC 0.8 V or more). Is held until the process is completed.
[0040]
Further preferably, the well voltage control means in the semiconductor memory device of the present invention sets the voltage after the voltage supplied to the first well region is discharged to the ground level or the positive voltage.
[0041]
Further preferably, the well voltage control means in the semiconductor memory device of the present invention sets the voltage supplied to the first well region to a positive voltage other than the ground potential when the second well region is at the ground potential.
[0042]
With the above configuration, before executing the write operation after executing the erase command or before applying the erase voltage, a voltage higher than the voltage applied to the second well region during the erase operation is supplied to the first well region and supplied to the first well region. Since the voltage is held until the memory cell is in the erased state, the overhead of charging and discharging time to the deep N well surrounding the memory cell when the erase pulse is applied is eliminated, and the erase time is shortened. The potential relationship between the P well PW and the deep N well DW with a simple circuit configuration of a conventional complicated well bias switching circuit (V_PW≦ V_DW) Can always be controlled.
[0043]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments in which a semiconductor memory device of the present invention is applied to a nonvolatile semiconductor memory device will be described with reference to the drawings.
[0044]
FIG. 1 is a configuration diagram showing a circuit and well lines for one block of a memory cell array in a nonvolatile semiconductor memory device according to an embodiment of the present invention. In FIG. 1, memory cells M00 to Mmn are arranged in an array in the vertical and horizontal directions, and the control gates CG of m + 1 memory cells M00 to Mm0 are commonly connected to the word line WL0. The same applies to WLn. The bit line BL0 is commonly connected to the drains D of n + 1 memory cells M00 to M0n, and the same applies to the bit lines BL1 to BLm. A common source line SOURCE is commonly connected to the sources S of the memory cells M00 to Mmn in the same block.
[0045]
A desired word line (for example, WL1) is selected from the word lines WL0 to WLn input to the control gates CG of the memory cells M00 to Mmn, and desired from the bit lines BL0 to BLm connected to the drains D of the memory cells M00 to Mmn. A desired memory cell (for example, M01) is selected by making the bit line BL0 conductive in order to select one bit line (for example, BL0). At this time, the common source line SOURCE connected to the source S of each of the memory cells M00 to Mmn is at the ground (GND) level.
[0046]
The plurality of memory cells M00 to Mmn in the same block have a triple well structure, and their P wells PW (first well type second well regions) are collectively connected to the PWL line. Each of the plurality of memory cells M00 to Mmn in the same block is in a deep N well DW (second conductivity type first well region) surrounding the P well PW, and the deep N well DW is Connected to the DWL line. A predetermined voltage V is applied to the P well PW via the PWL line._PWAnd a predetermined voltage V to the deep N well DW via the DWL line._DWCan be supplied.
[0047]
These predetermined voltages V_PW, V_DWThe well voltage control means of the present invention (corresponding to a conventional well bias switching circuit) controls the output, but since the configuration is substantially the same, the description is simplified and the deep N well DW is connected via the DWL line. Predetermined voltage V_DWOnly a circuit example for charging and discharging the battery will be described.
[0048]
FIG. 2 is a circuit diagram showing a configuration example of a main part of the well voltage control means in the nonvolatile semiconductor memory device of one embodiment of the present invention. In FIG. 2, the well voltage control means 1 corresponds to the level shifter circuit 2 that can output the VPP 12 level or the ground level to the output node DWSEL according to the control signal DWON, the control signal DWONB, and the output voltage of the level shifter circuit 2. A well voltage output circuit 3 that charges or discharges a deep N well DW, and a control signal output circuit 4 that outputs a control signal DWON and a control signal DWONB at a predetermined timing. The level shifter circuit 2 and the well voltage output circuit 3 constitute a well voltage supply circuit. The output node DWOUT is connected to the deep N well DW through the DWL line.
[0049]
The level shifter circuit unit 2 converts the high level of the control signal DWON (the power supply Vcc level of the nonvolatile semiconductor memory device) into the boosted high level VPP12 level, and also maintains the low level (reference voltage 0 V) of the control signal DWON as it is. , A circuit that converts the signal to a low level (reference voltage 0 V) and outputs the voltage to the output node DWSEL. The voltage VPP12 may be input from the outside or generated by boosting the power supply voltage Vcc to a predetermined value by a booster circuit inside the device. The voltage VPP12 level will be described. Since the MOS transistor T2 that outputs the voltage VPPDW uses an nMOS transistor, the voltage VPP12 level input to the gate of the MOS transistor T2 is not limited to the level of the voltage VPPDW. The voltage considering the threshold of T2 and the back gate effect must be set.
[0050]
The well voltage output circuit unit 3 supplies a predetermined voltage VPPDW (V_PW≦ V_DWWhen the output node DWSEL is at the high level (the control signal DWON is at the high level), the MOS transistor T2 is turned on and the voltage VPPDW level is output. The voltage VPPDW may be input from the outside or generated by boosting the power supply voltage Vcc by a booster circuit inside the device.
[0051]
As shown in FIG. 3, the control signal output circuit 4 has a P-well when the erase pulse voltage is applied immediately after the erase sequence is started (after the erase command is executed) and before the program operation (write operation) until the erase pulse voltage is applied. Voltage V supplied to PW_PWThe above supply voltage VPPDW (voltage V_DW) Is first supplied from the node DWOUT to the deep N well DW via the DWL line, and the supply voltage VPPDW (voltage V) to the deep N well DW until the end of the erase sequence._DW), The control signal DWON is output to the level shifter circuit 3 and the control signal DWONB is output to the well voltage output circuit 4.
[0052]
Here, the pulse control to the memory cell when the erase voltage is not applied will be described. During programming, a positive voltage is applied to the control gate CG and the drain D (the drain region of the second conductor) and the source S (the first S) The source region of the two conductors) is set to the ground potential (GND potential), channel hot electrons are generated, and electrons are injected into the floating gate FG. At this time, the P well PW is at the ground (GND) potential (0 V), and if the voltage of the deep N well DW is 0 V or more, a forward bias does not occur with respect to the P well, which causes no problem. In verifying the state of the memory cell in each of tasks 1 to 3 described later, there is a problem if the P well PW is at the ground (GND) potential (0 V) and the voltage of the deep N well DW is 0 V or higher. Absent. That is, the voltage V applied to the P well PW at the time of erasure even when the erase voltage is not actually applied._PWAbove voltage V_DWThere is no problem even if the N is supplied to the deep N well DW.
[0053]
FIG. 4 is a circuit diagram showing a simplified example of the verify circuit used in the present invention. In FIG. 4, a verify circuit 10 includes a bit line selection unit 11 including bit line selection transistors T00 to T0m selected from the bit lines BL0 to BLm of the memory cell array of FIG. 1, and a voltage limiting circuit connected to the bit line selection unit. Drain bias (Drain # bias) circuit 12, load circuit (LOAD) 3 whose output terminal is connected to drain bias (Drain # bias) circuit 12, and whose input terminal is connected to the power supply, and reference for writing state reference Reference cell selection means 14 for selecting one of the cell Cell_PV, the reference cell Cell_EV for erasing state reference, and the over-erased state reference cell Cell_RE, and a drain bias reference for voltage limitation (Drain # bias) connected to the reference cell selection means 14 #Ref) circuit 15 and the output terminal is drain bias A sense circuit S / A that detects a voltage difference between the load circuit (LOAD) 16 connected to the reference (Drain # bias # Ref) circuit 15 and whose input terminal is connected to the power supply and each output terminal of the load circuits 13 and 16. And a verify detection means 17 such as
[0054]
The erasure algorithm of the present invention will be described below with the above configuration. As described above, the present invention is characterized in that the deep N-well DW is connected to the predetermined voltage V immediately after the erase algorithm is started._DWAfter charging, the voltage V_DWIs not discharged until the erasing operation is completed, and the voltage V is_DWThis is in the point of discharging.
[0055]
Before the start of the erasing algorithm, the control signal DWON is at the low level and the control signal DWONB is at the high level, and the reference voltage 0 V is output as the supply voltage to the deep N well DW.
[0056]
Specifically, when the control signal DWON is at the low level, the MOS transistor T2 is turned off. However, when the control signal DWONB is set to the high level after the control signal DWON is set to the low level, the MOS transistor T1 is turned on and N The well DW is discharged to the reference voltage 0V.
[0057]
FIG. 5 is a flowchart showing an example of an erase algorithm of the nonvolatile semiconductor memory device using the well voltage control means of FIG.
[0058]
As shown in FIG. 5, when the erase start command is executed (after execution of the erase start command), first, in step S1, the voltage V applied to the P well PW when the erase pulse is applied_PWAbove voltage V_DW(For example, 6V) is charged to the deep N well DW.
[0059]
Specifically, when the erase algorithm starts, the control signal DWONB is changed to a low level, the MOS transistor T1 is turned off, and then the control signal DWON is changed to a high level. As a result, the MOS transistor T2 is turned on, and the voltage VPPDW is output and charged to the deep N well DW. As a result, the N well DW becomes the voltage VPPDW.
[0060]
Next, preconditions for task 1 (write pulse application; step S2) and write verify (step S3) are performed.
[0061]
First, preconditioning is performed, and all the memory cells in the block to be erased are in a written state (threshold voltage Vth is 4.5 V or more). In this writing, as a writing pulse, a positive voltage (for example, DC8V) is applied to the control gate CG, a positive voltage (for example, DC5V) is applied to the drain D, and the source S and the P well PW are set to the reference voltage 0V. Thus, channel hot electrons are generated in a portion with a high electric field near the drain region, and electrons are injected into the floating gate FG to raise the threshold voltage of the memory cell, thereby bringing the memory cell into a writing state.
[0062]
The potential V of the N well DW at this time_DWMaintains the voltage VPPDW and V_PW≦ V_DWThe relationship is secured.
[0063]
Next, write verify is performed. The write verify is to verify whether or not the memory cell has reached a predetermined threshold voltage Vth (for example, 4.5 V or more) by applying the write pulse as described above.
[0064]
This verify operation will be described in detail with reference to FIGS.
[0065]
A word line (for example, WL0) to be verified is selected from word lines WL0 to WLn input to the control gate CG of the memory cell, and a positive voltage (for example, DC 6.0V) is applied. Note that the reference voltage 0V is applied to the non-selected word lines WL1 to WLn.
[0066]
The common source line SOURCE and P well PW connected to the source S of each memory cell are set to a reference voltage of 0V.
[0067]
Further, in order to select a desired bit line (for example, BL0) from the bit lines BL0 to BLm connected to the drain D of the memory cell, the bit line selection signal CSEL0 is set to the high level to turn on the MOS transistor T00. The other bit line selection transistors T01 to T0m are turned off.
[0068]
In order to verify the threshold voltage Vth of the memory cell, a comparison is made with the threshold voltage of a reference memory cell to which data has been separately written. In order to turn on the MOS transistor connected to the reference cell Cell_PV for writing state reference (threshold voltage 4.5 V or more), the selection signal RSEL_PV is set to the high level to select the reference cell Cell_PV for writing state reference.
[0069]
The same positive voltage (for example, 6 V) as that of the word line WL0 is also applied to the reference cell word line WLref line. The drain D of the memory cell is connected to the memory cell by a drain bus (Drain # bias) circuit 12 and a drain bus reference (Drain # bias # Ref) circuit 15 in consideration of disturbance to the memory cell. The node BL_MEM and the node BL_Ref are limited to be 1V or less.
[0070]
Furthermore, the current from the power source through the load circuits 13 and 16 is supplied to each of the selected memory cell and the reference cell Cell_PV for writing state reference. In the selected memory cell in the memory cell array, a current corresponding to the write state flows.
[0071]
Here, if the threshold voltage of the selected memory cell is higher than the threshold voltage (threshold voltage 4.5 V) of the reference cell Cell_PV for writing state reference, the current flowing through the node BL_MEM is The current flows to the reference-side node BL_Ref. This difference in current value is converted into a difference in voltage value at the nodes SAIN and SAIN_Ref in the input stage of the sense amplifier S / A, and is input to the sense amplifier S / A.
[0072]
In this case, the voltage VSAIN of the node SAIN in the input stage of the sense amplifier S / A becomes higher than the voltage VSAIN # Ref of the node SAIN_Ref due to the voltage drop caused by the load circuits 13 and 16. This is determined by the sense amplifier S / A, and based on the output from the sense amplifier S / A, control is performed so as to stop the application of the subsequent write pulse.
[0073]
Conversely, if the threshold voltage Vth of the selected memory cell remains below the threshold voltage (4.5 V) of the reference cell Cell_PV for writing state reference, the current flowing through the node BL_MEM It becomes larger than the current flowing through the node BL_Ref.
[0074]
In this case, the voltage VSAIN of the node SAIN in the input stage of the sense amplifier S / A becomes lower than the voltage VSAIN # Ref of the node SAIN_Ref due to the voltage drop caused by the load circuits 13 and 16. This is determined by the sense amplifier S / A, and control is performed so that the write pulse is applied again based on the output from the sense amplifier S / A.
[0075]
This verify operation is performed on all the memory cells to be erased, and when the threshold voltage of all the memory cells becomes 4.5 V or higher, the processing of task 1 is completed. In this task 1, since the P well PW is at the reference voltage 0 V in both precondition and verify, the potential V of the deep N well DW is_DWMaintains the voltage VPPDW (for example, DC6V), the above V_PW≦ V_DwThe well voltage relationship is ensured.
[0076]
Next, the erase pulse voltage application (step S4 in FIG. 5) and erase verify (step S5 in FIG. 5) of task 2 will be described.
[0077]
Since the erase pulse voltage is applied for each block or all the blocks at the same time, a negative voltage (for example, −9 V) is applied to all the word lines WL0 to WLn connected to the control gate CG of the memory cell, and the drain D of the memory cell All the bit lines BL0 to BLm connected to, and the common source line SOURCE connected to the source S are brought into an open state (floating state).
[0078]
Further, the P well PW has a positive voltage (for example, DC5V) potential V._PWAt this time, the potential V of the N well DW_DWMaintains the voltage VPPDW (for example, DC6V)._PW≦ V_DWThe well voltage relationship is ensured.
[0079]
Next, erase verification will be described.
[0080]
The erase verify is theoretically the same as the previous write verify. The difference is that an erase state reference cell Cell_EV (threshold voltage Vth is 3.0 V) is selected and compared as a reference cell. Since the rest is the same, the description thereof is omitted.
[0081]
In this way, by repeating the erase pulse voltage application and erase verify, the threshold voltages of all the memory cells become 3.0 V or less, and the processing of task 2 ends.
[0082]
At the time of erase verify, since the P well PW has a reference voltage of 0 V, the potential V of the N well DW_DWMaintains the voltage VPPDW (for example, DC6V), the above V_PW≦ V_DwThe well voltage relationship is ensured. Therefore, through task 2, the potential V of N well DW_DWMaintains the voltage VPPDW (for example, DC6V), the above V_PW≦ V_DwThe well voltage relationship is ensured.
[0083]
Subsequently, the post-condition of task 3 (write pulse application; step S6 in FIG. 5) and over-erase verification (step S7 in FIG. 5) will be described.
[0084]
In Task 3, as described above, soft programming (light writing) is performed on the memory cell having a negative threshold voltage due to over-erasing, and the threshold voltage Vth is 0.8 V or higher. Since the over-erased state reference cell Cell_RE (threshold voltage DC 0.8 V) is selected at the time of verifying, and only the comparison is made. Detailed description is omitted. In task 3, since the P well PW is at the reference voltage 0 V in both the post-condition and the over-erase verification, the potential V of the N well DW is_DWMaintains the voltage VPPDW._PW≦ V_DwThe well voltage relationship is ensured.
[0085]
Finally, in step S8, the supply voltage VPPDW to the N well DW is discharged.
[0086]
The control signal DWON to the well voltage supply circuit to the N well DW shown in FIG. 2 is set to the low level (reference voltage 0 V), and the MOS transistor T2 is turned off. Thereafter, the control signal DWONB is set to the high level, the MOS transistor T1 is turned on, and is pulled to the reference voltage 0V, thereby discharging the supply voltage VPPDW to the N well DW.
[0087]
In the previous task 3, since the P well PW is already at the reference voltage 0V, the above V_PW≦ V_DwThe well voltage relationship is maintained, and this is not reversed. Therefore, in the present invention, the above V_PW≦ V_DwThe well voltage relationship is reversed, and there is no problem that a forward bias current flows.
[0088]
As described above, according to the present embodiment, the control signal output circuit 4 has the voltage V supplied to the P well PW when the erase pulse voltage is applied before the program operation (write operation) immediately after the start of the erase sequence._PWThe above supply voltage VPPDW (voltage V_DW) Is first supplied to the deep N well DW via the node DWOUT, and the control signal DWON is output to the level shifter circuit 3 so as to maintain the supply voltage VPPDW to the deep N well DW until the end of the erase sequence. Since the control signal DWONB is output to the well voltage output circuit 4, the N well DW is charged at the beginning of the erase operation, the N well DW is finally discharged, and the N well DW is charged / discharged only once. Therefore, even if the erase pulse application is repeated, V / V during charge / discharge_PW≦ V_DwThus, the conventional delay time for ensuring the well voltage relationship is not necessary, and the erasing time can be increased.
[0089]
In addition, since the conventional delay time is shortened, it is not necessary to finely control the timing, which can be realized by the simple well voltage control means 1, and it is necessary to increase the switching speed of the charge / discharge voltage of the N well DW having a large stray capacitance. Therefore, it is possible to reduce the circuit scale including downsizing of the output stage transistor.
[0090]
Furthermore, since the N well DW needs to be charged / discharged only once in the erasing sequence, charging / discharging of the N well DW having a large stray capacitance can be reduced, and power consumption can be reduced.
[0091]
In this embodiment, the charge / discharge timing to the N well DW is provided before and after the tasks 1 to 3, the N well DW is charged before preconditioning, and the N well DW is discharged after postconditioning. However, the present invention is not limited to this, and may be at least before and after the task 2 for applying the erase pulse. Further, only the charge to N well DW may be before task 2, and only the discharge to N well DW may be after task 2.
[0092]
In the present embodiment, the potential after the discharge of the N well DW is set to the reference voltage 0V, but is not the reference voltage 0V but a positive voltage (the power supply voltage Vcc of the nonvolatile semiconductor memory device) as shown in FIG. May be.
[0093]
In FIG. 6, when a new level shifter circuit is connected in parallel and the control signal DWONB is at a high level, this high level is boosted to the VPP12 level, the MOS transistor T1 is turned on, and the power supply voltage Vcc is supplied to the N well DW. Is.
[0094]
Instead of completely discharging to 0V as shown in FIG. 6, only a slight discharge to the Vcc level is required, so that higher speed and lower power consumption can be further achieved.
[0095]
Although not specifically described in the present embodiment, the present invention is effective for an erasing method of a nonvolatile semiconductor memory device having a configuration in which an N well DW is disposed so as to surround a P well PW. The present invention can be applied regardless of the configuration of the nonvolatile semiconductor memory device such as NAND type, NOR type, and AND type.
[0096]
In this embodiment, the P well PW of each memory cell in the same block is surrounded by one N well DW. However, the present invention is not limited to this, and the N well DW includes the P well PW of each memory cell. It is good also as a structure to surround. Also in this case, each deep N well DW surrounding the P well PW of each memory cell in the same block may be connected to the DWL line in a lump.
[0097]
【The invention's effect】
As described above, according to the present invention, when the erase pulse is applied, the well voltage can be supplied by the simple well voltage control means without damaging the well voltage relationship that makes the potential of the N well DW deeper than the potential of the P well PW. The timing overhead can be eliminated, and the erase time can be shortened.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a circuit for one block of a memory cell array in a nonvolatile semiconductor memory device according to an embodiment of the present invention;
FIG. 2 is a circuit diagram showing a configuration example of a main part on the deep N well side of the well voltage control means in the nonvolatile semiconductor memory device of one embodiment of the present invention;
FIG. 3 is a timing diagram of a well supply voltage when an erase voltage is applied according to the present invention.
FIG. 4 is a circuit diagram schematically showing an example of a verify circuit used in the present invention.
FIG. 5 is a flowchart showing an example of an erasing algorithm according to the present invention.
FIG. 6 is a circuit diagram showing a configuration example of a deep N well side of well voltage control means in another embodiment of the present invention.
FIG. 7 is a cross-sectional view showing a first conventional example of a flash memory cell having a floating gate structure.
FIG. 8 is a cross-sectional view showing a second conventional example of a flash memory cell having a floating gate structure.
FIG. 9 is a diagram showing threshold voltage distributions of memory cells after erasing and after programming.
FIG. 10 is a timing diagram of a well supply voltage used in a conventional channel erase method.
FIG. 11 is a flowchart showing an example of a conventional erasing algorithm.
[Explanation of symbols]
1 Well voltage control means
2-level shifter circuit
3 well voltage output circuit
4 Control signal output circuit
10 Verify circuit
DWON, DWONB control signal
M00 to Mmn memory cell
DW Deep N-well
PW P well
V_DW    Deep N-well DW potential
V_PWPotential of P well PW

Claims (5)

A first conductivity type first well region disposed in the first conductivity type semiconductor substrate; a first conductivity type second well region disposed in the first well region; and the second well region In a semiconductor memory device having a memory cell having a source region and a drain region of a second conductor formed in
A voltage higher than the voltage applied to the second well region during the erase operation of the memory cell is supplied to the first well region at least before the erase voltage is applied after execution of the erase command to the memory cell, and the first well Semiconductor memory device having well voltage control means for holding the voltage supplied to the region without discharging until the memory cell is in an erased state at least below a predetermined threshold voltage by repeating erase voltage application and erase verify . The well voltage control means, the prior write operation performed after the erase instruction execution for the memory cell, supplying a voltage higher than the voltage applied to the second well region during the erase operation of the memory cells in said first well region The semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 1, wherein the well voltage control means holds the voltage supplied to the first well region until a memory cell in an over-erased state is in an erased state equal to or higher than a predetermined threshold voltage.   The semiconductor memory device according to claim 1, wherein the well voltage control unit sets a voltage after the voltage supplied to the first well region is discharged to a ground level or a positive voltage.   The semiconductor device according to claim 1, wherein the well voltage control unit sets the voltage supplied to the first well region to a positive voltage equal to or higher than a ground potential when the second well region is in a ground potential state. Storage device.

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