JPH1116383A - Electrically writable/erasable nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect a memory cell to be erased from an erasing voltage exceeding the dielectric strength of the memory cell by a method wherein the gate voltage of a dummy memory cell whose floating gate and control gate are short-circuited is controlled so as to be lower than the floating gate voltage of the memory cell to be erased to clamp the erasing voltage. SOLUTION: A dummy memory cell Mdummy has the same construction as memory cell transistors M11-Mnm and its floating gate and control gate are short-circuited. Its drain is opened, its source is connected to the common source line of the memory cell transistors M11-Mnm and a constant voltage Vconst, for instance -3--4 V, is applied to its gate. In this state, the source dielectric strength of the dummy memory cell Mdummy is so set as to be lower than the source dielectric strengths of the memory cells. In an erasing operation, a voltage obtained by clamping an erasing power supply voltage Vpp in this state is supplied to the common source line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically writable / erasable nonvolatile semiconductor memory device, and more particularly to an erasing circuit therefor.

[0002]

2. Description of the Related Art Conventionally, in a nonvolatile semiconductor memory device of this kind, as disclosed in, for example, Japanese Patent Application Laid-Open No. 1-273357, the drain potential of a memory cell during an erase operation is set between the drain of a memory cell transistor and a semiconductor substrate. Clamping is performed at a voltage lower than the breakdown voltage to prevent avalanche breakdown, prevent deterioration in writing characteristics, erasing characteristics, and the number of times of rewriting, and realize a highly reliable nonvolatile semiconductor memory device.

FIG. 7 is a diagram showing a part of a circuit configuration of a conventional nonvolatile semiconductor memory device. In FIG. 7, Vpp1
Is a write power supply, Vpp2 is an erase power supply, MN1 is a field-effect transistor having a write control signal Tpg as a gate input, IN
V1 is an inverter circuit which receives the erase control signal Ter as an input,
MN2 is a field-effect transistor having an output of INV1 as a gate input, MN3 is a field-effect transistor having an erase control signal Ter as an input, D1 and D2 are diodes, D1,.
Dm is a digit line, W1, W2, and Wn are word lines, S is a source line, and Mc is a split gate type memory cell transistor.

Next, the operation of the nonvolatile semiconductor memory device shown in FIG. 7 will be described. At the time of the erase operation of the memory cell, the field effect transistor MN1 is turned off by the Tpg signal which is the write control signal, and the erase control signal Ter is turned off.
The signal turns on the field effect transistor MN3, and the output signal of the inverter circuit INV1 turns on the field effect transistor MN2. As a result, the erase voltage Vpp2 is applied to the digit line (Di). At this time, since the field effect transistor MN3 is turned on, the potential of the digit line (Di) is clamped by the diode D2.

Next, a description will be given with reference to FIG. 8 showing IV (current-voltage) characteristics. In FIG. 8, curves Ier0, Ier
E denotes the IV curve of the memory cell transistor, Ier0 denotes the start of erasing, and IerE denotes the IV curve at the end of erasing. L is a load curve (load curve at the time of erasure). When erasing is started, the digit potential rises from VA, but is clamped at VL2 (about 12 V) by the diode D2 and does not rise any more. Since VL2 is lower than a breakdown voltage VBD between the drain and the semiconductor substrate of about 18 V, no avalanche breakdown occurs. Therefore, damage to the gate oxide film near the drain is reduced.

[0006] The nonvolatile semiconductor memory device shown in FIG.
5 is an example of a split gate type memory cell transistor. High voltage is applied to the source of the memory cell transistor to perform erasing.

In the case of a source erase / NOR type memory cell transistor, the configuration shown in FIG. 9 and the IV characteristics shown in FIG. 10 are obtained. Here, D1 to Dm are digit lines, M11 to Mnm are NOR type memory cell transistors, V
pp is a power supply for erasing, PM1 is a P-type field effect transistor,
NM1 is an N-type field effect transistor, and D is a diode element.

At the time of an erase operation, an erase control signal ERASE
Due to ￣, the P-type field-effect transistor PM1 is turned on, the N-type field-effect transistor NM1 is turned off, and the erase voltage Vpp is applied to the source line. In the initial stage of erasing, the source potential of the memory cell becomes VSO, and the source potential increases as erasing progresses. However, when the voltage exceeds the withstand voltage of the diode D (〜１０10 V), the source voltage is clamped by the diode D.

[0009]

However, the above-described erase circuit of the conventional nonvolatile semiconductor memory device has the following problems.

(1) The first problem is that the gate oxide film is deteriorated by carriers caused by band-to-band tunneling (see FIG. 10) at the time of repetitive write / erase operations.

The reason is that, in order to suppress carriers caused by avalanche breakdown, the erasing voltage is clamped by a simple diode, but it is not possible to suppress band-to-band tunneling with a simple diode. .

(2) The second problem is that the set value of the breakdown voltage of the diode element must be determined in consideration of the variation in the breakdown voltage of the memory cell source.

The reason is that the withstand voltage of the diode element does not depend on the voltage of the floating gate of the memory cell which affects the withstand voltage of the memory cell.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and has as its object to reduce the deterioration of a tunnel oxide film at the time of repetition of writing / erasing and to improve the reliability of a nonvolatile memory. It is to provide a semiconductor memory device.

Another object of the present invention is to provide a nonvolatile memory device which suppresses deterioration of a tunnel oxide film at the time of repetition of writing / erasing so that a source voltage of a memory cell at the time of erasing does not cause inter-band tunneling. It is to provide a semiconductor memory device.

[0016]

In order to achieve the above object, an erasing circuit of a nonvolatile semiconductor memory device according to the present invention comprises a band for a memory cell to be erased, the erase voltage being applied to the source of the memory cell to be erased. This is to suppress the voltage below the voltage at which the inter-tunneling phenomenon occurs. More specifically, a memory cell matrix composed of a plurality of floating gate type memory cell transistors, and means for applying an erase voltage to source lines of the plurality of memory cells,
Means for clamping the erase voltage to a value equal to or lower than the source withstand voltage of the floating gate type memory cell transistor.

[0017]

Embodiments of the present invention will be described below. According to the embodiment of the present invention, means (PM1 in FIG. 1) for supplying an erase voltage to the source of the memory cell transistor to be erased according to the erase control signal, and the erase voltage applied to the source of the memory cell transistor should be erased. Means for clamping in accordance with the state of the memory cell. This clamp means controls a dummy memory cell (Mdummy) in which the floating gate and control gate of a normal memory cell are short-circuited, and controls the gate voltage of the dummy memory cell to a potential lower than the floating gate of the memory cell transistor to be erased. And a dummy memory cell transistor gate control circuit (see FIG. 5).

The gate voltage of the dummy memory cell is always
If the voltage is controlled to be lower than the floating gate voltage of the memory cell to be erased, the source withstand voltage of the dummy memory cell becomes lower than the source withstand voltage of the memory cell to be erased.
The applied erase voltage is always clamped to the source breakdown voltage of the dummy memory cell by the inter-band tunneling current generated in the dummy memory cell. Thus, a voltage exceeding the withstand voltage is not applied to the source of the memory cell to be erased.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[Embodiment 1] FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention. In FIG. 1, M11 to Mnm
Is a floating gate type memory cell transistor,
D1 and Dm are digit lines connected to the drains of the memory cell transistors, and W1, W2 and Wn are word lines connected to the gates of the memory cell transistors. Vpp is an erasing power supply, PM1 is a source and an erasing power supply (Vpp), and a gate is an erasing control signal ERAS.
E￣, a P-type field effect transistor having a drain connected to a common source line of a plurality of memory cells, NM1 a source at a reference potential, a gate at an erase control signal ERASE￣, and a drain at a common source of the plurality of memory cells. An N-type field effect transistor connected to the line, Mdummy, shorts the control gate and the floating gate, a constant voltage (Vconst) is applied to this gate, the drain is open, and the source is the common source of the plurality of memory cells. A memory cell transistor connected to the line (hereinafter referred to as a "dummy memory cell").

At the time of the erase operation, the ERASE signal goes low, the N-type transistor (NM1) is turned off, the P-type transistor (PM1) is turned on, and the common source line of a plurality of memory cells is connected. Erase voltage V
pp is applied.

FIG. 3A shows a cross section of a memory cell transistor, and FIG. 3B shows a cross section of a dummy memory cell Mdummy. As shown in FIG. 3B, the dummy memory cell Mdummy has exactly the same structure as the memory cell transistor except that the control gate and the floating gate are short-circuited.

Next, the operation of one embodiment of the present invention will be described with reference to the IV characteristics shown in FIG. In FIG.
L is an erase load line, Is (d) is a dummy memory cell Mdummy
Is the IV curve of the source, Is (m) 0 is the IV curve of the memory cell transistor source at the start of erasing, and Is (m) E is the IV curve of the memory cell at the completion of erasing.

As shown in FIG. 2, the IV curve of the source of the memory cell transistor is relatively low at the start of erasing, that is, when the potential of the floating gate of the memory cell is sufficiently low (for example, -2 to -3 V). Inter-band tunneling current starts to flow at low source voltage (Is (m)
0). As erasing progresses, the potential of the floating gate of the memory cell transistor increases (for example, 0
V), the source voltage at which the inter-band tunneling current starts to flow rises (Is (m) E).

Here, the source withstand voltage of the dummy memory cell Mdummy is reduced by setting the gate potential of the dummy memory cell Mdummy lower than the floating gate potential of the memory cell at the start of erasing (for example, -3 to -4 V). It can be set lower than the source breakdown voltage of the memory cell.

As a result, the erase voltage applied to the plurality of memory cell sources is clamped by the source breakdown voltage of the dummy cell, so that the erase voltage causing band-to-band tunneling is not applied to the plurality of memory cell sources.

Further, since the dummy memory cells are manufactured by the same manufacturing process as the plurality of memory cells, manufacturing variations in the diffusion process are reduced.

Second Embodiment Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 shows a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an example of FIG.

The basic structure is the same as that of the first embodiment. However, in this embodiment, a dummy memory cell (Mdumm
The difference lies in that a dummy cell transistor gate control circuit 101 that changes the gate signal in y) according to the erased state of a plurality of memory cells is not fixed to a constant value.

As a result, in the second embodiment of the present invention, as shown in FIG. 6, a plurality of memory cells always have a maximum voltage lower than a voltage causing an inter-band tunneling phenomenon. Of memory cell sources. As a result, the erasing time can be shortened as compared with the first embodiment.

Here, the gate voltage Vg (Dummy) applied to the dummy memory cell Mdummy is lower than the floating gate voltage VF (MAX) of the memory cell having the highest threshold voltage among the plurality of memory cells. There must be.

VF (MAX) is the threshold voltage of the memory cell having the highest threshold voltage, VTH (MAX), the capacitance between the floating gate and the control gate is C1, and the capacitance between the floating gate and the substrate is C2. When the threshold voltage of the memory cell viewed from the floating gate is VTF, the following equation (1) is obtained.

[0033]

(Equation 1)

Therefore, the gate voltage Vg (Dummy) applied to the dummy memory cell Mdummy is given by the following equation (2) (see also FIG. 4).

[0035]

(Equation 2)

Here, α is a margin between the source withstand voltage of the memory cell and the source withstand voltage of the dummy cell.
About V.

Specifically, VTF = 1.5 V, C1 / C2 =
0.5, VTM (MAX) is 7V ~ 3V, α = 1V,
Vg (Dumny) is about -2 to -0.5V.

FIG. 4 is a diagram showing the relationship between the source voltage (Vs) and the memory cell threshold voltage (Vtm). The gate voltage Vg (Dummy) of the dummy memory cell is controlled to be always lower than the floating gate voltage of the memory cell to be erased. In this case, since the source breakdown voltage of the dummy memory cell is lower than the source breakdown voltage of the memory cell to be erased,
The erase voltage applied to the plurality of memory cell sources is clamped to the source breakdown voltage of the dummy memory cell by the inter-band tunneling current generated in the dummy memory cell, and a voltage exceeding the breakdown voltage is applied to the plurality of memory cell sources. No erase voltage is applied which would cause band-to-band tunneling.

[0039]

As described above, according to the present invention,
The erase voltage applied to the memory cell can be clamped to a voltage lower than the voltage at which the band-to-band tunneling phenomenon occurs at the memory cell source, whereby the memory cell gate oxide film due to repeated writing / erasing can be performed. This has the effect of reducing the damage to the device.

The reason is that, in the present invention, the gate voltage of the dummy memory cell is always kept lower than the potential of the floating gate of the memory cell to be erased, so that the band-to-band tunneling current generated in the dummy memory cell causes This is because the source voltage of the memory cell to be erased can be clamped.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an IV curve in one embodiment of the present invention.

3A is a cross-sectional view of a memory cell, and FIG. 3B is a cross-sectional view of a dummy memory cell.

FIG. 4 is a diagram showing a relationship between a source voltage and a memory cell threshold voltage in one embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 6 is a diagram showing an IV curve according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration of a conventional example.

FIG. 8 is a diagram showing an IV curve of the circuit of FIG. 7;

FIG. 9 is a diagram showing a configuration of a second conventional example.

FIG. 10 is a diagram showing an IV curve of the circuit of FIG. 9;

[Explanation of symbols]

 D Diode element Di, D1, DM digit line INV1 Inverter circuit Mc, M11 to Mmn Memory cell source transistor Mdummy Dummy memory cell NM1 N-type transistor PM1 P-type transistor W1, W2, Wn Word line

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (3)

[Claims] A memory cell matrix comprising a plurality of floating gate type memory cell transistors; means for applying an erasing voltage to source lines of the plurality of memory cells; Means for clamping to a source breakdown voltage or less; and an electrically writable / erasable non-volatile semiconductor memory device, characterized by comprising: 2. The floating gate type memory cell transistor according to claim 2, wherein said means for clamping said erase voltage to a source withstand voltage of said floating gate type memory cell transistor is short-circuited between a floating gate and a control gate of said floating gate type memory cell transistor.
A source terminal of the dummy memory cell is connected to a source line of the plurality of floating gate type memory cell transistors, and a gate terminal of the dummy memory cell is connected to the floating gate before erasing is started. 2. The electrically writable / erasable nonvolatile semiconductor memory device according to claim 1, wherein a potential lower than a floating gate voltage of the type memory cell transistor is applied. 3. The memory cell transistor (“dummy”), wherein the means for clamping the erase voltage to a source withstand voltage of the floating gate memory cell transistor or less short-circuits a floating gate and a control gate of the floating gate memory cell transistor. Memory Cell "
A source terminal of the dummy memory cell is connected to source lines of the plurality of floating gate transistors,
The gate terminal is connected to the output of the voltage supply means, and the voltage supply means supplies a potential lower than the floating gate potential of the floating gate type memory cell transistor to be erased. 2. The electrically programmed / erased memory according to claim 1, wherein when the floating gate potential of the floating gate type memory cell transistor changes, the floating gate potential becomes a maximum allowable value according to the change. Possible nonvolatile semiconductor memory device.