KR100191315B1 - Loop filter having variable bandwidth - Google Patents

Abstract

The present invention relates to a loop filter having a variable bandwidth. The present invention reduces the bandwidth selection range by using a fixed shift portion instead of the multiplier used in the conventional loop filter, but reduces the overall price by reducing the overall hardware amount, and there is no delay caused by the multiplier. This provides a variable bandwidth loop filter with better performance.

Description

Bandwidth-variable loop filter

1 is a block diagram of a conventional bandwidth-variable loop filter.

2 is a block diagram of a loop-variable loop filter according to the present invention.

3 is a view showing the configuration of the first shift unit 211 in FIG.

* Explanation of symbols for main parts of the drawings

21: first bandwidth variable portion 23: second bandwidth variable portion

ctrl1: first bandwidth variable control signal ctrl2: second bandwidth variable control signal

The present invention relates to a loop filter capable of varying the bandwidth mainly used in digital communication.

In general, a timing recovery circuit and a carrier recovery circuit used in a digital communication receiver include a loop filter for the purpose of noise reduction. Typically, the loop filter uses a large number of first order low pass filters. At this time, the bandwidth of the loop filter uses a wide bandwidth in the acquisition mode, whereas a narrow bandwidth is used in the tracking mode. Therefore, the loop filter should be able to vary with at least two bandwidths. As described above, a conventional loop filter that can be changed to two or more bandwidths will be described with reference to FIG.

1 is a block diagram showing a first order low pass filter used as a general loop filter.

As shown in FIG. 1, the apparatus of FIG. 1 includes a first multiplier 11 and a second multiplier 13 for multiplying the applied data S and the filter coefficients K1 and K2 calculated by the user. . The first adder 15 is connected to the output terminal of the second multiplier 13. In order to integrate the output of the second multiplier (13), the first adder (15) delays the output of the second multiplier (13) by one clock through the delay unit (17) and feeds back the incoming signal and the current input signal. We add. A second adder 19 is connected to the output terminal of the first adder 15 and the first multiplier 11 to add both outputs. The transfer function of the apparatus of FIG. 1 configured as described above is expressed as follows.

Accordingly, the apparatus of FIG. 1 may vary the bandwidth according to the filter coefficients K1 and K2 as the first-order low pass filter.

The conventional apparatus configured as described above has an advantage of varying various types of bandwidths, but delays occur due to the multipliers 11 and 13 included in the conventional apparatus, which adversely affects the entire loop. In addition, since the general loop filter requires only two bandwidths as described above, there is no need to use a complex multiplier having a configuration capable of varying various types of bandwidths as in the apparatus of FIG. In addition, multipliers have been complicated, and the amount of hardware has increased, which has been a considerable burden in terms of price.

Accordingly, an object of the present invention is to provide a variable bandwidth loop filter that can satisfy the low cost and the performance improvement at the same time to solve the above problems.

A feature of the present invention for achieving the above object is a first bandwidth variable control signal for shifting a predetermined bit input data by a predetermined number of bits in the apparatus for variable bandwidth of the loop filter, and inputs the shifted data a first bandwidth variable section 21 for combining according to (ctrl1) to output data having a desired bandwidth, and shifting input data of a predetermined bit by a predetermined number of bits, and second bandwidth variable for inputting the shifted data. A second bandwidth variable unit 23 for combining the control signal ctrl2 and outputting data having a desired bandwidth, and a first bandwidth for adding the output data and the feedback input data of the second bandwidth variable unit 23; An adder 25, a delayer 27 for delaying the output data of the first adder 25 by one clock and feeding it back to the first adder 25, and the first bandwidth variable 21 and the first bandwidth. 1 addition However in a second variable bandwidth loop filter as possible, including adding means (29) for adding and outputting the output data (25).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a loop-variable loop filter according to the present invention. As shown, in the apparatus of FIG. 1, the first multiplier 11 and the second multiplier 13 are replaced with the first bandwidth variable 21 and the second bandwidth variable 23 in the apparatus of FIG. The first bandwidth variable portion 21 and the second bandwidth variable portion 23 include two shift portions, one logical product gate, and one adder, respectively.

The apparatus of the present invention configured as described above will be described in more detail.

First, the input signal S is input to the first bandwidth variable 21 and the second bandwidth variable 23. The first shift 211 and the second shift part 213 in the first bandwidth variable part 21 shift the applied signal S by a predetermined number of bits through a predetermined simulation. The output of the first shifter 211 is applied to the first adder 217. An output of the second shift unit 213 is input to the first logical gate 215. The first bandwidth variable control signal ctrl1 is connected to the other input terminal of the first logical gate 215. That is, when the first bandwidth variable control signal ctrl1 is the control signal 0, the output of the first logical gate 215 is also 0. Therefore, the first adder 217, which adds the output of the first shift unit 211 and the output of the first logical gate 215, outputs only the output of the first shift unit 211 as it is. If the first bandwidth variable control signal ctrl1 is the control signal 1, the output of the first logical gate 215 is the same as the output of the second shift unit 213. Therefore, the first adder 217 sums the output of the first shift unit 211 and the output of the second shift unit 213 and outputs the sum. The output of the first adder 217 is applied to the fourth adder 29.

Meanwhile, the third shift unit 213 and the fourth shift unit 233 in the second bandwidth variable unit 23 shift the applied signal S by a predetermined number of bits through a predetermined simulation. The output of the third shift unit 231 is applied to the second adder 237. The output of the fourth shift unit 233 is input to the second logical gate 235. The output of the second logical gate 235 is applied to the second adder 237. A second bandwidth variable control signal ctrl2 is connected to the other input terminal of the second logical gate 235. That is, when the second bandwidth variable control signal ctrl2 is the control signal 0, the output of the second logical gate 235 is also 0. Therefore, the second adder 237 that adds the output of the third shift unit 231 and the output of the second logical gate 235 to output only the output of the third shift unit 231 as it is. If the second bandwidth variable control signal ctrl2 is the control signal 1, the output of the second logical gate 235 is the same as the output of the fourth shift unit 233. Therefore, the second adder 237 sums the output of the third shift unit 231 and the output of the fourth shift unit 233 and outputs the sum. The output of the second adder 237 is applied to the third adder 25. The third adder 25 feeds back the input signal through the delayer 27 to integrate the input signal, feeds it back, adds it with the current input signal, and outputs the fourth signal 29. The fourth adder 29 adds the output of the first adder 217 and the output of the third adder 25 to the output terminal.

In the present invention configured as described above, a loop filter having four types of bandwidths is implemented by adjusting the first bandwidth variable control signal crtl1 and the second bandwidth variable control signal ctrl2. That is, the first bandwidth variable control signal ctrl1 has a value of 1 or 0 and the second bandwidth variable control signal ctrl2 has a value of 1 or 0, thereby generating four control signals (two types). × 2 types = 4 types). The outputs of the first bandwidth variable portion 21 and the second bandwidth variable portion 23 in the four cases as described above are plotted as follows.

The user can select and use the most suitable bandwidth among the above four cases.

The structure of the first shift portion 211 to the fourth shift portion 233 in the present invention will be described with reference to FIG.

3 is a diagram illustrating an internal configuration of the first shift unit 211. Since the structures of the second shift portion 213 to the fourth shift portion 233 are the same as the structure of the first shift portion 211, a description thereof will be omitted. As shown, if the input data is t bits and the first shift unit 211 defines that the input data is shifted in the left or right direction by K bits, the first shift unit 211 has the lower K bits of the input. Alternatively, discard the upper K bits of the input. In FIG. 3, since the filter coefficient is usually 1 or less, the lower K bits of the input are discarded. For example, if the input is 8 bits and the value is 00011000 and the value K is 2 and the first shift unit 211 is passed, 00011000 becomes 00000110. That is, 00011000 is 24 in decimal, and 00000110 is 6 in decimal. That is, the first shift unit 211 is 2 to the incoming number It will function as a multiplier, such as multiplying by. In addition, if the number of shifted bits of the first shift unit 211 to the fourth shift unit 233 is determined through sufficient simulation, and the output terminals corresponding to the input bits are connected according to the determined value, the first shift unit 211 In the fourth shift unit 233, no delay occurs. The delay of the loop filter not only makes theoretical prediction of various parameters impossible, but also reduces the performance, so reducing the possible delay is very important for the performance. Therefore, the present invention has the effect of expecting better performance by reducing the delay. In addition, since the invention does not use the multiplier used in FIG. 1, the amount of hardware is reduced, resulting in a cost reduction effect.

Claims (4)

In the apparatus for varying the bandwidth of the loop filter, data having a desired bandwidth by shifting input data of a predetermined bit by a predetermined number of bits and combining the shifted data according to the input first bandwidth variable control signal (ctrl1). A first bandwidth variable section 21 outputting the data; The second bandwidth variable unit 23 shifts the input data of a predetermined bit by a predetermined number of bits and combines the shifted data according to the input second bandwidth variable control signal ctrl2 to output the data having a desired bandwidth. ; First adding means (25) for adding and outputting the output data of the second bandwidth variable section (23) and the data inputted to the feedback; A delay unit 27 for delaying the output data of the first adding means 25 by one clock and feeding back to the first adding means 25; And second adding means (29) for adding and outputting the first bandwidth variable portion (21) and the output data of the first adding means (25). The bandwidth variable loop filter of claim 1, wherein the number of bits is preset through simulation. 2. The apparatus of claim 1, wherein the first bandwidth varying unit (21) comprises: a first shift unit (211) for shifting the input data of the predetermined bit by a plurality of preset bits; A second shift unit 213 for shifting the input data of the predetermined bit by a plurality of preset bits; A first logical gate 215 for combining and outputting the shifted data of the second shift unit 213 according to the first bandwidth variable control signal; And a first adder 217 for outputting a desired bandwidth by adding the output of the first shift unit 211 and the output of the first logical gate 215. . 2. The apparatus of claim 1, wherein the second bandwidth variable section (23) comprises: a third shift section (231) for shifting the input data of the predetermined bit by a plurality of preset bits; A fourth shift unit 233 for shifting the input data of the predetermined bit by a predetermined number of bits; A second logical gate 235 for outputting the combined data by the fourth shift unit 233 according to the second bandwidth variable control signal; And a second adder 237 for adding the output of the third shift unit 231 and the output of the second logical gate 235 to output a desired bandwidth. .