KR100191018B1 - Semiconductor integrated circuit device - Google Patents

Abstract

Related to semiconductor technology, in order to improve moisture resistance, a plurality of aluminum wirings having a predetermined film thickness and a CVD method using tetraethoxy silane as a source gas are regularly arranged at predetermined intervals on a semiconductor substrate. 10. A semiconductor integrated circuit device having a first insulating film formed on an aluminum wiring by using a second insulating film and a second insulating film formed on the first insulating film by a plasma CVD method, wherein the first insulating film is 1/2 of an interval of the aluminum wiring. It has the above film thickness.

By using such an apparatus, moisture resistance can be improved.

Description

Semiconductor integrated circuit device

1 is a cross-sectional view of an essential part of a DRAM according to Embodiment 1 of the present invention.

2 is a partial cross-sectional perspective view of a resin-encapsulated semiconductor device which seals and blocks the DRAM.

3 is a chip layout diagram of the DRAM.

4 is an equivalent circuit diagram of an essential part of a memory cell array of the DRAM.

5 is a plan view of an essential part of a memory cell array of the DRAM.

6 and 7 are plan views of main parts in a predetermined manufacturing process of the memory cell array of the DRAM.

8 is a diagram showing a relationship between a target voltage and a specific resistance value during sputtering of a film used for the DRAM.

9 and 10 show the relationship between the X-ray incidence angle and the X-ray diffraction spectrum of the film.

11 and 13 are schematic plan views illustrating a boundary area between the memory cell array and a peripheral circuit.

12 and 14 are enlarged plan views of main portions of the boundary region.

Fig. 15 is a sectional view of principal parts at different positions of the DRAM.

16 to 49 are cross-sectional views of principal portions showing the DRAM in each manufacturing process.

50 is a sectional view of an essential part of a fuse element of the DRAM;

51 to 53 are sectional views of principal parts showing the fuse element in each manufacturing step.

FIG. 54 is a diagram showing the relationship between the temperature and the vapor pressure of a film used in the DRAM.

55 is a diagram showing etching characteristics used in the DRAM.

56 to 58 are cross-sectional views of principal parts of a DRAM according to a second embodiment of the present invention.

59 and 60 are cross-sectional views of principal parts of a DRAM according to a third embodiment of the present invention.

Fig. 61 (a) shows the relationship between the deposition time and the gas flow rate of the film used in the DRAM.

61 (b) shows the relationship between the deposition time of the membrane and the amount of reaction by-products generated.

62 is a schematic structural diagram of a CVD apparatus according to Embodiment 4 of the present invention.

63 and 64 are schematic diagrams of principal parts of the CVD apparatus.

65 is a timing chart showing the opening and closing operation of the gas valve of the CVD apparatus according to the fifth embodiment of the present invention.

FIG. 66 is a timing chart showing a gas flow rate of the CVD apparatus. FIG.

67 is a schematic structural diagram of the CVD apparatus.

68 to 71 are cross-sectional views of principal parts each of the manufacturing steps of the DRAM according to the sixth embodiment of the present invention.

Fig. 72 is a plan view of the essential parts of a predetermined manufacturing process of DRAM according to the seventh embodiment of the present invention.

73 to 76 are cross-sectional views of principal parts showing the DRAM in each manufacturing step.

77 is a plan view of an essential part of a predetermined manufacturing process of another example of the DRAM.

78 to 80 are main sectional views showing another example of the DRAM for each manufacturing process.

81 to 84 are main sectional views showing another example of the DRAM for each manufacturing process.

85 to 88 are cross-sectional views of the essential parts showing another example of the DRAM in each manufacturing process.

89 is an alignment tree diagram of the DRAM according to the eighth embodiment of the present invention.

90 is a sectional view of principal parts of a target mark portion of a DRAM according to Embodiment 9 of the present invention.

91 is a conceptual diagram of photolithographic technology used in the manufacturing process of DRAM according to the tenth embodiment of the present invention.

92 is a process flow diagram of the photolithographic technique.

93 is a structural diagram of a material used in the photolithographic technique.

94 is a view showing properties of the material.

95 is a diagram for explaining the effect of using the material.

96 is a schematic plan view showing a configuration of a semiconductor wafer of Example 11 of the present invention;

97 is an enlarged plan view of the semiconductor wafer.

FIG. 98 is an enlarged plan view of the semiconductor wafer shown in FIG. 97;

99 is a view for explaining the effect when the associative alignment method is applied.

100 is a sectional view of principal parts of a DRAM 1 according to Embodiment 12 of the present invention.

101 is a sectional view of principal parts in a given manufacturing process of the DRAM;

Fig. 102 is a sectional view of principal parts of a DRAM in Embodiment 13 of the present invention.

FIG. 103 is a diagram showing a relationship between target voltage and stress during sputtering of a film used in the DRAM. FIG.

104 is a sectional view of principal parts of a DRAM 1 of Embodiment 14 of the present invention.

105 and 106 are cross-sectional views of principal portions showing the DRAM in each manufacturing process.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a semiconductor integrated circuit device having a dynamic random access memory (DRAM) and a technology effective for its formation technology.

A memory cell holding 1 bit of DRAM is composed of a series circuit of a memory cell selection MISFET and an information storage capacitor. The memory cell selection MISFET of the memory cell is configured on the main surface of the active region of the semiconductor substrate (or well region). The active region of the semiconductor substrate is provided in a region defined by the isolation insulating film (field insulating film) and the channel stopper region formed between the elements formed in the inactive region of the semiconductor substrate. The gate electrode of the memory cell selection MISFET is connected to a word line extending in the row direction. One semiconductor region of the memory cell selection MISFET is connected to the complementary data line. The other semiconductor region is connected to one electrode of the information storage capacitor. A predetermined potential is applied to the other electrode of the information storage capacitor.

This type of DRAM tends to be integrated for larger capacities, thereby reducing the size of memory cells. When the size of the memory cell is reduced, the size of the information storage capacitor is also reduced, so that the amount of charge accumulated as information decreases. The decrease in the charge accumulation amount lowers the? Line soft error withstand voltage. Therefore, in particular, a DRAM having a large capacity of 1 Mbit or more is one of the important technical problems in improving the α-line soft error withstand voltage.

According to this technical problem, there is a tendency that a stacked structure (STC structure) is adopted for the information storage capacitor of a DRAM memory cell. The information storage capacitor of the stacked structure is configured by sequentially stacking each of the lower electrode layer, the dielectric film, and the upper electrode layer. The lower electrode layer is partially connected to the other semiconductor region of the memory cell selection MISFET, and the other region extends to the gate electrode. The upper electrode layer is formed by interposing a dielectric film on the surface of the lower electrode layer. This upper electrode layer is integrally formed with the upper electrode layer of the information storage capacitor of the stacked structure of other adjacent memory cells and used as a common plate electrode.

A DRAM constituting a memory cell with an information storage capacitor having a stacked structure is described, for example, in US Patent Application No. 07 / 246,514 (filed September 19, 1988).

An object of the present invention is to provide a technique capable of improving moisture resistance in a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Brief descriptions of representative ones of the inventions disclosed herein are as follows.

According to the present invention, a plurality of aluminum wirings having a predetermined film thickness are regularly arranged on a semiconductor substrate and formed on the aluminum wirings by using a CVD method using tetraethoxy silane as a source gas. A semiconductor integrated circuit device having an insulating film and a second insulating film formed on the first insulating film by a plasma CVD method, wherein the first insulating film has a film thickness of 1/2 or more of the interval between the aluminum wirings.

According to the above-described means, the silicon oxide film under the passivation film can be deposited at a low step temperature and high step coverage without melting the wiring, and the stepped shape formed by the wiring layer can be flattened, so that the upper layer of the passivation film A silicon nitride film having excellent moisture resistance can be formed without generating a cavity in accordance with the step shape. As a result, no cavity is generated in the silicon nitride film on the upper layer of the passivation film, so that the crack of the silicon nitride film is not generated or moisture is not stored in the cavity, so that the moisture resistance of the passivation film can be improved.

Hereinafter, the configuration of the present invention will be described together with the first embodiment in which the present invention is applied to a DRAM constituting a memory cell by a series circuit of a memory cell selection MISFET and a stacked information storage capacitor.

In addition, in all the drawings for demonstrating an embodiment, the thing which has the same function attaches | subjects the same code | symbol, and the repeated description is abbreviate | omitted.

Example 1

2 is a partial cross-sectional perspective view showing a resin-encapsulated semiconductor device which seals and blocks a DRAM according to Embodiment 1 of the present invention.

As shown in FIG. 2, the DRAM (semiconductor pellet) 1 is sealed with a small out-line J-bend (SOJ) type resin encapsulated semiconductor device 2. The DRAM 1 has a large capacity of 16 Mbit x 1 bit, and has a flat rectangular shape of 16.48 mm x 8.54 mm. This DRAM 1 is sealed with a 400 mil resin encapsulated semiconductor device 2.

A memory cell array and peripheral circuits are mainly disposed on the main surface of the DRAM 1. The memory cell array will be described in detail later, but a plurality of memory cells (memory elements) for storing 1-bit information are arranged in a row. The peripheral circuit is composed of a direct peripheral circuit and an indirect peripheral circuit. The direct peripheral circuit is a circuit for directly controlling the write operation of the information of the memory cell and the read operation of the information. The direct peripheral circuit includes a low address decoder circuit, a column address decoder circuit, a sense amplifier circuit, and the like. The indirect peripheral circuit is a circuit for indirectly controlling the operation of the direct peripheral circuit. The indirect peripheral circuit includes a clock signal generation circuit, a buffer circuit, and the like.

The inner lead 3A is disposed on the main surface of the DRAM 1, that is, on the surface on which the memory cell array and the peripheral circuit are arranged. An insulating film 4 is interposed between the DRAM 1 and the internal lead 3A. The insulating film 4 is formed of a polyimide resin film, for example. An adhesive layer (not shown) is provided on each surface of the insulating film 4 on the DRAM 1 side and the inner lead 3A side. As the adhesive layer, for example, polyether amide imide resin or epoxy resin is used. This type of resin encapsulated semiconductor device 2 employs a lead on chip (LOC) structure in which an internal lead 3A is disposed on the DRAM 1. Since the resin-encapsulated semiconductor device 2 employing the LOC structure can freely arrange the inner lead 3A without being restricted by the shape of the DRAM 1, the DRAM 1 having a size as large as that corresponding to this arrangement is provided. It can be sealed off. That is, the resin-encapsulated semiconductor device 2 employing the LOC structure can increase the mounting density since the sealing and blocking size is suppressed small even when the size of the DRAM 1 increases due to the increase in the capacity.

The inner lead 3A has one end integrated with the outer lead 3B. The external leads 3B are defined and numbered with signals applied to each of them according to standard specifications. In Figure 2, the left end is terminal 1 and the right end is terminal 14. The right end back (terminal number is indicated by internal lead 3A) is terminal 15 and the left end is terminal 28. In other words, the resin-encapsulated semiconductor device 2 is composed of a total of 24 terminals of terminals 1-6, terminals 9-14, terminals 15-20, and terminals 23-28.

Terminal 1 is a power supply voltage Vcc terminal. The power supply voltage Vcc is, for example, an operating voltage of 5 V of the circuit. Terminal 2 is data input signal terminal (D), Terminal 3 is empty terminal, Terminal 4 is write enable signal terminal (W), terminal 5 is low address strobe signal terminal ( ), Terminal 6 is the address signal terminal (A ₁₁ ).

Terminal 9 is the address signal terminal (A ₁₀ ), Terminal 10 is the address signal terminal (A ₀ ), Terminal 11 is the address signal terminal (A ₁ ), Terminal 12 is the address signal terminal (A ₂ ), Terminal 13 The terminal is an address signal terminal A ₃ . Terminal 14 is the power supply voltage Vcc terminal.

Terminal 15 is the reference voltage Vss terminal. The reference voltage Vss is, for example, a reference voltage of 0 V of the circuit. Terminal 16 is address signal terminal (A ₄ ), Terminal 17 is address signal terminal (A ₅ ), terminal 18 is address signal terminal (A ₆ ), terminal 19 is address signal terminal (A ₇ ) and terminal 20 The terminal is an address signal terminal A ₈ .

Terminal 23 is the address signal terminal (A ₉ ), Terminal 24 is the empty terminal, Terminal 25 is the column address strobe signal terminal (CE), Terminal 26 is the empty terminal, Terminal 27 is the data output signal terminal, The terminal is the reference voltage Vss terminal.

The other end of the inner lead 3A extends to the center side of the DRAM 1 across each of the long sides of the rectangular shape of the DRAM 1. The tip of the other end of the inner lead 3A is connected to an external terminal (bonding pad) 8P arranged at the center of the DRAM 1 via the bonding wire 5. The bonding wire 5 uses aluminum (Al) wire. Moreover, as the bonding wire 5, you may use gold (Au) wire, copper (Cu) wire, the coating wire which coat | covered insulating resin on the surface of a metal wire, etc. The bonding wire 5 is bonded by the bonding method which combined ultrasonic vibration with thermocompression bonding.

Each of the inner leads Vcc 3A of terminals 1 and 14 of the inner lead 3A is integrally formed, and a central portion of the DRAM 1 extends in parallel with its long side. Similarly, the inner leads Vss 3A of the 15th terminal and the 28th terminal are integrally formed, and the central portion of the DRAM 1 extends in parallel with the long side thereof. Each of the inner lead Vcc 3A and the inner lead Vss 3A extends in parallel in the region defined by the tip of the other end of the other inner lead 3A. Each of the internal leads Vcc 3A and the internal leads Vss 3A is configured to supply the power supply voltage Vcc and the reference voltage Vss to any position on the main surface of the DRAM 1. In other words, the resin-encapsulated semiconductor device 2 is configured to absorb power supply noise so that the operation speed of the DRAM 1 can be increased.

A pellet supporting lead 3C is provided on the rectangular short side of the DRAM 1.

Each of the inner lead 3A, outer lead 3B, and pellet support lid 3C is cut in the lead frame and is molded. The lead frame is made of, for example, a Fe-Ni (for example, Ni content of 42 or 50%) alloy, Cu, or the like.

The DRAM 1, the bonding wire 5, the inner lead 3A, and the pellet supporting lead 3C are sealed with a resin encapsulation portion 6. As shown in FIG. The resin encapsulation portion 6 uses an epoxy resin to which a phenol-based curing agent, silicone rubber, and filler are added in order to reduce stress. Silicone rubber functions to lower the thermal expansion rate of the epoxy resin. The filler is formed of spherical silicon oxide particles and similarly serves to lower the coefficient of thermal expansion.

Next, a schematic configuration of the DRAM 1 sealed with the resin-encapsulated semiconductor device 2 will be described with reference to FIG. 3 (chip layout diagram).

As shown in FIG. 3, a memory cell array (MA) 11 is disposed almost all over the surface of the DRAM 1. The DRAM 1 of this embodiment is not limited to this, but the memory cell array 11 is largely divided into four memory cell arrays 11A to 11D. In FIG. 3, two memory cell arrays 11A and 11B are disposed above the DRAM 1, and two memory cell arrays 11C and 11D are disposed below. Each of these four divided memory cell arrays 11A to 11D is further divided into sixteen memory cell arrays (MA) 11E. That is, the DRAM 1 arranges 64 memory cell arrays 11E. One memory cell array 11E divided into 64 is configured with a capacity of 256 Kbit.

A sense amplifier circuit (SA) 13 is disposed between two memory cell arrays 11E of the 64 subdivided DRAMs 1. The sense amplifier circuit 13 is composed of a complementary MISFET (CMOS). A column address decoder circuit (YDEC) 12 is disposed at one end of each of the four divided parts of the DRAM 1 below each of the memory cell arrays 11A and 11B. Similarly, a column address decoder circuit (YDEC) 12 is disposed at one end above each of the memory cell arrays 11C and 11D.

The word driver circuit (WD) 14, the low address decoder circuit (XEDC) 15, at one end of each of the four divided portions of the DRAM 1, respectively, on the right side of the memory cell arrays 111 and 11C. Each of the unit mat control circuits 16 is arranged in order from left to right. Similarly, at one end of each left side of each of the memory cell arrays 11B and 11D, the word driver circuit 14, the low address decoder circuit 15, and the unit mat control circuit 16 are sequentially arranged from right to left. It is.

Each of the sense amplifier circuit 13, the column address decoder circuit 12, the word driver circuit 14, and the low address decoder circuit 15 constitutes a direct peripheral circuit among the peripheral circuits of the DRAM 1. This direct peripheral circuit is a circuit for directly controlling the memory cells arranged in the subdivided memory cell array 11E of the memory cell array 11.

Peripheral circuit 17 and an external device between the memory cell arrays 11A and 11B and each of the memory cell arrays 11C and 11D among the four divided ones of the DRAM 1, respectively. The terminal BP is arranged. As the peripheral circuit 17, a main amplifier circuit 1701, an output buffer circuit 1702, a substrate potential generation circuit (VBB generation circuit) 1703, and a power supply circuit 1704 are disposed, respectively. A total of 16 main amplifier circuits 1701 are arranged in four units. A total of four output buffer circuits 1702 are disposed.

The external terminal BP constitutes the resin-encapsulated semiconductor device 2 in a LOC structure and extends the inner lead 3A to the center portion of the DRAM 1, and thus is disposed at the center portion of the DRAM 1. The external terminal BP is disposed from the end of the war to the bottom of the DRAM 1 in the areas defined by the memory cell arrays 11A, 11C, 11B, and 11D, respectively. Since the signal applied to the external terminal BP has been described in the resin-encapsulated semiconductor device 2 shown in FIG. 2, the description is omitted here. Basically, since the internal lead 3A to which the reference voltage Vss and the power supply voltage Vcc are applied extends from the upper end to the lower end on the surface of the DRAM 1, the DRAM 1 is extended. A plurality of external terminals BP for the reference voltage Vss and the power supply voltage Vcc are disposed along the direction. In other words, the DRAM 1 is configured to sufficiently supply the respective powers of the reference voltage Vss and the power supply voltage Vcc. Each of the data input signal D, the data output signal Q, the address signals A _{0 to} A ₁₁ , the clock signal and the control signal are concentrated in the central portion of the DRAM 1.

Peripheral circuits 18 are disposed between each of the memory cell arrays 11A and 11C and among each of 11B and 11D among the four divided DRAMs 1.

On the left side of the peripheral circuit 18, a low address strobe (RE) circuit 1801, a write enable (W) circuit 1802, a data input buffer circuit 1803, a VCC limiter circuit 1804, and an X address Each of the driver circuit (logic stage) 1805, the X-based redundant circuit 1806, and the X address buffer circuit 1807 is disposed. On the right side of the peripheral circuit 18, the column address straw (CE) circuit 1808, the test circuit 1809, the VDL limiter circuit 1810, the Y address driver circuit (logic stage) 1811, the Y system redundant Each of the circuit 1812 and the Y address buffer circuit 1813 is disposed. In the center of the peripheral circuit 18, a Y address driver circuit (drive end) 1814, an X address driver circuit (drive end) 1815, and a mat selection signal circuit (drive end) 1816 are disposed, respectively.

The peripheral circuits 17, 18, and 16 are also used as indirect peripheral circuits of the DRAM 1.

Next, the main part of the memory cell array 11E subdivided into 16 pieces of the DRAM 1 and the main part of the peripheral circuit thereof will be described with reference to FIG. 4 (main part equivalent circuit diagram).

As shown in FIG. 4, the DRAM 1 is constructed of a folded bit line system (or a two-point intersection system).

In each of the memory cell arrays 11E subdivided into sixteen DRAMs 1, a plurality of memory cells M are arranged in a matrix form. The memory cell M is arranged at the intersection of the complementary data line (complementary bit line) DL, DL and word line WL.

The complementary data lines DL extend in the row direction in FIG. 4 and are arranged in the column direction. The word lines WL extend in the column direction and are arranged in the row direction. Each of the shared sense type sense amplifier circuit Sa, the precharge circuit DP, and the input / output signal selection circuit VO is connected to the complementary data line DL extending in the row direction. The word line WL is connected to the low address decoder circuit (XDEC) 15 via the word driver circuit (WD) 14 shown in FIG. Although not shown in FIG. 4, a shunt word line WL extending in the column direction is disposed at the position along the word line WL. The shunt word line WL is configured to short-circuit with the word line WL at a predetermined portion (for example, every predetermined number of memory cells) to reduce the specific resistance of the word line WL.

The memory cell M consists of a series circuit of memory cell selection MISFETQs and information storage capacitor C. MISFETQs for selecting memory cells are composed of n channels. One semiconductor region of the memory cell selection MISFETQs is connected to the complementary data line DL. The other semiconductor region is connected to one electrode (lower electrode layer) of the information storage capacitor C. The gate electrode is connected to the word line WL. The other electrode of the information storage capacitor C is connected to the low power supply voltage 1 / 2Vcc. The DRAM 1 uses the above-described power supply voltage Vcc, i.e., 5V, for the operating voltages of the input terminal circuit and the output terminal circuit used as interfaces with the external device. The power supply voltage Vcc is applied to the respective operating voltages of the internal circuits of the DRAM 1, that is, the memory cell array 11, the direct peripheral circuits (12) to (15), and the indirect peripheral circuits (16) to (18). A lower low power supply voltage Vcc, for example 3.3V, is used. The low power supply voltage Vcc can reduce the charge / discharge amount of the complementarity data line DL, especially during the write operation and read operation of the information of the DRAM 1, so that the power consumption of the DRAM 1 can be reduced. Therefore, the low power supply voltage 1 / 2Vcc is about 1.65V potential between the low power supply voltage Vcc and the reference voltage Vss.

The precharge circuit DP is composed of two precharge MISFETs each having a gate electrode connected to the precharge signal line Фpc, and one short circuit MISFET having a gate electrode connected to the precharge signal line Фpc. The precharge MISFET connects one semiconductor region to the complementary data line DL, and the other semiconductor region to the common source line (reference voltage Vss) PN. Each semiconductor region of the short-circuit MISFET is connected to each of the complementarity data lines DL. Each of the precharge MISFET and the short circuit MISFET consists of n channels.

The sense amplifier circuit Sa is composed of two n-channel MISFETQn and two p-channel MISFETQp. One semiconductor region of each of the n-channel MISFETQn of the sense amplifier circuit Sa is connected to the complementary data line DL, and each other semiconductor region is connected to the common source line (reference voltage Vss) PN. Each gate electrode of the n-channel MISFETQn crosses each other and is connected to one data line of the complementarity data line DL to which one semiconductor region is connected and the other data line. One semiconductor region of each of the p-channel MISFETQp of the sense amplifier circuit Sa is connected to the complementary data line DL, and each other semiconductor region is connected to the common source line (Vcc: 3.3V) PP. Each gate electrode of the p-channel MISFETQp is similarly connected to each other and to the other data line of the complementary data line DL to which one semiconductor region is connected.

The input / output signal selection circuit VO is composed of an input / output selection MISFET (column switch) formed of N channels. This input / output selection MISFET is arranged for each data line of the complementarity data line DL. In the input / output selection MISFET, one semiconductor region is connected to the complementary data line DL, and the other semiconductor region is connected to any one of the complementary input / output signal lines I / O. The column selection signal line YSL is connected to the gate electrode of the input / output selection MISFET. The column select signal line YSL is connected to the column address decoder circuit 12.

The sense amplifier circuit 13 includes a complementary data line DL of the upper memory cell array 11E and a sense amplifier circuit Sa, and a complementary data line DL of the lower memory cell array 11E and an input / output signal selection circuit VO. The mat selection MISFET is provided. The mat selection MISFET is composed of n channels, and is configured to be controlled by each of the mat selection signals SHL and SHR. In the vicinity of the sense amplifier circuit 13, a dummy cell DS is arranged in the memory cell array 11E at the intersection of the complementary data line DL and the dummy word line DWL. This dummy cell DS is composed of n-channel MISFETs.

A clear MISFET opposite to the side connected to the word driver circuit 14 of the word line WL of the memory cell array 11E is disposed. This clear MISFET is controlled by the clear signal WLC.

Next, a detailed structure of the element constituting the memory cell M and the peripheral circuit (sense amplifier circuit, decoder circuit, etc.) of the DRAM 1 will be described. The planar structure of the memory cell array 11E is shown in FIG. 5 (main part plan view). The cross-sectional structure of the memory cell array 11E and the cross-sectional structure of the elements of the peripheral circuit are shown in FIG. 1 (main cross-sectional view). In addition, the cross-sectional structure of the memory cell M shown on the left side of FIG. 1 shows the cross-sectional structure of the part which cut the I-I cutting line of FIG. In addition, the right side of FIG. 1 shows the cross-sectional structure of the complementary MISFET (CMOS) which comprises a peripheral circuit.

As shown in Figs. 1 and 5, the DRAM 1 is composed of a p-type semiconductor substrate 20 made of single crystal silicon. The p-type semiconductor substrate 20 uses a (100) crystal plane as an element formation surface and is formed at a resistance value of about 10 mA / cm, for example. Introduction of n-type impurities of about 10 ¹⁵ atoms / cm ² or more by the ion implantation method is not performed on the main surface of a part of the p-type semiconductor substrate 20. A part of the area is at least an area of the memory cell array 11E. Since the introduction of the n-type impurity generates a large amount of crystal defects and leaks information charges, the region for introducing the impurity is partially limited. Therefore, in order to reduce contamination by heavy metals such as Fe, the DRAM 1 of this embodiment has a gettering layer in the deep region of the semiconductor substrate 20.

The p-type well region 22 is provided at the periphery of each formation region of the memory cell M (memory cell array 11E) and the n-channel MISFETQn of the p-type semiconductor substrate 20. The n-type well region 21 is provided in the main surface portion of the p-type semiconductor substrate 20 in the formation region of the p-channel MISFETQp. In other words, the DRAM 1 of this embodiment has a twin well structure. Although described later in the manufacturing method, the p-type well region 22 is formed in self-alignment with respect to the n-type well region 21.

An isolation insulating film (field insulating film) 23 is provided on the main surface (inactive region) between the semiconductor element formation regions of the well regions 21 and 22. A p-type channel stopper region 25A is provided below (inactive region) the element isolation insulating film 23 in the main surface portion of the formation region of the memory cell array 11E of the p-type well region 22. . Since the parasitic MOS using the inter-element isolation insulating film 23 as the gate insulating film is easily inverted to n-type, a channel stopper region is provided at least in the main surface portion of the p-type well region 22. The p-type channel stopper region 25A has a higher impurity concentration than each of the p-type semiconductor substrate 20 and the p-type well region 22.

The p-type semiconductor region 25B is provided in the main surface portion of the p-type well region 22 in the memory cell M formation region of the memory cell array 11E. The p-type semiconductor region 25B is substantially provided in front of the active region of the memory cell array 11E. The p-type semiconductor region 25B is formed in the same manufacturing process as the p-type channel stopper region 25A. The p-type semiconductor region 25B and the p-type channel stopper region 25A will be described in detail later, but after forming the isolation insulating film 23 between the elements, the memory cell array 11E of the p-type well region 22 is formed. Impurity is introduced into each of the main surface portions of the active region and the non-active region of the < RTI ID = 0.0 > For example, B is used as an impurity, and the impurity is introduced by a high energy ion implantation method. Impurities are introduced into the main surface portion of the non-active region of the p-type well region 22 by passing through the isolation insulating film 23 between the elements. The impurity is introduced into the main surface portion of the active region of the p-type well region 22 (the formation region of the memory cell M) at a position deep in the main surface as much as the film thickness of the isolation insulating film 23 between the elements. Doing.

The p-type channel stopper region 25A configured as described above is formed in a self-aligning manner with respect to the isolation insulating film 23 for inter-elements, and is described later after the heat treatment for forming the isolation insulating film 23 for inter-element isolation. The diffusion amount of the p-type impurity forming the p-type channel stopper region 25A to the active region side can be reduced. Reducing the diffusion amount of the p-type impurity can reduce the short channel effect of the memory cell selection MISFETQs of the memory cell M. Further, since the p-type semiconductor region 25B is formed under the memory cell M to act as a potential barrier region for minority carriers, the α-ray soft error withstand voltage can be increased. In addition, the p-type semiconductor region 25B can slightly increase the impurity concentration of the main surface of the p-type well region 22 and increase the threshold voltage of the memory cell selection MISFETQs. Even if noise occurs, it does not conduct wrongly. In addition, the p-type semiconductor region 25B can increase the pn junction capacitance formed in the semiconductor region 29 on the side of the memory cell selection MISFETQs that is connected to the electrode of the information storage capacitor C. Therefore, the information storage capacitance is increased. The charge accumulation amount of the device C can be increased.

The memory cell selection MISFETQs of the memory cell M are shown in FIGS. 1, 5, and 6 (main part plan views in a predetermined manufacturing process), and the main surface portion of the p-type well region 22. Consists of. In fact, the memory cell selection MISFETQs are constituted by the main surface portion of the p-type well region 22 which is surrounded by the p-type semiconductor region 25B and has a slightly high impurity concentration. The memory cell selection MISFETQs are formed in an area defined by the isolation film 23 for element isolation and the p-type channel stopper area 25A. The memory cell selection MISFETQs are mainly composed of a p-type well region 22, a gate insulating film 26, a gate electrode 27, a source region, and a pair of n-type semiconductor regions 29, which are drain regions.

The p-type well region 22 is used as a channel forming region. The gate insulating film 26 is formed of a silicon oxide film formed by oxidizing a main surface of the p-type well region 22. In addition, when the insulation breakdown voltage is ensured as the gate insulating film 26 is thinned, the gate insulating film 26 may be formed as a composite film in which a silicon oxide film and a silicon nitride film are sequentially stacked.

The gate electrode 27 is provided on the gate insulating film 26. The gate electrode 27 is formed of, for example, a polycrystalline silicon film deposited by CVD and is formed to a film thickness of about 200 to 300 nm. This polycrystalline silicon film introduces n-type impurities (p or As) which reduce the resistance value. The gate electrode 27 may be composed of a single layer of a transition metal (high melting point metal Mo, Ti, Ta, W) film or a transition metal silicide (high melting point metal silicide MoSi2, TiSi2, TaSi2, WSi2) film. The gate electrode 27 may also be composed of a composite film laminated on the polycrystalline silicon film with the transition metal film or the transition metal silicide film.

As shown in FIGS. 5 and 6, the gate electrode 27 is integrally formed with the word line WL 27 extending in the column direction. That is, each of the gate electrode 27 and the word line 27 is formed of the same conductive layer. The word line 27 is configured to connect the gate electrodes 27 of the memory cell selection MISFETQs of the plurality of memory cells M arranged in the column direction.

As shown in FIG. 6, the gate length dimension of the gate electrode 27 of the memory cell selection MISFETQs is longer than the width dimension of the word line 27. As shown in FIG. For example, the width of the word line 27 is 0.5 µm while the gate length of the gate electrode 27 is 0.7 µm. That is, the MISFETQs for selecting memory cells are configured to secure an effective gate length (effective channel length) dimension and to reduce short channel effects. On the other hand, the word line 27 is configured to reduce the area of the word line 27 to a minimum and to reduce the area of the memory cell M to improve the degree of integration. Although the word line 27 will be described later, the resistance value is reduced by the shunt word line (WL) 55. Therefore, even if the width dimension is reduced, the operation speeds of the write operation of information and the read operation of information are not reduced. Do not. In the present embodiment, the DRAM 1 employs a so-called 0.5 µm manufacturing process with a minimum processing dimension of 0.5 µm.

The n-type semiconductor region 29 is formed at a lower impurity concentration than the n + -type semiconductor region 32 of MISFETQn constituting the peripheral circuit. Specifically, the n-type semiconductor region 29 is composed of an ion implantation method having a low impurity concentration of less than 1 × 10 ¹⁴ atoms / cm ² . In other words, the n-type semiconductor region 29 is formed so as to reduce the occurrence of crystal defects due to the introduction of impurities and to fully recover the crystal defects by heat treatment after the introduction of the impurities. Accordingly, since the n-type semiconductor region 29 has a small amount of leakage current at the pn junction with the p-type well region 22, the electric charge that is accumulated in the information storage capacitor C can be stably maintained.

Since the n-type semiconductor region 29 is formed in a self-aligned manner with respect to the gate electrode 27, and the channel formation region is formed at a low impurity concentration, memory cell selection MISFETQs having a lightly doped drain (LDD) structure are formed. do.

The n-type semiconductor region 29 on one side of the memory cell selection MISFETQs (connection side of the complementarity data line 50) has a complementarity data line 50 within a region defined by a connection hole 40A described later. The n-type impurity introduced into the polycrystalline silicon film 50A of the lower layer is diffused, and the impurity concentration is slightly high. Since the n-type impurity introduced into the n-type semiconductor region 29 can ohmically connect each of the n-type semiconductor region 29 and the complementarity data line 50, the resistance value of the connection portion can be reduced. Further, in the n-type impurity, a mask misalignment occurs in the manufacturing process between the n-type semiconductor region 29 and the connection hole 40A, so that the connection hole 40A is separated from each other. The n-type semiconductor region is formed so that the complementary data line 50 and the p-type well region 22 do not short-circuit even when the main surface of the p-type well region 22 is exposed in the connection hole 40A. It is supposed to be.

In addition, the n-type semiconductor region 29 on the other side of the memory cell selection MISFETQs (the connection side of the information storage capacitor C) is within the region defined by the connection hole 34, and is described later. The n-type impurity introduced into the lower electrode layer 35 of C diffuses to form a slightly higher impurity concentration. Since the n-type impurity introduced into the n-type semiconductor region 29 can ohmically connect each of the n-type semiconductor region 29 and the lower electrode layer 35, the resistance value of the connection portion can be reduced. In addition, the n-type impurity can increase the impurity concentration of the n-type semiconductor region 29, thereby increasing the pn junction capacitance formed by the n-type semiconductor region 29 and the p-type well region 22. The charge accumulation amount of the capacitor C can be increased.

An insulating film 28 is provided on the upper layer of the gate electrode 27 of the memory cell selection MISFETQs, and sidewall spacers 31 are provided on each sidewall of the gate electrode 27 and the insulating film 28. The insulating film 28 is mainly configured to electrically separate the gate electrode 27 and each of the electrodes (particularly, 35) of the information storage capacitor C formed thereon. The sidewall spacer 31 is the n-type semiconductor region 29 and the information storage capacitor C which are self-aligned with respect to the gate electrode 27 of the memory cell selection MISFETQs in the memory cell M formation region. It is formed in order to connect each of the lower electrode layers 35 of. The sidewall spacers 31 are configured in order to make the CMOS an LDD structure in the peripheral circuit formation area. Each of the insulating film 28 and the sidewall spacer 31 is formed of a silicon oxide film deposited by a CVD method using inorganic silane gas and nitrogen oxide gas as a source gas, although the manufacturing method thereof will be described later. This silicon oxide film has a higher step coverage at the bottom step portion and a smaller shrinkage of the film than the silicon oxide film deposited by the CVD method using organic silane gas as a source gas. That is, since each of the insulating film 28 and the sidewall spacer 31 formed by this method can reduce the peeling between both due to the reduction of the film, the gate electrode 27 and the conductive layer other than the same. For example, a short circuit between the lower electrode layers 35 can be prevented.

As shown in FIG. 1, FIG. 5, and FIG. 7 (main part plan view in a predetermined manufacturing process) of the information storage capacitor C of the memory cell M, the lower electrode layer 35 and the dielectric film ( 36) and the upper electrode layers 37 are sequentially stacked. The capacitor C for information storage has a so-called stacked structure (stacked type: STC).

A part (center portion) of the lower electrode layer 35 of the information storage capacitor C of the stacked structure is connected to the other n-type semiconductor region 29 of the memory cell selection MISFETQs. This connection is made through each of the connection holes 34 defined by the connection holes 33A, the sidewall spacers 31 and 33B formed in the interlayer insulating film 33. The size of the open hole in the row direction of the connection hole 34 corresponds to the gate electrode 27 of the MISFETQs for memory cell selection, the isolation dimension of each of the word lines 27 adjacent thereto, and the sidewall spacers 31 and 33B. It is prescribed by each film thickness. The difference between the size of the open hole of the connection hole 33A and the size of the open hole of the connection hole 34 is at least larger than that corresponding to the mask fitting margin in the manufacturing process. The other part (peripheral part) of the lower electrode layer 35 extends to the upper part of each of the gate electrode 27 and the word line 27.

The interlayer insulating film 33 is formed of the same insulating film as each of the insulating film 28 and the side wall spacer 31 in the lower layer. In other words, it is formed of a silicon oxide film deposited by the CVD method using inorganic silane gas and nitrogen oxide gas as the source gas.

The lower electrode layer 35 is formed of, for example, a polycrystalline silicon film deposited by a CVD method, and an n-type impurity (As or p) for reducing the resistance value is introduced into the polycrystalline silicon film at a high concentration. The lower electrode layer 35 is configured to increase the area of the sidewalls of the surface layer so as to increase the charge accumulation amount of the information storage capacitor C of the stacked structure. The lower electrode layer 35 is formed to have a film thickness equal to or larger than 1/2 of the gate length direction of the open hole size of the connection hole 34 so that the surface thereof is flattened. For example, the lower electrode layer 35 is formed with a relatively thick film thickness of about 400 to 600 nm. The planar shape of the lower electrode layer 35 has a long rectangular shape in the row direction in which the complementarity data lines 50 extend, as shown in FIGS. 5 and 7.

The dielectric film 36 is basically a silicon nitride film 36A deposited on the upper layer (surface) of the lower electrode layer (polycrystalline silicon film) 35 by CVD and a silicon oxide film obtained by oxidizing the silicon nitride film 36A at a high pressure. It consists of a two-layer structure which laminated | stacked 36B. In fact, the dielectric film 36 is formed of a natural silicon oxide film (not shown because a very thin film thickness of less than 5 nm) is formed on the surface of the polycrystalline silicon film of the lower electrode layer 35, so that the natural silicon oxide film, silicon nitride film 36A, Each of the silicon oxide films 36B is composed of a three-layer structure in which layers are sequentially stacked. Since the silicon nitride film 36A of the dielectric film 36 is deposited by CVD, the process conditions independent of the bottom are not affected by the crystal state or step shape of the polycrystalline silicon film (lower electrode layer 35) at the bottom. Can be formed. That is, since the silicon nitride film 36A oxidizes the surface of the polycrystalline silicon film and has a higher dielectric breakdown voltage and fewer defects per unit area than the silicon oxide film, leakage current is very small. The silicon nitride film 36A is characterized by a higher dielectric constant than the silicon oxide film. Since the silicon oxide film 26B can be formed of a very high quality film, the above characteristics of the silicon nitride film 36A can be further improved. In particular, the silicon nitride film 36A is formed by high pressure oxidation (1.5 to 10 torr), which will be described later in detail, and therefore, it can be formed with a shorter oxidation time, that is, a heat treatment time than the normal pressure oxidation.

The dielectric film 36 is provided along the upper surface and the sidewall of the lower electrode layer 35 and secures an area in the height direction by using the sidewall portion of the lower electrode layer 35. Increasing the area of the dielectric film 36 can improve the charge accumulation amount of the information storage capacitor C of the stacked structure. The planar shape of the dielectric film 36 is defined by the planar shape of the upper electrode layer 37, and is substantially formed in the same shape as the upper electrode layer 37.

The upper electrode layer 37 is provided thereon to cover the lower electrode layer 35 with the dielectric film 36 interposed therebetween. The upper electrode layer 37 is integrally formed with the upper electrode layer 37 of the information storage capacitor C of the stacked structure of other memory cells M adjacent thereto. The low power supply voltage 1 / 2Vcc is applied to the upper electrode layer 37. The upper electrode layer 37 is formed of, for example, a polycrystalline silicon film deposited by the CVD method, and an n-type impurity for reducing the resistance value is introduced into the polycrystalline silicon film. The upper electrode layer 37 is formed to be thinner than the lower electrode layer 35, for example. An insulating film 38 is provided on the surface of the upper electrode layer 37. Although the insulating film 38 is mentioned later, when the upper electrode layer 37 is processed, it is formed when the etching residue which remains in the step part of a bottom surface is removed.

The dielectric film 36 of the information storage capacitor C of the stacked structure is formed on the interlayer insulating film 33 in a region other than the lower electrode layer 35. As described above, the interlayer insulating film 33 is formed of a silicon oxide film deposited by the CVD method using inorganic silane gas and nitrogen oxide gas as the source gas. That is, since the silicon nitride film 36A in the lower layer of the dielectric film 36 is in contact with the interlayer insulating film 33 with less shrinkage of the film, the information storage capacitor C of the laminated structure is formed by the dielectric film 36. It is configured to prevent the destruction caused by stress.

The memory cell M is connected to another memory cell M adjacent to each other in the row direction as shown in FIGS. 1, 5, 6, and 7. That is, the two memory cells M adjacent in the row direction integrally constitute one n-type semiconductor region 29 of each of the memory cell selection MISFETQs, and are composed of an inversion pattern around the portion. The two memory cells M are arranged in plural in the column direction, and the two memory cells M and the other two memory cells M adjacent in the column direction are arranged by 1/2 pitch shift in the row direction.

Complementary data lines DL 50 are connected to one n-type semiconductor region 29 of memory cell selection MISFETQs of memory cell M, as shown in FIG. 1 and FIG. The complementarity data line 50 is connected to the n-type semiconductor region 29 through the connection holes 40A formed in each of the interlayer insulating films 33 and 40.

The interlayer insulating film 33 is formed of, for example, a silicon oxide film deposited by a CVD method using inorganic silane gas and nitrogen oxide gas as a source gas. The information storage capacitor C of the laminated structure overlaps each of the lower electrode layer 35, the dielectric film 36, and the upper electrode layer 37 in sequence, and forms a thick film thickness of the lower electrode layer 35. The shape becomes large. Thus, the interlayer insulating film 40 is planarized on its surface. That is, since the stepped shape of the surface grows as large as the interlayer insulating film 40 corresponds to the film thickness of the lower electrode layer 35, the interlayer insulating film 40 is interposed between the lower electrode layer 35 and another adjacent lower electrode layer 35. By embedding in 40, the surface of the interlayer insulating film 40 becomes flat. The region of the smallest interval among the lower electrode layers 35 of the information storage capacitor C of the stacked structure of the adjacent memory cells M forms a large stepped shape having an aspect ratio of one or more. In this embodiment, the minimum spacing between the lower electrode layers 35 is about 0.5 μm. A dielectric film 36 and an upper electrode layer 37 are interposed between the lower electrode layers 35. Therefore, the interlayer insulating film 40 is formed with a film thickness of 1/2 or more of the confinement interval between the dielectric film 36 and the lower electrode layer 35 with the upper electrode layer 37 interposed therebetween. In addition, the interlayer insulating film 40 is formed with a film thickness that ensures an insulation breakdown voltage and can reduce parasitic capacitance. The interlayer insulating film 40 is formed with a film thickness of, for example, about 250 to 350 nm.

The complementary data line 50 is composed of a composite film having a two-layer structure in which each of the polycrystalline silicon film 50A and the transition metal silicide film 50B is sequentially stacked. The lower polycrystalline silicon film 50A is deposited by CVD and is formed with a film thickness of about 100 to 150 nm, for example. Into this polycrystalline silicon film 50A, n-type impurities, for example, p, which reduces the resistance value, are introduced. Since the step polysilicon film 50A of the lower layer has good step coverage at the bottom step portion, disconnection failure of the complementarity data line 50 can be reduced. The upper transition metal silicide film 50B is deposited by the CVD method (or sputtering method), and is formed with a film thickness of about 100 to 200 nm, for example. The upper transition metal silicide film 50B can reduce the resistance value of the complementarity data line 50, and speed up the operation speeds of the write operation of information and the read operation of information. In addition, since the step transition of the upper transition metal silicide film 50B is good at the bottom step portion, disconnection failure of the complementarity data line 50 can be reduced. Each of the polycrystalline silicon film 50A in the lower layer of the complementarity data line 50 and the transition metal silicide film 50B in the upper layer have heat resistance and oxidation resistance. The complementarity data line 50 is formed with a wiring width of, for example, about 0.6 μm.

Thus, the memory cell selection MISFETQs to which the complementary data line 50 is connected to one n-type semiconductor region 29, and the lower electrode layer 35, dielectric film 36, and upper electrode layer 37 formed on the upper layer. In the DRAM 1 constituting the memory cell M as a series circuit of the information storage capacitor C of the stacked structure in which the stacked structure is sequentially stacked, the DRAM layer 1 is formed on the upper layer of the upper electrode layer 37 of the information storage capacitor C of the stacked structure. The complementary data line 50 formed of a composite film in which each of the polycrystalline silicon film 50A and the transition metal silicide film 50B deposited by the CVD method via the interlayer insulating film 40 was sequentially laminated is constituted, and the upper layer is formed. The memory thickness of the interlayer insulating film 40 between the electrode layer 37 and the complementarity data line 50 is set to the other memory adjacent to the lower electrode layer 35 of the information storage capacitor C of the stacked structure of the memory cell M at minimum intervals. Lower layer of capacitive element C for information storage in a stacked structure of cell M It is made thicker than 1/2 of the space | interval which interposed the said upper electrode layer 37 between electrode layers 35. With this configuration, since the transition metal silicide film 50B on the upper layer of the complementarity data line 50 causes the diffusion of impurities, the interlayer insulating film 40 is flowed using a BPSG film or a PSG film to provide the complementary data. Although the planarization of the bottom surface of the line 50 cannot be promoted, the film thickness of the interlayer insulating film 40 is controlled in accordance with the dimension of the interval between adjacent lower electrode layers 35 at the minimum interval so that the lower electrode layer 35 is controlled. The gap between the layers is filled with the interlayer insulating film 40, and the surface of the interlayer insulating film 40 can be planarized. Therefore, the lower electrode layer 35 is formed during the processing of the complementary data line 50. The electrical reliability can be improved by preventing a short circuit between the complementary data lines 50 due to the etching residue remaining in the stepped portion of the interlayer insulating film 40.

A column select signal line (YSL) 52 is formed on the complementary data line 50 with an interlayer insulating film 51 interposed therebetween.

The interlayer insulating film 51 is composed of, for example, a composite film having a two-layer structure in which each of the silicon oxide film 51A deposited by the CVD method and the BPSG film 51B deposited by the CVD method is sequentially laminated. The lower silicon oxide film 51A is provided to prevent B or P added to the upper BPSG film 51B from leaking into the lower layer. The lower silicon oxide film 51A is formed of, for example, a silicon oxide film deposited by a CVD method using inorganic silane gas and nitrogen oxide gas as a source gas. The lower silicon oxide film 51A is formed with a film thickness of, for example, about 100 to 200 nm. The upper BPSG film 51B is flowed so as to planarize its surface. The BPSG film 51B is formed with a film thickness of, for example, about 250 to 350 nm.

The column select signal lines 52 are deposited on the surface of the bottom interlayer insulating film 51, and thus are formed of, for example, transition metal films deposited by a sputtering method. This transition metal film is formed of, for example, a W film. The column select signal lines 52 are formed with a film thickness of, for example, about 350 to 450 nm. Since the column select signal line 52 is formed at a different layer from the complementary data line 50, the column select signal line 52 is not defined by the wiring pitch of the complementary data line 50. There is no need to avoid the connection. That is, the column select signal line 52 is wider than the wiring width dimension of the complementarity data line 50 and can extend substantially in a straight line, thereby reducing the resistance value. The column select signal line 52 is formed with a wiring width dimension of, for example, about 2.0 μm.

A shunt word line (WL) 55 is formed in the upper layer of the column select signal line 52 with an interlayer insulating film 53 interposed therebetween. Although not shown, the shunt word line 55 is connected to the word line WL 27 in a predetermined region corresponding to each of tens to hundreds of memory cells M. Although not shown in FIG. The word lines 27 are divided into several pieces in the extending direction in the memory cell array 11E, and the shunt word lines 55 are connected to the plurality of divided word lines 27, respectively. The shunt word line 55 is configured to reduce the resistance of the word line 27 so as to speed up the selection speed of the memory cell M in each of the write operation of the information and the read operation of the information.

As shown in FIG. 1, the interlayer insulating film 53 is a silicon oxide film (deposited insulating film) 53A, a silicon oxide film (coated insulating film) 53B, and a silicon oxide film (deposited insulating film) 53C. ) Is composed of a three-layer structure formed of a composite film in which each of the layers is sequentially laminated. Each of the silicon oxide film 53A in the lower layer of the interlayer insulating film 53 and the silicon oxide film 53C in the upper layer is a conformal gas containing tetraethoxy silane (TEOS: Si (OC ₂ H ₅ ) ₄ ) gas as a source gas. It is deposited by plasma CVD (hereinafter C-CVD) method. Each of the lower silicon oxide film 53A and the upper silicon oxide film 53C deposited by C-CVD can be deposited at a low temperature (about 400 ° C. or less) and has high step coverage. Each of the lower silicon oxide film 53A and the upper silicon oxide film 53C is formed with a film thickness of about 250 to 350 nm, for example. The silicon oxide film 53B of the intermediate layer of the interlayer insulating film 53 is formed of a silicon oxide film coated with SOG (Spin On Glass) and then baked. The silicon oxide film 53B of this intermediate layer is formed for the purpose of planarizing the surface of the interlayer insulating film 53. The silicon oxide film 53B of the intermediate layer is formed so as to be coated, then baked, and then etched on the entire surface to fill only the recessed portions of the stepped portions. In particular, although the silicon oxide film 53B of the intermediate layer is described later, it is removed by etching so as not to remain on the surface of the inner wall of the connection hole 53D formed in the interlayer insulating film 53. That is, the silicon oxide film 53B of the intermediate layer is configured to reduce the corrosion of the aluminum film or the alloy film of the shunt word line 55 by the moisture contained therein. The silicon oxide film 53B of the intermediate layer is coated with a film thickness of, for example, about 100 nm.

The shunt word line 55 is composed of a composite film formed by sequentially stacking 55A of transition metal nitride films (or transition metal silicide films) and aluminum alloy films (or aluminum films) 55B.

The lower transition metal nitride film 55A is formed of, for example, a TiN film having barrier properties when Cu is added to the upper aluminum alloy film 55B. The lower transition metal nitride film 55A is formed of, for example, a TiN film when Si is added to the upper aluminum alloy film 55B. In this case, it is formed of a transition metal silicide film, for example, MoSi2. The lower transition metal nitride film 55A is deposited by, for example, a sputtering method, and formed to a thickness of about 100 nm. When the TiN film is used as the lower transition metal nitride film 55A, a TiN film having a crystal orientation of (200) is used, although described in detail below.

In the upper aluminum alloy film 55B, Cu and Si are added to aluminum. Cu is added in order to reduce a migration phenomenon, for example, about 0.5 weight% is added. Si is added in order to reduce an alloy pike phenomenon, for example, about 1.5 weight% is added. The aluminum alloy film 55B is, for example, deposited by a sputtering method, and formed to a film thickness of about 600 to 800 nm.

The said shunt word line 55 is comprised by the wiring width dimension of about 0.7 micrometer, for example.

As described above, the memory cell array 11E of the DRAM 1 of the present embodiment is composed of a six-layer multilayer wiring structure in which a two-layer wiring structure is provided on a four-layer gate wiring structure. The four-layer gate wiring structure includes a gate electrode 27 (or word line 27) of MISFETQs for memory cell selection, a lower electrode layer 35, an upper electrode layer 37, and complementarity of a capacitor C for stacking information. It consists of a data line 50. The wiring structure of the two layers is composed of a column select signal line 52 and a shunt word line 55.

The CMOS constituting the peripheral circuit of the DRAM 1 is configured as shown in the right side of FIG. The n-channel MOSFET Qn of the CMOS is formed in the main surface portion of the p-type well region 22 in a region surrounded by the insulating film 23 for inter-element isolation and the p-type channel stopper region 24. The n-channel MOSFET Qn mainly includes a pair of n-type semiconductor regions 29 and a pair of n + -type semiconductor regions, which are mainly a p-type well region 22, a gate insulating film 26, a gate electrode 27, a source region and a drain region. It consists of 32.

The p-type channel stopper region 24 surrounding the n-channel MISFETQn is formed by a manufacturing process different from that of the p-type channel stopper region 25A surrounding the memory cell selection MISFETQs of the memory cell M. The p-type channel stopper region 24 introduces p-type impurities using the same mask as the mask for forming the inter-device isolation insulating film 23, and forms the p-type impurity insulating film 23 for inter-device isolation. It is formed by activating by heat treatment. Since the p-type channel stopper region 24 is formed by the same manufacturing process as the isolation insulating film 23 for inter-elements, the diffusion amount of the p-type impurity to the active region is slightly larger, but the n-channel MISFETQn is smaller than that of the memory cell selection MISFETQs. Since it is formed in a large size, the diffusion amount of the p-type impurity is relatively small. Therefore, the n-channel MISFETQn is less affected by the short channel effect. On the contrary, since the p-type impurities forming the p-type channel stopper region 24 are introduced only into the main surface portion of the inactive region of the p-type well region 22, the impurity concentration of the main surface of the active region of the p-type well region 22 is reduced. Can be lowered. That is, since the n-channel MISFETQn can lower the threshold voltage, the driving effect can be improved by reducing the substrate effect. In particular, when the n-channel MISFETQn is used as the output stage circuit, the output signal level can be sufficiently secured.

Each of the p-type well region 22, the gate insulating layer 26, the gate electrode 27, and the n-type semiconductor region 29 has the same manufacturing process and substantially the same function as the MISFETQs for memory cell selection. Have In other words, the n-channel MISFETQn has an LDD structure.

The n + type semiconductor region 32 having a high impurity concentration is configured to reduce specific resistance values of the source region and the drain region. The n + type semiconductor region 32 is defined and formed by sidewall spacers 31 which are self-aligned on the sidewalls of the gate electrode 26 and is self-aligned with respect to the gate electrode 27. The sidewall spacer 31 is configured to define the length in the gate length direction of the n-type semiconductor region 29 forming the LDD structure. Since the sidewall spacer 31 is formed in a single layer in the formation region of the n-channel MISFETQn, the dimension in the gate length direction of the n-type semiconductor region 29 can be shortened. The n-type semiconductor region 29 has a high resistance value because the impurity concentration is low. However, since the length of the n-type semiconductor region 29 is short, the n-channel MISFETQn can improve the transfer conductance.

The n-channel MISFETQn, which is used as an input / output end circuit among the n-channel MISFETQn, is driven by the power supply voltage Vcc because the interface with an external device is executed at a single power supply voltage Vcc (5V). This n-channel MISFETQn has a gate length of about 8 m, for example, to reduce the electric field strength in the vicinity of the drain region. On the other hand, the n-channel MISFETQn used as an internal circuit, for example, a direct peripheral circuit or an indirect peripheral circuit, is driven at a low power supply voltage Vcc (about 3.3 V) to achieve low power consumption. In order to achieve high integration, the n-channel MISFETQn has a gate length in the range of, for example, about 0.8 to 1.4 mu m, and the electric field strength near the drain region is relaxed by the introduction of the low power supply voltage Vcc. Each of the n-channel MISFETQn of the input / output end circuit and the internal circuit is configured in substantially the same structure only by changing the size of the gate length and changing the power supply used. In other words, each of the n-channel MISFETQn of the input / output end circuit and the internal circuit can be composed of the gate insulating film 26, the gate electrode 27, the n-type semiconductor region 29, and the n + -type semiconductor region 32. In addition, each n-channel MISFETQn can make the size of the side length spacer 31 in the gate length direction substantially the same dimension.

As described above, in the DRAM 1 having n-channel MISFETQn of the LDD structure used as an input / output terminal circuit and n-channel MISFETQn of the LDD structure used as an internal circuit, the voltages used for the n-channel MISFETQs of the input / output end circuit are determined. Wherein the gate length dimension of the n-channel MISFETQn of the input / output stage circuit is set to be higher than the gate length dimension of the n-channel MISFETQn of the internal circuit. The dimensions of the gate length direction of the n-type semiconductor region 29 having a low impurity concentration forming the LDD structure of each n-channel MISFET of the internal circuit are substantially the same. With this configuration, since the n-channel MISFETQn of the input / output end circuit has increased the gate length dimension to improve the hot carrier breakdown voltage, it is possible to reduce the deterioration of the threshold voltage over time to improve the electrical characteristics and to improve the n of the internal circuit. The channel MISFETQn can achieve low power consumption by using the low power supply voltage Vcc while securing the hot carrier withstand voltage by using the low power supply voltage Vcc, and the n-channel MISFETQn of the input / output end circuit has a long gate length dimension and an internal circuit. Since the n-channel MISFETQn of the N-channel MISFETQn improves the hot carrier breakdown voltage by the use of the low power supply voltage Vcc, the length in the gate length direction of the n-type semiconductor region 29 having a low impurity concentration forming the LDD structure can be independently controlled. The gate length of the n-type semiconductor region 29 of low impurity concentration of each n-channel MISFETQn of the input / output terminal circuit and the internal circuit The length (or the length of the gate length direction of the sidewall spacer 31) may be substantially equal. That is, the DRAM 1 can reduce the power consumption and at the same time form a hot carrier withstand voltage, and can reduce the number of manufacturing steps for forming the n-channel MISFETQn, which will be described later.

The wiring 52 is connected to the n + type semiconductor region 32 of the n-channel MISFETQn through a connection hole 51C formed in the interlayer insulating film 40 and the interlayer insulating film 51. The wiring 52 is formed of the wiring layer under the two-layer wiring structure which is the same conductive layer as the column selection signal line 52.

The p-channel MISFETQp of the CMOS is configured in the main surface portion of the n-type well region 21 in the region surrounded by the insulating film 23 for inter-element isolation. The p-channel MISFETQp mainly includes a pair of p-type semiconductor regions 30 and a pair of p + -type semiconductor regions, which are mainly n-type well regions 21, gate insulating layers 26, gate electrodes 27, source regions and drain regions. It consists of 39.

Each of the n-type well region 21, the gate insulating film 26, and the gate electrode 27 has substantially the same functions as those of the memory cell selection MISFETQs and the n-channel MISFETQn.

The low impurity concentration p-type semiconductor region 30 constitutes a p-channel MISFETQp of LDD structure. The high impurity concentration P + type semiconductor region 39 is formed self-aligning with respect to the sidewall spacers 31 and 33C formed self-aligning with respect to the sidewall of the gate electrode 27. That is, the P + type semiconductor region 39 having a high impurity concentration of the p-channel MISFETQp is formed of a two-layer structure in which the sidewall spacers 33C are laminated on the sidewalls of the sidewall spacers 31. The sidewall spacers 31 and 33C are configured to have a length in the gate length direction as long as the sidewall spacers 33C corresponding to the sidewall spacers 31 of the n-channel MISFETQn. In other words, the sidewall spacers 31 and 33C can extend the dimension in the gate length direction to reduce the diffusion amount of the p-type impurity in the P + -type semiconductor region 39 toward the channel formation region, and thus the effective channel length. It is configured to reduce the short channel effect of p channel MISFETQp. Since the p-type impurity has a larger diffusion coefficient than the n-type impurity, the p-channel MISFETQp has the structure described above.

Thus, in the DRAM 1 having n-channel MISFETQn of LDD structure and p-channel MISFETQp of LDD structure, the sidewall spacers are formed on the sidewalls of the gate electrode 27 of the p-channel MISFETQp with respect thereto. The length in the gate length direction of 31) and 33C is longer than the dimension in the gate length direction of the sidewall spacer 31 which is self-aligned to the sidewall of the gate electrode 27 of the n-channel MISFETQn. do. This configuration shortens the dimension in the gate length direction of the sidewall spacer 31 of the n-channel MISFETQn to shorten the length in the gate length direction of the n-type semiconductor region 29 having a low impurity concentration forming an LDD structure. As a result, the conductance of the n-channel MISFETQn can be improved to increase the operating speed, and the dimensions of the sidewall spacers 31 and 33C of the p-channel MISFETQp in the direction of the gate length can be increased to make high impurities. Since the return to the channel forming region side of the P + type semiconductor region 39 can be reduced, the short channel effect of the p-channel MISFETQp can be reduced and high integration can be achieved.

The wiring 52 is connected to the P + type semiconductor region 39 of the p-channel MISFETQp through the connection hole 51C.

As shown in the right side of FIG. 1, the wiring 52 is connected to the upper wiring 55 through the transition metal film 54 embedded in the connection hole 53D formed in the interlayer insulating film 53. As shown in FIG. . The wiring 55 extending on the interlayer insulating film 53 is formed of the wiring layer on the upper layer of the two-layer wiring structure which is the same conductive layer as the shunt 55. The transition metal film 54 embedded in the connection hole 53D is formed of a W film selectively deposited on the surface of the wiring 52 exposed in the connection hole 53D by, for example, a selective CVD method. It is. The transition metal film 54 is formed to improve step coverage in the stepped shape formed by the connection hole 53D of the wiring 55.

As described above, the wiring 55 (including the shunt word line 55) is formed of a composite film in which each of the transition metal nitride film 55A and the aluminum alloy film 55B is sequentially stacked. The wiring 55 is mainly defined by the upper aluminum alloy film 55B. The transition metal nitride film (transition metal silicide film 55A) of the lower layer of the wiring 55 is a transition embedded in the wiring 55 and the connection hole 55D when Si is added to the aluminum alloy film 55B of the upper layer. It is provided in the whole area between the aluminum alloy film 55B of the upper layer containing the metal film 54 and a connection part, and the interlayer insulation film 53. As shown in FIG. That is, the wiring 55 is made uniform in the material of the bottom of the upper aluminum alloy film 55B in each of the said connection hole 53D part and the interlayer insulation film 53 part. Further, the transition metal film 55A in the lower layer of the wiring 55 has a higher migration breakdown voltage than the aluminum alloy film 55B in the upper layer. That is, even when the upper aluminum alloy film 55B is disconnected due to the migration phenomenon, the signal can be transmitted to the lower transition metal film 55A, so that the disconnection failure of the wiring 55 can be reduced.

Thus, the transition metal film 54 embedded in the connection hole 53D formed in the bottom interlayer insulating film 53 by the selective CVD method, and the aluminum alloy film 55B with Si added to the interlayer insulating film 53 are added. The interlayer insulating film 53 at the bottom and the aluminum alloy film 55B including the transition metal film 54 embedded in the connection hole 53 and the aluminum alloy film 55B in the DRAM 1 for connecting each of them. ) 55A of transition metal nitride films (or transition metal silicide films) are provided between the layers. By this structure, the bottom of the aluminum alloy film 55B is uniformized on the transition metal film 54 embedded in the connection hole 53D and on the interlayer insulating film 53, respectively, and the aluminum alloy film 55B. Since Si added to the precipitate can be reduced at the interface between the transition metal film 54 and the aluminum alloy film 55B embedded in the connection hole 53D, the resistance value of the interface can be reduced. In addition, the transition metal nitride film 55A provided under the aluminum alloy film 55B is interposed between the aluminum alloy film 55B via this disconnection even when the aluminum alloy film 55B is disconnected by, for example, a migration phenomenon. Since it can connect, the disconnection defect of the wiring 55 can be reduced.

The wiring 55 (including the shunt word line 55) is a transition embedded in at least the aluminum alloy film 55B and the connection hole 53D when Cu is added to the aluminum alloy film 55B in the upper layer. The transition metal nitride film 55A is provided at the connecting portion (interface portion) of the metal film 54. This transition metal nitride film 55A has a barrier property as described above. That is, the wiring 55 is configured to prevent the alloying reaction due to the interdiffusion of aluminum of the upper aluminum alloy film 55B and W of the transition metal film 54 embedded in the connection hole 53D.

In this way, the transition metal film 54 embedded in the connection hole 53D formed in the bottom interlayer insulating film 53 by the selective CVD method, and the aluminum alloy film 55B containing Cu added on the interlayer insulating film 53 are added. In the DRAM 1 for connecting each of the two, the transition metal nitride film 55A having a barrier property is provided between the transition metal film 54 embedded in the connection hole 53D and the aluminum alloy film 55B. This configuration prevents the alloying reaction by interdiffusion of the transition metal and aluminum at the interface between the transition metal film 54 and the aluminum alloy film 55B embedded in the connection hole 53D, thereby reducing the resistance value of the interface. Can be reduced.

As described above, the transition metal nitride film 55A under the wiring 55 actively uses a crystal having an orientation of (200). 8 shows the relationship between the target voltage KW at the time of sputtering and the specific resistance value?-?-Cm. Each of the data (A) and (B) represents a distance from the center of the semiconductor wafer of the TiN film deposited by the sputtering method on the surface of the semiconductor wafer. The data A shows the characteristic of the TiN film at the center of the semiconductor wafer, which is 0 mu m from the center of the semiconductor wafer. The data (B) shows the characteristics of the TiN film at a position of 50 µm from the center of the semiconductor wafer.

As shown in Fig. 8, the resistivity value of the TiN film is lowered as the distance from the center of the data B, i.e., the semiconductor wafer, increases. X-ray diffraction spectra were performed on the TiN film in the region C or higher, for example, about 460 µΩ-cm or higher, as shown in FIG. 8 (see FIG. 9). Is shown in the diagram). In addition, X-ray diffraction spectra were performed on the TiN film in the region D or less, for example, about 400 µΩ-cm or less. FIG. 10 shows the relationship between the incident angle of the X-ray and the X-ray diffraction intensity. The figure is shown. As shown in FIG. 9, in the region having a high specific resistance value, the TiN film is a mixture of crystal orientation of (111) and crystal orientation of (200). On the other hand, as shown in FIG. 10, the TiN film has the orientation of the single crystal of (200). That is, the TiN film having the orientation of the crystals of (200) has a specific resistance value as shown in FIG. 8 as compared to the TiN film having the orientation of the crystals of (111) alone or (111) and (200) mixed. Because of their low density, the film has a high physical property. Therefore, the TiN film which has the orientation of this (200) crystal has the characteristics which are excellent in heat resistance (barrier resistance) and can reduce the precipitation of Si.

Thus, the transition metal nitride film 55A between the transition metal nitride film 55A in the lower layer of the wire 55, in particular at least the transition metal film 54 embedded in the connection hole 53D, and the aluminum alloy film 55B in the upper layer 55A. ) Is composed of a TiN film having a crystal orientation of (200). With this configuration, the TiN film having the orientation of the crystals of (200) is more deposited than the TiN film having the orientation of the crystals of (111) or the TiN film having the orientation of mixed crystals of (111) and (200). Since the resistance value of the interface ((54)-(55B) interface) can be further reduced, and the specific resistance value is smaller than that of the TiN film having the crystal orientation other than the above, Since the resistance value can be further reduced, and the film density is high, the barrier property can be further improved.

As shown in FIG. 1 and FIG. 15 (main part sectional drawing which shows the cross-sectional structure of a position different from the cross-sectional structure shown in FIG. 1), 2-layer wiring in the area | region of the peripheral circuit of DRAM 1 Since the wiring 52 in the lower layer of the structure has a high integration, the dimension of the wiring width is reduced, and thus the migration breakdown voltage cannot be secured in the aluminum film or the aluminum alloy film. Thus, the transition metal film is used as described above. Especially as the peripheral circuit, the integrated peripheral circuit arranges each of the n-channel MISFETQn and the p-channel MISFETQp in correspondence with the arrangement pitch of the memory cells M of the memory cell array 11E, so that the layout of the wiring 52 is strictly enforced.

When the n + type semiconductor region 32 of the n channel MISFETQn and the P + type semiconductor region 39 of the p channel MISFETQp are connected to each other in the peripheral circuit region, a transition metal silicide film or a stacked film thereof (e.g., For example, when wiring is formed of the same conductive layer as that of the complementarity data line 50, interdiffusion of impurities occurs. Therefore, the wiring 52 does not use the same conductive layer as the complementary data line 50 used for the memory cell array 11E, and uses the above-described transition metal film in which the diffusion of impurities does not occur.

The DRAM 1 having each of the complementary data lines, the shunt word lines, and the column select signal lines on the memory cell array 11E and the wiring layer having two layers in the peripheral circuit area of the memory cell array 11E is thus provided. In the memory cell array 11E comprising a composite film in which each of the polycrystalline silicon film 50A and the transition metal silicide film 50B in which the complementary data lines 50 are deposited by CVD is sequentially stacked. The column select signal line 52 is composed of a transition metal film deposited on the upper layer of the complementary data line 50 by the sputtering method, and the shunt word line 55 is sputtered on the upper layer of the column select signal line 52. The aluminum alloy film 55B (including the transition metal nitride film 55A) deposited thereon is the same as the word line 55 for the shunt, and the same conductive layer 55 as the column select signal line 52 thereunder. Each of the conductive layers 52 is formed in the interlayer insulating film 53 therebetween. Connected via 53D is a transition metal film 54 embedded by a selective CVD method, and the lower wiring 52 of the two wiring layers in the region of the peripheral circuit is the same conductive layer as the column select signal line 52. The wiring 55 of the upper layer of the two wiring layers is constituted of the same conductive layer as the word line 55 for the shunt, and the wiring 52 of the lower layer of the wiring layer of the two layers and the wiring of the upper layer ( Each of 55 is connected via the transition metal film 54 embedded in the connection hole 53D by the selective CVD method. By this configuration, the following effects can be obtained.

(1) The complementary data line 50 on the memory cell array 11E has excellent heat treatment resistance and oxidation resistance, and has high step coverage of the polycrystalline silicon film 50A deposited by the lower layer CVD method, resulting in poor disconnection. Can be reduced. In addition, the complementary data line 50 deposits the upper transition metal silicide film 50B by the CVD method, so that step coverage can be further improved to reduce disconnection defects.

(2) The column select signal line 52 is formed on the upper layer of the complementarity data line 50 so that the column select signal line 52 is formed in a substantially straight line without avoiding the connection portion (connection hole 40A) of the complementarity data line 50 and the memory cell M. Since it is possible to extend the signal transmission speed, it is possible to speed up each of the write operation of information and the read operation of information, and it is formed in a layer different from the complementarity data line 50. Therefore, the lower complementarity data line 50 is formed. Increasing the degree of integration can be achieved by reducing the wiring spacing.

(3) Since the shunt word line 55 has a lower resistance value than the lower complementarity data line 50 or the column select signal line 52, the shunt word line 55 reduces the resistance value of the shunt word line 55 to provide information. The speed of each of the write operation and the read operation of information can be increased.

(4) The transition metal film 54 which connects each of the column selection signal line 52, the same conductive layer 52, the shunt word line 55 and the same conductive layer 55, has an upper shunt word line. Step coverage at the connecting portion of the same conductive layer 55 as in (55) can be reinforced to reduce the disconnection defect of the conductive layer 55, and at the same time, the conductive layer 52 at the bottom can be replaced with the same type of transition metal film ( 52, the stress between the bottom transition metal film 52 can be reduced.

(5) Since the wiring 52 in the lower layer of the peripheral circuit area, particularly the direct peripheral circuit (sense amplifier circuit or decoder circuit) of the memory cell array 11E, is a transition metal film, the migration breakdown voltage is high, and the wiring 52 The width of the wafer can be reduced (decreased in response to the arrangement pitch of the memory cells M), so that the degree of integration can be improved.

As shown in FIG. 1, a passivation film 56 is provided on the shunt word line 55 and the wiring 55 of the DRAM 1. The passivation film 56 is comprised from the composite film which laminated | stacked each of the silicon oxide film 56A and the silicon nitride film 56B one by one.

The lower silicon oxide film 56A is configured to planarize its surface, that is, the bottom surface of the upper silicon nitride film 56B. The lower silicon oxide film 56A forms the aluminum alloy film 55B of the upper layer of the shunt word line 55 and the wiring 55 of the lower layer, so that the aluminum alloy film 55B is not melted. Not deposited at low temperatures. That is, the underlying silicon oxide film 56A is deposited by, for example, the C-CVD method using tetraethoxy silane gas as the source gas. The lower silicon oxide film 56A has a good step coverage of the stepped portion of the bottom surface. Therefore, in order to planarize the surface, the aspect ratio between the shunt word line 55 or between the wiring 55 and the film thickness thereof is In one or more regions, the film is formed with a film thickness of 1/2 or more between the shunt word lines 55 or between the wirings 55. The region having an aspect ratio of 1 or more corresponds to a minimum wiring interval or a dimension close thereto, and in the region having an aspect ratio of 1 or less, step coverage of the upper silicon nitride film 56 is not a problem. Since the shunt word line 55 is formed at a wiring interval of about 0.7 μm, the lower silicon oxide film 56A is formed to have a film thickness of about 350 to 500 nm.

The silicon nitride film 56B on the upper layer of the passivation film 56 is formed to improve moisture resistance. The upper silicon nitride film 56B is deposited by, for example, plasma CVD, and is formed to a film thickness of about 1000 to 1200 nm. In the upper silicon nitride film 56B, the surface of the lower silicon oxide film 56A is flattened, so that occurrence of a cavity or the like due to growth of an overhang in the bottom step portion can be prevented.

In the DRAM 1 in which the passivation film 56 is provided on the wiring 55 mainly composed of the aluminum alloy film 55B, C, wherein the passivation film 56 is a tetraethoxy silane gas as the source gas. The silicon oxide film 56A deposited by the CVD method and the silicon nitride film 56B deposited by the plasma CVD method are sequentially formed, and the silicon oxide film 56A under the passivation film 56 is formed. ) Is made up of 1/2 or more of the film thickness of the gap between the wiring 55 and the wiring 55 in the region where the aspect ratio of the film thickness of the wiring 55 is one or more. By this structure, the silicon oxide film 56A under the passivation film 56 can be deposited at a low temperature and high step coverage in which the aluminum alloy film 55B of the wiring 55 is not melted. Since the stepped shape formed by the wiring 55 can be flattened, a silicon nitride film 56B having excellent moisture resistance of the upper layer of the passivation film 56 can be formed without generating a cavity corresponding to the stepped shape. . As a result, no cavity is generated in the silicon nitride film 56B on the upper layer of the passivation film 56, so that the crack of the silicon nitride film 56 does not occur or moisture is retained in the cavity. Moisture resistance can be improved.

The boundary region between the memory cell array MA 11E and the peripheral circuit of the DRAM 1 is constituted as shown in Figs. 11 (Schematic plan view) and 12 (Extended plan view of the main part of Fig. 11). That is, each of the p-type channel stopper region 25A formed in the inactive region of the memory cell array 11E and the p-type channel stopper region 24 formed in the inactive region of the peripheral circuit do not overlap in the boundary region. not. Since the p-type channel stopper region 25A of the memory cell array 11E and the p-type channel stopper region 24 of the peripheral circuit are formed by respective manufacturing processes, the non-overlapping non-overlapping in the boundary region is the inactive region. The impurity concentration in the region is low. This can increase the pn junction withstand voltage of each of the n-type semiconductor region 29 and the n + -type semiconductor region 32 formed in the active region and the main surface portion of the boundary region of the p-type well region 22. However, since the impurity concentration of the main surface of the non-active region of the boundary region of the p-type well region 22 is low, the threshold voltage of the parasitic MOS is lowered and an n-type inversion layer is likely to occur. The n-type inversion layer is formed with a large area surrounding the memory cell array 11E, and if there is an active region crossing or near the boundary region, the area of the active region is set to the area of the n-type inversion layer. Increase by the equivalent. This apparently increases the pn junction area and increases the amount of leakage current at the pn junction. Therefore, as shown in FIG. 12, the active region Act, for example, the n-channel MISFETQn of the peripheral circuit, is isolated in the boundary region (does not cross the boundary region). This isolation is performed at least in consideration of the mask misalignment in the manufacturing process and the diffusion amount of n-type impurities in each of the n-type semiconductor region 29 and the n + -type semiconductor region 32.

The boundary region between the memory cell array MA 11E and the peripheral circuit may be configured as shown in FIG. 13 (schematic plan view) and FIG. 14 (main part enlarged plan view of FIG. 13). That is, each of the p-type channel stopper region 25A of the memory cell array 11E and the p-type channel stopper region 24 of the peripheral circuit overlaps in the boundary region. This superposition overlaps at least as much as the mask fitting allowance dimension in a manufacturing process. When each of the p-type channel stopper regions 24 and 25A is superimposed, the impurity concentration of the boundary region of the inactive region becomes high. When the impurity concentration of the main surface portion of the inactive region of the p-type well region 22 is increased, the separation ability can be improved by increasing the threshold voltage of the parasitic MOS, but on the contrary, the n-type semiconductor region formed in the boundary region and the active region ( 29), the pn junction breakdown voltage of each of the n + type semiconductor regions 32 decreases. Therefore, as shown in FIG. 14, the active region Act, for example, the n-channel MISFETQn of the peripheral circuit, is isolated in the boundary region. This isolation includes at least the mask misalignment in the manufacturing process and the p-type impurities in the p-type channel stopper regions 24 and 25A, the n-type semiconductor region 29 and the n + -type semiconductor region 32, respectively. This measurement is carried out in consideration of the diffusion amount of the n-type impurity.

In the boundary region, a guard ring region, not shown, which prevents minority carriers generated from the substrate potential generating circuit (V _BB generating circuit) 1703 from entering the memory cell array 11E is disposed. This guard ring region is arranged around the memory cell array 11E and is composed of an n-type semiconductor region 29 or an n + -type semiconductor region 32. The guard ring region is provided in the memory cell array 11E (isolated from the boundary region) inside the respective boundary regions of the p-type channel stopper regions 25A and 24. On the upper part of the guard ring region, a step relaxation layer formed by the same conductive layer as the lower electrode layer 35, the upper electrode layer 37, or both layers of the information storage capacitor C of the stacked structure of the memory cell M is provided. have. This step mitigating layer relaxes the shape of the step generated between the memory cell array 11E and the peripheral circuit so as to improve the processing accuracy of the upper layer wiring, for example, the column select signal line 52 or the shunt word line 55, or disconnection. It is comprised so that reduction of defect may be aimed at.

The memory cell M and the periphery of the main surface in the different active region of the p-type well region 22 defined as the p-type channel stopper region formed in the main surface portion of the inactive region of the p-type well region 22 as described above. In the DRAM 1 which arranges each of the n-channel MISFETQn circuits, the p-type channel stopper region 25A surrounding the memory cell M and the p-type channel surrounding the n-channel MISFETQn of the peripheral circuit. Each manufacturing process of the stopper region 24 is configured independently, and each boundary region of the p-type channel stopper region 25A and the p-type channel stopper region 24 includes the memory cell M and the n of the peripheral circuit. No active area Act is provided, such as channel MISFETQn. With this configuration, when each of the p-type channel stopper region 25A and the p-type channel stopper region 24 is isolated from the boundary region, a large n-type inversion layer corresponding to the area is generated in the boundary region. If the active region Act is present in the boundary region, the area of the n-type semiconductor region 29 or the n + -type semiconductor region 32 formed in the active region Act is increased by adding the n-type inversion layer in appearance. The amount of leakage current increases at the junction between the p-type well region 22 and the n-type semiconductor region 29 or the n + -type semiconductor region 32, but the active region Act is not disposed in the boundary region. The leakage current amount can be reduced. In the case where each of the p-type channel stopper region 25A and the p-type channel stopper region 24 is folded in the boundary region, the impurity concentration of the region becomes high, but no active region Act is disposed in the boundary region. The pn junction breakdown voltage of the p-type well region 22 and the n-type semiconductor region 29 or the n + -type semiconductor region 32 can be improved.

Next, the specific manufacturing method of the DRAM 1 described above will be briefly described using FIGS. 16 to 49 (the main part cross sectional diagram shown for each manufacturing process).

First, a p-type semiconductor substrate 20 made of single crystal silicon is prepared.

Well Forming Process

Next, each of the silicon oxide film 60 and the silicon nitride film 61 is sequentially stacked on the main surface of the p-type semiconductor substrate 20. The silicon oxide film 60 is formed by the steam oxidation method of about 900-1000 degreeC high temperature, for example, is formed by the film thickness of about 40-50 nm. This silicon oxide film 60 is used as a buffer layer. The silicon nitride film 61 is used as an impurity introduction mask and an oxidation resistant mask, respectively. The silicon nitride film 61 is deposited, for example, by CVD to form a film thickness of about 40 to 60 nm.

Next, the silicon nitride film 61 of the n-type well region 21 formation region is removed and a mask is formed. Formation of the mask 61 is performed using photolithographic technique (photoresist mask formation technique) and etching technique.

Next, as shown in FIG. 16, n type impurity 21n is introduce | transduced into the main surface part of the p-type semiconductor substrate 20 through the silicon oxide film 60 using the said mask 61. As shown in FIG. The n-type impurity 21n is introduced by ion implantation with an energy of about 120 to 130 KeV using, for example, an impurity concentration of about 10 ¹³ atoms / cm ² .

Next, using the mask 61, as shown in FIG. 17, a silicon oxide film 60 exposed by the mask is grown, and a thick silicon oxide film 60A is formed. The silicon oxide film 60A is formed only in the n-type well region 21 forming region, and is used as a mask for removing the mask 61 and an impurity introduction mask. The silicon oxide film 60A is formed by steam oxidation at a high temperature of about 900 to 1000 ° C., for example, so as to finally have a film thickness of about 110 to 130 nm. The n-type impurity 21n introduced therein is slightly diffused by the heat treatment step of forming the silicon oxide film 60A.

Next, the mask 61 is selectively removed by, for example, thermal phosphoric acid.

Next, as shown in FIG. 18, the silicon oxide film 60A is used as an impurity introduction mask, and the p-type impurities (in the main surface of the p-type semiconductor substrate 20 passed through the silicon oxide film 60) are formed. 22p). The p-type impurity 22p is introduced by an energy ion implantation method of about 20 to 30 KeV using, for example, B (or BF2) having an impurity concentration of about 10 ¹² to 10 ⁴³ atoms / cm ² . Since the p-type impurity 22p forms a thick film thickness of the silicon oxide film 60A, it is not introduced into the formation region of the n-type well region 21.

Next, each of the n-type impurity 21n and the p-type impurity 22p is extended and diffused, so that the n-type well region 21 and the p-type well region 22 are shown in FIG. Form. The n-type well region 21 and the p-type well region 22 are formed by performing heat treatment in an atmosphere at a high temperature of about 1100 to 1300 ° C. As a result, the p-type well region 22 is formed self-aligning with respect to the n-type well region 21.

(Separation Zone Forming Process)

Next, each of the silicon oxide films 60 and 60A is removed, and the main surfaces of the n-type well region 21 and the p-type well region 22 are exposed.

Next, as shown in FIG. 20, the silicon oxide film 62, the silicon nitride film 63, and the polycrystalline silicon film are formed on the main surfaces of the n-type well region 21 and the p-type well region 22, respectively. Each of the 64 is sequentially stacked. The lower silicon oxide film 62 is used as a buffer layer. The silicon oxide film 62 is formed by, for example, steam oxidation at a high temperature of about 900 to 1000 占 폚 and a film thickness of about 15 to 25 nm. The silicon nitride film 63 of the intermediate layer is mainly used as an oxidation mask. The silicon nitride film 63 is deposited by, for example, CVD and is formed to a film thickness of about 150 to 250 nm. The upper polycrystalline silicon film 64 is mainly used as each of an etching mask of the underlying silicon nitride film 63, a mask for determining the groove depth, and a mask for controlling the length of the sidewall spacer. The polysilicon film 64 is deposited by, for example, CVD and is formed to a film thickness of about 80 to 120 nm.

Next, as shown in FIG. 21, the polysilicon film 64 of the upper layer on the main surface of each of the inactive regions of the n-type well region 21 and the p-type well region 22 is removed, and then the active region is removed. The mask is formed of the polycrystalline silicon film 64 remaining in the film. This mask 64 is formed using photolithographic and etching techniques. After the mask 64 is formed, the etching mask (photoresist film) formed by the photolithographic technique is removed.

Next, as shown in FIG. 22, the mask 64 is used as an etching mask, the silicon nitride film 63 exposed to the inactive region is removed, and a mask 63 is formed under the mask 64. . Patterning of the mask 63 prevents contaminants from the photoresist film from being trapped in the main surface of each of the n-type well region 21 and the p-type well region 22 or in the silicon oxide film 62. In order to do this, the mask 64 is used without using a photoresist film for patterning the mask 64.

Next, as shown in FIG. 23, each of the silicon nitride film 65 and the silicon oxide film 66 is sequentially laminated on the entire substrate including the mask 64. As shown in FIG. The lower silicon nitride film 65 is mainly used as an oxidation resistant mask and is formed with a thin film thickness compared with the mask 63. The silicon nitride film 65 is, for example, deposited by a CVD method and formed to a film thickness of about 15 to 25 nm. The upper silicon oxide film 66 is mainly used as an etching mask. The silicon oxide film 66 is deposited by, for example, a CVD method using inorganic silane gas (SiH ₄ or SiH ₂ Cl ₂ ) and nitrogen oxide gas (N ₂ O) as the source gas, and has a film thickness of about 150 to 250 nm. Is formed.

Next, as shown in FIG. 24, anisotropic etching is performed to correspond to the film thickness deposited on each of the silicon oxide film 66 and the silicon nitride film 65, respectively. Each of the masks 65 and 66 is formed on the side wall of the mask self-aligned with respect to it. Each of these masks 65 and 66 is formed of a so-called sidewall spacer.

Next, as shown in FIG. 25, the main surfaces of the inactive regions of the n-type well region 21 and the p-type well region 22 respectively using the masks 64 and 66 as etching masks. To form a shallow groove 67. The shallow groove 67 is formed deeper than the junction depth of the n-type semiconductor region 29 or 32, for example, to form a depth of the lower surface of the isolation film 23 for inter-element isolation formed in a later step. It is formed to increase the ability. The depth of this shallow groove 67 is controlled by the film thickness of the mask 64. That is, the mask 64 is removed at the same time as the shallow groove 67 is formed, and the reactive gas component of the mask 64 is detected, and the mask 64 is shallow at or near the point where the reactive gas component of the mask 64 disappears. Etching to form the grooves 67 is stopped. The shallow groove 67 is formed by anisotropic etching, such as RIE, for example, and is formed in the depth of about 80-120 nm.

As described above, the n-type well region 21 is formed by using a mask 64 formed of a material having an etching rate substantially equal to that of each of the n-type well region 21 and the p-type well region 22. The main surface of each non-active region of the p-type well region 22 is etched by the amount corresponding to the film thickness of the mask 64 to form the shallow groove 67. By this structure, since the depth of the shallow groove 67 can be controlled by the film thickness of the mask 64, the controllability of the depth of the shallow groove 67 can be improved.

Next, a silicon oxide film 62A is formed on the main surfaces of the inactive regions of the n-type well region 21 and the p-type well region 22 exposed by the formation of the shallow groove 67. . This silicon oxide film 62A is used as a buffer layer when introducing impurities. The silicon oxide film 62A is formed by, for example, a thermal oxidation method to form a film thickness of about 8 to 12 nm.

Next, as shown in FIG. 26, the p-type impurity 24p is formed in the main surface portion of the inactive region of the p-type well region 22 in the peripheral circuit formation region through the silicon oxide film 62A. Introduce. To introduce the p-type impurity 24p, each of the masks 63 and 66 and a photoresist mask (not shown) is used as the impurity introduction mask. The p-type impurity 22p is introduced by an ion implantation method of energy of about 50 to 70 KeV using, for example, BF ₂ having an impurity concentration of about 10 ¹³ atoms / cm ² . This p-type impurity 24p is self-aligned with respect to the active region in the formation region of the peripheral circuit.

Next, the silicon oxide film on the main surface of each of the non-active regions of the n-type well region 21 and the p-type well region 22 was used using each of the masks 63 and 65 as the oxidation resistant mask. An isolation insulating film (field insulating film) 23 between elements is formed in the portion 62A). At this time, the silicon oxide film 66 is removed with a pullulic acid-based etching solution before the formation of the insulating film 23 for element isolation. The isolation insulation 23 between the elements is subjected to a heat treatment for about 30 to 40 minutes in a nitrogen gas atmosphere containing a small amount (about 1% or less) of oxygen at a very high temperature of, for example, about 1050 to 1150 ° C. It can be formed by oxidizing for about 30 to 50 minutes by the steam oxidation method. The isolation insulating film 23 for elements is formed to have a film thickness of, for example, about 400 to 600 nm.

Since the end portion on the active region side of the isolation insulating film 23 for inter-elements is in direct contact with the substrate with a thin film thickness, the growth in the transverse direction (active region side) in the initial stage of oxidation is reduced, and The thick film thickness mask 63 can reduce the growth in the lateral direction even if oxidation proceeds, so that the buzz bequee can be reduced. On the other hand, the mask 65 having a thin film thickness is lifted onto the Buzz beak as oxidation progresses, so that the occurrence of defects can be reduced by relieving stress. That is, the isolation insulating film 23 for elements can be formed with a small buzz bee and a thick film thickness. Therefore, since the isolation insulating film 23 for inter-elements can be formed to the same size as the size of the mask 63 forming the same, the effective area of the active region can be increased while reducing the separation area between the elements.

The p-type impurity 24p introduced into the main surface portion of the p-type well region 22 is extended and diffused by the heat treatment forming the isolation insulating film 23 between the devices, thereby extending the p-type channel. The stopper region 24 is formed. The heat treatment diffuses the p-type impurity 24p also in the horizontal direction (active region side), but the n-channel MISFETQn of the peripheral circuit is larger than the size of the memory cell selection MISFETQs of the memory cell M. The amount of diffusion in the transverse direction of 24p) is relatively small. In other words, the channel MISFETQn is less affected by the short channel effect.

Next, each of the masks 63, 65 and the silicon oxide film 62 is removed to expose the main surfaces of the active regions of the n-type well region 21 and the p-type well region 22, respectively. . Thereafter, as shown in FIG. 27, a silicon oxide film 68 is formed on each of the main surfaces of the exposed n-type well region 21 and p-type well region 22. As shown in FIG. The silicon oxide film 68 is formed at the end of the inter-element isolation insulating film 23 by each of the silicon nitride films (masks) 63 and 65 which are mainly used in forming the inter-element isolation insulating film 23. To oxidize the nitride of silicon, the so-called white ribbon. The silicon oxide film 68 is formed by, for example, steam oxidation at a high temperature of about 900 to 1000 ° C., and is formed to a film thickness of about 40 to 100 nm.

Next, as shown in FIG. 28, the p-type channel stopper region 25A and the p-type semiconductor region 25B in the main surface portion of the p-type well region 22 in the formation region of the memory cell array 11E. To form each of the. The p-type channel stopper region 25A is formed in the inactive region below the isolation insulating film 23 for inter-elements. The p-type semiconductor region 25B is formed in the active region which is the formation region of the memory cell M. Each of the p-type channel stopper region 25A and the p-type semiconductor region 25B includes, for example, an ion implantation method having a high energy of about 200 to 300 KeV with B having an impurity concentration of about 10 ¹² to 10 ¹³ atoms / cm ² . It is formed by introducing. In the main surface portion of the non-active region of the p-type well region 22, the p-type impurity is introduced through the isolation film 23 for inter-element isolation. In the main surface portion of the active region, the p-type impurity is introduced into the deep position of the main surface portion of the p-type well region 22 as much as the film thickness of the insulating film 23 for inter-element isolation. Each of the p-type channel stopper region 25A and the p-type semiconductor region 25B formed by this method is formed in self-alignment with respect to the insulating film 23 for inter-element isolation.

Thus, in the DRAM 1 which forms the memory cell selection MISFETQs on the main surface in the active region surrounding the inactive region of the p-type well region 22, the active region of the p-type well region 22 is formed. Forming a first mask in which each of the masks 63 and 64 on the main surface is sequentially laminated; the mask 63 of the first mask formed on the sidewall of the first mask in a self-aligned manner; As compared with the above, the step of forming a second mask obtained by sequentially stacking the masks 65 and 66 having a thin film thickness and the p-type well region 22 using the first mask and the second mask is performed. Etching to the main surface of the non-active region of the () to form a shallow groove 67 in the non-active region of the p-type well region 22, thermal oxidation using the first mask and the second mask. Insulator isolation for the main surface of the non-active region of the p-type well region 22 (Field Insulating Film) 23. After removing the first mask and the second mask, p-type impurities on all major surfaces including the active region and the inactive region of the p-type well region 22. And forming the p-type channel stopper region 25A on the main surface of the p-type well region 22 under the inter-element isolation insulating film 23. With this configuration, since the amount of oxidation in the horizontal direction of the inter-element isolation insulating film 23 can be reduced, the size of the inter-element isolation insulating film 23 can be reduced and the film thickness can be made thicker. The shallow groove 67 is used to deepen the position of the lower surface of the interlayer isolation insulating film 23 relative to the main surface of the active region of the p-type well region 22, and to isolate the isolation dimension between the memory cell selection MISFETQs. Since it can be ensured in the depth direction of the type well region 22, the separation capability between the memory cell selection MISFETQs can be improved, and the film thickness of the isolation insulating film 23 for inter-device isolation is formed thick to form the p-type channel stopper. When the p-type impurity forming the region 25A is introduced, the p-type impurity introduced into the main surface portion of the active region of the p-type well region 22 can be introduced into the deep position of the p-type well region 22. Therefore, according to the introduction of the p-type impurity It is possible to reduce the variation in the threshold voltage.

In addition, the process of forming the insulating film 23 for isolation between elements is carried out by a high temperature oxidation method in the range of about 1050 to 1150 占 폚. In this arrangement, when forming the isolation insulating film 23 between the devices, the fluidity of the silicon oxide film according to the high temperature oxidation method is promoted so that the isolation insulating film 23, the n-type well region 21 and the p-type well between the devices are promoted. Since the stress generated between the main surfaces of each non-active area of the area 22 can be reduced, in particular, the shallow surface formed on the main surfaces of each of the non-active areas of the n-type well area 21 and the p-type well area 22 can be reduced. The occurrence of crystal defects in the corner portions of the grooves 67 can be reduced.

In addition, the shallow grooves 67 formed in the main surface of each of the inactive regions of the n-type well region 21 and the p-type well region 22 are not able to recover crystal defects or are not particularly necessary. It does not have to be formed. In this case, the mask 64 may be removed and the film thickness of the mask 65 may be set to 200 to 300 nm.

In addition, each of the memory cell selection MISFETQs forming the memory cell M and the n-channel MISFETQn forming the peripheral circuit are formed of the inter-element isolation insulating film 23 and the p-type channel stopper region of the p-type well region 22. A DRAM 1 formed on a main surface of an active region in an area surrounded by an inactive region, the active region forming memory cell selection MISFETQs of the p-type well region 22 and an inactive region surrounding the active region. In the main surface portion, the inactive region is provided with a p-type channel stopper region 25A formed by passing the interlayer isolation film 23 and introducing p-type impurities, and n of the p-type well region 22 is provided. The p-type impurity 24p is introduced into the main surface portion of the inactive region surrounding the active region forming the channel MISFETQn to provide the p-type channel stopper region 24. This configuration increases the threshold voltage of the parasitic MOS in the p-type channel stopper region 25A to secure the separation capability between the memory cell M and the memory cell selection MISFETQs forming the same and the surrounding memory cell M. The p-type channel stopper region 25A is self-aligned with respect to the isolation insulating film 23 for inter-device isolation, and the p-type impurity forming the p-type channel stopper region 25A has a diffusion amount toward the active region side. Since the short channel effect of the memory cell selection MISFETQs can be reduced, the p-type impurity 24p forming the p-type channel stopper region 24 is introduced only into the inactive region and the n-channel MISFETQn Since it is not introduced into the active region forming the structure, the influence of the substrate effect can be reduced, and the variation in the threshold voltage of the n-channel MISFETQn can be reduced. As described above, since the n-channel MISFETQn has a larger size than the memory cell selection MISFETQs of the memory cell M, the n-channel MISFETQn has a p-type impurity 24p forming the p-type channel stopper region 24p. The diffusion amount toward the active region is relatively small, and the short channel effect hardly occurs. In addition, the n-channel MISFETQn can reduce the impurity concentration on the surface of the active region without introducing the p-type impurity 24p forming the p-type channel stopper region 24 into the active region, thereby reducing and driving the threshold voltage. You can increase your skills. In particular, when the n-channel MISFETQn is used as an output stage circuit, the output signal level can be sufficiently secured.

Each of the memory cell selection MISFETQs and n-channel MISFETQn of the memory cell M is provided in the main surface portion of the p-type well region 22 having a higher impurity concentration than the p-type semiconductor substrate 20. This configuration can increase the impurity concentration of each channel forming region of the memory cell selection MISFETQs and n-channel MISFETQn of the p-type well region 22, thereby reducing the short channel effect and simultaneously reducing the p-type. Since the potential barrier region can be formed by the difference in the impurity concentration of each of the type well region 22 and the p-type semiconductor substrate 20, in particular, the? -Ray soft error breakdown voltage of the memory cell M can be improved. Further, when the n-channel MISFETQn forms a direct peripheral circuit such as the column address decoder circuit (YDEC) 12, the sense amplifier circuit (SA) 13, or the like, the? Line soft error withstand voltage can be similarly improved.

(Gate insulating film forming process)

Next, a silicon oxide film 68A is formed on the main surface of each of the active regions of the n-type well region 21 and p-type well region 22. The silicon oxide film 68A is formed again after removing the silicon oxide film 68. The silicon oxide film 68A has a film thickness of about 15 to 25 nm.

Next, as shown in FIG. 29, in the peripheral circuit formation region, an active region defined by the isolation insulating film 23 between the n-type well region 21 and the p-type well region 22, respectively. The p-type impurity 69p for controlling the threshold voltage is introduced into the main surface of the substrate. The p-type impurity 69p is introduced by ion implantation with an energy of about 20 to 30 KeV using, for example, an impurity concentration of B of about 10 ¹² atoms / cm ² . This p-type impurity 69p mainly introduces n-channel MISFETQn and Qp to adjust respective threshold voltages. In addition, the p-type impurity 69p may be introduced into the main surface portions of the n-type well region 21 and the p-type well region 22 in respective steps.

Next, the silicon oxide film 68A is selectively removed to expose the main surfaces of the p-type well region 22 and the n-type well region 21, respectively.

Next, a gate insulating film 26 is formed on each of the main surfaces of the exposed p-type well region 22 and n-type well region 21. The gate insulating film 26 is formed by steam oxidation at a high temperature of about 800 to 1000 ° C. and a film thickness of about 12 to 18 nm.

(Gate Wiring Formation Process)

Next, a polycrystalline silicon film is formed over the entire substrate including the gate insulating film 26 and the interlayer isolation insulating film 23. The polycrystalline silicon film is deposited by CVD and formed to a film thickness of about 200 to 300 nm. An n-type impurity, for example, p, which reduces the resistance value by thermal diffusion, is introduced into the polycrystalline silicon film. Thereafter, a silicon oxide film (not shown) is formed on the surface of the polycrystalline silicon film by thermal oxidation. This polycrystalline silicon film is formed by the gate wiring formation process of the 1st layer in a manufacturing process.

Next, an interlayer insulating film 28 is formed on the entire surface of the polycrystalline silicon film. The interlayer insulating film 28 is formed by a CVD method using inorganic silane gas and nitrogen oxide gas as the source gas. The interlayer insulating film 28 is formed to have a film thickness of, for example, about 250 to 350 nm.

Next, as shown in FIG. 30, each of the interlayer insulating film 28 and the polycrystalline silicon film is sequentially etched using an etching mask (not shown) to form the gate electrode 27 and the word line WL 27. do. The interlayer insulating film 28 is left over the gate electrode 27 and the word line 27, respectively. The etching is performed by anisotropic etching.

(Low concentration semiconductor region formation process)

Next, a silicon oxide film (without reference numerals) is formed on the entire surface of the substrate in order to reduce contamination due to the introduction of impurities. The silicon oxide film is formed on the main surface of each of the p-type well region 22 and n-type well region 21 exposed by the etching or on the sidewalls of the gate electrode 27 and the word line 27. The silicon oxide film is formed in an oxygen gas atmosphere at a high temperature of about 850 to 950 ° C, for example, and is formed at a film thickness of about 10 to 20 nm.

Next, using the interlayer isolation insulating film 23 and the interlayer insulating film 28 (and the gate electrode 27) as an impurity introduction mask, p- in each of the formation regions of the memory cell array 11E and the n-channel MISFETQn. An n-type impurity 29n is introduced into the main surface portion of the type well region 22. The n-type impurity 29n is introduced into the gate electrode 27 in a self-aligned manner. The n-type impurity 29n is introduced by ion implantation with an energy of about 30 to 50 KeV using, for example, p (or As) having an impurity concentration of about 10 ¹³ atoms / cm ² . Although not shown, when the n-type impurity 29n is introduced, the formation region of the p-channel MISFETQp is covered with an impurity introduction mask (for example, a photoresist film).

Next, as shown in FIG. 31, the n-type in the formation region of the p-channel MISFETQp is formed by using the interlayer isolation insulating film 23 and the interlayer insulating film 28 (and the gate electrode 27) as impurity introduction masks. The p-type impurity 30p is introduced into the main surface of the well region 21. The p-type impurity 30p is self-aligned with respect to the gate electrode 27. The p-type impurity 30p is introduced by ion implantation with an energy of about 20 to 30 KeV using, for example, B (or BF ₂ ) having an impurity concentration of about 10 ¹² atoms / cm ² . Although not shown, the formation regions of the memory cell array 11E and the n-channel MISFETQn at the time of introduction of the p-type impurity 30p are covered with an impurity introduction mask (photoresist film).

(High concentration semiconductor region formation process 1)

Next, sidewall spacers 31 are formed on the sidewalls of the gate electrode 27, the word line 27, and the interlayer insulating film 28 therebetween. The sidewall spacer 31 can be formed by depositing a silicon oxide film and performing anisotropic etching of RIE or the like as much as the film thickness on which the silicon oxide film is deposited. The silicon oxide film of the sidewall spacer 31 is formed by a CVD method using inorganic silane gas and nitrogen oxide gas having the same film quality as the interlayer insulating film 28 as a source gas. This silicon oxide film is formed to a film thickness of, for example, about 130 to 180 nm. The length of the side length spacer 31 in the gate length direction (channel length direction) is formed to about 150 nm.

Next, in the formation region of the n-channel MISFETQn in the peripheral circuit, n-type impurities 32n are introduced as shown in FIG. At the time of introduction of the n-type impurity 32n, the sidewall spacer 31 is mainly used as the impurity introduction mask. In addition, the regions other than the n-channel MISFETQn formation region, that is, each of the memory cell array 11E and the p-channel MISFETQp formation region, are impurity introduction masks (not shown) upon introduction of the n-type impurity 32n. Covered with) The n-type impurity 32n is introduced by an ion implantation method of energy of about 70 to 90 KeV using As (or p) of an impurity concentration of about 10 ¹⁵ atoms / cm ² , for example.

Next, as shown in FIG. 33, heat treatment is performed to extend and diffuse the n-type impurity 29n, n-type impurity 32n, and p-type impurity 30p, respectively, to form an n-type semiconductor region ( 29), each of the n + type semiconductor region 32 and the p type semiconductor region 30 is formed. The heat treatment is performed for about 20 to 40 minutes at a high temperature of about 900 to 1000 ° C, for example. By forming the n-type semiconductor region 29, memory cell selection MISFETQs of the LDD structure of the memory cell M are completed. The n-channel MISFETQn of the LDD structure is completed by forming the n-type semiconductor region 29 and the n + -type semiconductor region 32. This n-channel MISFETQn is used for peripheral circuits (for low voltage) and input / output end circuits (for high voltage) of the DRAM 1. The p-type semiconductor region 30 constituting the LDD structure of the p-channel MISFETQp is completed, but the p + -type semiconductor region 39 is formed after the completion of the memory cell M, so that the p-channel MISFETQp is completed in a later step.

In the DRAM 1 having each of the n-channel MISFETQn of the high voltage LDD structure used as the input / output end circuit and the n-channel MISFETQn of the low voltage LDD structure used as the peripheral circuit, the p-type well region 22 Forming a gate insulating film 26 and a gate electrode 27 of the high voltage n-channel MISFETQn and the low voltage n-channel MISFETQn on the main surfaces of the different active regions in the same manufacturing process, and the p-type well region 22. N-type semiconductor region of low impurity concentration which forms an LDD structure in a self-aligned manner with respect to the gate electrode 27 of the high voltage n-channel MISFETQn and the low voltage n-channel MISFETQn in the main surface portion of each active region 29) forming the same manufacturing process; forming sidewall spacers 31 on the sidewalls of each of the gate electrodes 27 of the high voltage n-channel MISFETQn and the low voltage n-channel MISFETQn. p-type wells An n + type semiconductor region 32 having a high impurity concentration is formed on the main surface of each of the high voltage n-channel MISFETQn and the low voltage n-channel MISFETQn in the active region of the region 22 with respect to the sidewall spacer 31. It includes a process to make. This configuration makes it possible to use both of the high voltage n-channel MISFETQn and the low voltage n-channel MISFETQn together with each of the forming steps, and in particular, the respective sidewall spacers 31 can be formed in the same manufacturing process. The number of manufacturing processes can be reduced.

(Interlayer Insulating Film Formation Step 1)

Next, an interlayer insulating film 33 is formed on the entire surface of the substrate including the above interlayer insulating film 28 and the sidewall spacer 31. This interlayer insulating film 33 is used as an etching stopper layer when processing each electrode layer of the information storage capacitor C having a laminated structure. The interlayer insulating film 33 is formed to electrically separate each of the lower electrode layer 35 of the information storage capacitor C of the stacked structure, the gate electrode 27 and the word line 27 of the MISFETQs for memory cell selection. It is. The interlayer insulating film 33 is configured to increase the thickness of the sidewall spacer 31 of the p-channel MISFETQp. The interlayer insulating film 33 is mainly formed with the film thickness which anticipated the reduction amount by the over etching at the time of processing of an upper conductive layer, the reduction amount in a washing process, etc. The interlayer insulating film 33 is formed of a silicon oxide film deposited by the CVD method using inorganic silane gas and nitrogen oxide gas as the source gas. In other words, the interlayer insulating film 33 can reduce stress caused by the linear expansion coefficient difference between the dielectric film 36 of the information storage capacitor C of the stacked structure and the interlayer insulating film 28 at the bottom. The interlayer insulating film 33 is formed to have a film thickness of, for example, about 130 to 180 nm.

Next, as shown in FIG. 34, the other n-type semiconductor region of the memory cell selection MISFETQs of the memory cell M forming region (that is, the lower electrode layer 35 of the information storage capacitor C is connected) (29) ), The interlayer insulating film 33 is removed to form the connection holes 33A and 34, respectively. The connection hole 34 is formed in a region defined by each of the sidewall spacers 33B deposited on the sidewalls of the sidewall spacers 31 when the sidewall spacers 31 and the interlayer insulating film 33 are etched. It is.

(Gate Wiring Formation Step 2)

Next, as shown in FIG. 35, a polycrystalline silicon film is formed on the entire surface of the substrate including the interlayer insulating film 33 to form the lower electrode layer 35 of the capacitor C for information storage of the stacked structure of the memory cells M. As shown in FIG. . This polycrystalline silicon film is connected to a portion of the n-type semiconductor region 29 through each of the connection holes 33A and 34. This polycrystalline silicon film is formed of a polycrystalline silicon film deposited by CVD and is formed at a film thickness of about 150 to 250 nm. This polycrystalline silicon film is formed by the gate wiring formation process of the 2nd layer in a manufacturing process. In the polysilicon film, an n-type impurity, for example, p, which reduces the resistance value after deposition, is introduced by the thermal diffusion method. The n-type impurity diffuses in a large amount into the n-type semiconductor region 29 through the connection hole 34, and the n-type impurity does not diffuse to the channel forming region side of the MISFETQs for memory cell selection. Impurities are introduced at low impurity concentrations.

Next, as shown in FIG. 36, a polycrystalline silicon film is further deposited on the polycrystalline silicon film. The upper polycrystalline silicon film is deposited by CVD to form a film thickness of about 250 to 350 nm. In the upper polycrystalline silicon film, an n-type impurity, for example, p, which reduces resistance after deposition, is introduced by thermal diffusion. This n-type impurity is introduced at a high impurity concentration in order to improve the charge accumulation amount of the information storage capacitor C for the stacked structure.

Next, as shown in FIG. 37, the lower layer electrode layer 35 is formed by processing the polycrystalline silicon film into a predetermined shape using the photolithography technique and the anisotropic etching technique. The photolithographic technique includes a step of forming an etching mask (photoresist film) and a step of removing the etching mask. Removing step of the etching mask is, for example, runs in the plasma processing of the downstream using a mixed gas of Freon gas (CHF ₃₎ and oxygen gas (O _2). This process has the effect of reducing damage to each element of the DRAM 1.

In the DRAM 1 constituting the memory cell M as a series circuit of the memory cell selection MISFETQs and the stacking information storage capacitor C of the stacked structure, the memory cell selection of the stacking information storage capacitor C of the stacked structure Polycrystalline silicon film in which n-type impurity which reduces resistance value at low concentration is introduced into lower electrode layer 35 connected to one n-type semiconductor region 29 of MISFETQs, and polycrystalline silicon in which n-type impurity is introduced at high concentration Each of the films is composed of a composite film obtained by sequentially stacking. By this structure, the film thickness of the lower electrode layer 35 of the information storage capacitor C of the memory cell M stacked structure is made thick, and the area of the sidewall of the lower electrode layer 35 is increased as much as the film thickness is made thicker. Direction, the amount of charge accumulation can be increased, the area of memory cell M can be reduced, and the degree of integration can be improved. Since the concentration of impurities on the surface of the polysilicon film of the upper layer of the lower electrode layer 35 is high, the amount of charge accumulation is increased. Similarly, the degree of integration can be further improved, and the impurity concentration of the polycrystalline silicon film of the lower electrode layer 35 is lowered so that the amount of diffusion of n-type impurities toward one of the n-type semiconductor regions 29 of the MISFETQs for memory cell selection is reduced. Therefore, the short channel effect of the memory cell selection MISFETQs can be reduced, and the area of the memory cell M can be reduced to further improve the degree of integration. In the present invention, the polycrystalline silicon film may be deposited in three or more layers, and the lower electrode layer 35 may be formed by introducing n-type impurities into each polycrystalline silicon film.

Further, in the DRAM 1 constituting the memory cell M with a series circuit of memory cell selection MISFETQs and a stacked structure information storage capacitor C, the memory cell selection MISFETQs phase of the p-type well region 22 is formed. Depositing a polycrystalline silicon film of the first layer on the entire surface of the interlayer insulating film 33 including n, and then introducing an n-type impurity which reduces the resistance value to the polycrystalline silicon film of the first layer, and the polycrystal of the first layer After depositing a polycrystalline silicon film of the second layer on the entire surface of the silicon film, introducing the n-type impurity reducing the resistance value to the polycrystalline silicon film of the second layer, the polycrystalline silicon film of the second layer, and the first Predetermined patterning is performed on each of the layered polycrystalline silicon films by anisotropic etching to form the lower electrode layer 35 of the information storage capacitor C of the stacked structure. By this structure, even if the film thickness of the lower electrode layer 35 of the information storage capacitor C of the stacked structure is thickened to some extent and the amount of impurities introduced therein is also uniformized, the anisotropic etching of anisotropic etching is increased. Also, the etching speed can be increased. Since the anisotropy of the anisotropic etching is improved, the size of the lower electrode layer 35 can be reduced, so that the area of the memory cell M can be reduced to improve the degree of integration of the DRAM 1.

(Dielectric Film Formation Process)

Next, as shown in FIG. 38, a dielectric film 36 is formed on the entire surface of the substrate including the lower electrode layer 35 of the data storage capacitor C of the memory cell M stacked structure. As described above, the dielectric film 36 is basically formed in a two-layer structure in which each of the silicon nitride film 36A and the silicon oxide film 36B is sequentially stacked. The lower silicon nitride film 36A is deposited, for example, by CVD to form a film thickness of about 5 to 7 nm. When the silicon nitride film 36A is formed, intrusion of oxygen is suppressed as much as possible. In the case where the silicon nitride film 36A is formed on the lower electrode layer 35 (polycrystalline silicon film) at a normal production level, intrusion of a small amount of oxygen occurs, and thus, between the lower electrode layer 35 and the silicon nitride film 36A. A natural silicon oxide film (not shown) is formed.

The silicon oxide film 36B in the upper layer of the dielectric film 36 is formed by subjecting the silicon nitride film 36A in the lower layer to a high pressure oxidation method and having a film thickness of about 1 to 3 nm. When the silicon oxide film 36B is formed, the film thickness of the lower silicon nitride film 36A is slightly reduced. The silicon oxide film 36B is basically formed in a high pressure of 1.5 to 10 torr and an oxygen gas atmosphere at a high temperature of about 800 to 1000 ° C. In this embodiment, the silicon oxide film 36B has a high pressure of 3 to 3.8 torr and an oxygen flow rate (source gas) at 21 / min and a hydrogen flow rate (source gas) at 3 to 81 / min. The silicon oxide film 36B formed by the high pressure oxidation method can be formed with a desired film thickness in a short time compared with the silicon oxide film formed at atmospheric pressure of 1 torr. In other words, the high-pressure oxidation method can shorten the heat treatment time at high temperature, so that the pn junction depth of the source region and the drain region, such as MISFETQs for memory cell selection, can be made shallow. The natural silicon oxide film can be thinned by reducing the ingress of oxygen. In addition, although the number of manufacturing steps increases, the dielectric film 36 may be formed into a two-layer structure by nitriding the natural silicon oxide film.

(Gate Wiring Formation Step 3)

Next, a polycrystalline silicon film is deposited on the entire substrate including the dielectric film 36. The polysilicon film is deposited by CVD to form a film thickness of about 80 to 120 nm. This polycrystalline silicon film is formed by the gate wiring forming process of the 3rd layer in a manufacturing process. Thereafter, an n-type impurity, for example, p, which reduces the resistance value, is introduced into the polycrystalline silicon film by the thermal diffusion method.

Next, an etching mask is formed on the polysilicon film on the entire surface of the memory cell array 11E except for the connection region between one n-type semiconductor region 29 and the complementarity data line 50 of the memory cell selection MISFETQs. . The etching mask is formed of, for example, a photoresist film using a photolithographic technique. Thereafter, as shown in FIG. 39, the upper electrode layer 37 is formed by sequentially anisotropic etching each of the polysilicon film and the dielectric film 36 using the etching mask. By forming the upper electrode layer 37, the information storage capacitor C of the stacked structure is substantially completed, and as a result, the memory cell M of the DRAM 1 is completed. After completion of the memory cell M, the etching mask is removed.

Next, as shown in FIG. 40, thermal oxidation is performed to form an insulating film (silicon oxide film) 38 on the surface of the upper electrode layer 37. Next, as shown in FIG. The step of forming the insulating film 38 is a step of oxidizing a residual (polycrystalline silicon film) of etching remaining on the bottom surface (the surface of the interlayer insulating film 33) when the upper electrode layer 37 is patterned. Since the stacked information storage capacitor C has a two-layer lower electrode layer 35 and an upper electrode layer 37 deposited on top of the memory cell selection MISFETQs, the stepped shape is large, in particular, the complementarity data line 50 and the memory. The stepped shape of the connection portion of the cell M is large, and etching residues are likely to occur. This etching residue short-circuits the complementarity data line 50 and the upper electrode layer 37.

The memory cell selection MISFETQs in which one n-type semiconductor region 29 is connected to the complementary data line 50 and the lower electrode layer 35, the dielectric film 36, and the upper electrode layer 37 formed on the upper layer are thus formed. In the DRAM 1 constituting the memory cell M in a series circuit of the information storage capacitor C of a stacked structure in which each is sequentially stacked, a polycrystalline silicon film is deposited on the dielectric film 36 of the memory cell M by CVD. The polycrystalline silicon film is subjected to anisotropic etching to form a predetermined pattern to form the upper electrode layer 37, and an insulating film 38 (silicon oxide film) by thermal oxidation on the surface of the upper electrode layer 37. It includes a step of forming a. This configuration makes it possible to oxidize the etching residue of the polycrystalline silicon film remaining in the stepped portion of the bottom surface after the polycrystalline silicon film is patterned by a thermal oxidation process to be performed thereafter, so that the upper electrode layer 37 and the complementary data line 50 It is possible to improve the manufacturing efficiency in manufacturing by preventing the short circuit of).

(High concentration semiconductor region formation process 2)

Next, in the formation region of the p-channel MISFETQp of the peripheral circuit, the interlayer insulating film 33 formed in the above-described process is subjected to anisotropic etching to form the sidewall spacer 33C as shown in FIG. The sidewall spacers 33C are formed on the sidewalls of the sidewall spacers 31 and are self-aligned with respect to the gate electrode 27. The sidewall spacer 33C is formed to lengthen the dimension in the gate length direction of the sidewall spacer 31 of the p-channel MISFETQp. The dimension in the gate length direction, which is the sum of the sidewall spacers 31 and 33C, is formed as about 200 nm as described above.

Next, an insulating film (not shown) is formed on the entire surface of the substrate including the upper layer electrode layer 37, the n-channel MISFETQn, and the p-channel MISFETQp forming region of the stacked structure information storage capacitor C. This insulating film is mainly used as an antifouling film at the time of introducing impurities. The insulating film is formed of, for example, a silicon oxide film deposited by a CVD method using inorganic silane gas and nitrogen oxide gas as a source gas, and is formed to a thin film thickness of about 10 nm.

Next, in the formation region of the n-channel MISFETQn in the peripheral circuit, the p-type impurity 39p is introduced as shown in FIG. In introducing the p-type impurity 39p, the sidewall spacers 31 and 33C are mainly used as the impurity introduction mask. In addition, the regions other than the formation region of the p-channel MISFETQp, that is, each of the formation regions of the memory cell array 11E and the n-channel MISFETQn, do not show an impurity introduction mask (photoresist film) when the p-type impurity 39p is introduced. Covered with The p-type impurity 39p is introduced by an ion implantation method of energy of about 50 to 70 KeV using BF ₂ (or B) having an impurity concentration of about 10 ¹⁵ atoms / cm ² , for example.

Thereafter, heat treatment is performed to extend and diffuse the above-described p-type impurity 39p to form the p + type semiconductor region 39. The heat treatment is performed for about 20 to 40 minutes at a high temperature of about 900 to 1000 ° C, for example. By forming the p + type semiconductor region 39, the p-channel MISFETQp of the LDD structure is completed. The p-channel MISFETQp is heat treated to increase the dimension in the gate length direction of the sidewall spacer 31 by the sidewall spacer 33C, and to form the capacitor C for the information storage of the stacked structure of the memory cells M (e.g., For example, it is formed after the dielectric film 36 is formed. That is, the p-channel MISFETQp can reduce the short channel effect by reducing the diffusion of the p + type semiconductor region 39 toward the channel forming region.

In the DRAM 1 having the memory cell M composed of a series circuit of the memory cell selection MISFETQs and the stacked information storage capacitor C and the complementary MISFET of the LDD structure constituting the peripheral circuit. A step of sequentially forming each of the memory cell selection MISFETs of the memory cells M, the n-channel MISFETQn of the peripheral circuit, the gate insulating film 26 of the p-channel MISFETQp, and the gate electrode 27, respectively, in this gate electrode 27 Self-alignment with each other to form the n-type semiconductor region 29 and the p-type semiconductor region 30 having low impurity concentrations forming LDD structures of the memory cell selection MISFETQs, n-channel MISFETQn, and p-channel MISFETQp, respectively. A step of forming sidewall spacers 31 on the sidewalls of the gate electrodes 27 of the memory cell selection MISFETQs, n-channel MISFETQn, and p-channel MISFETQp, and self-aligning with respect to the sidewalls 31. Of the n-channel MISFETQn Forming an n + type semiconductor region 32 having a high impurity concentration, forming an information storage capacitor C having a stacked structure of the memory cell M, and forming a sidewall on the sidewall of the gate electrode 27 of the p-channel MISFETQp. A step of forming the sidewall spacers 33C in a self-aligning manner with respect to the gate electrode 27 via the wall spacer 31 is a high impurity of the p-channel MISFETQp in a self-aligning manner with respect to the sidewall spacers 33C. Forming a p + type semiconductor region 39 at a concentration. With this configuration, the n-channel MISFETQn defines dimensions in the gate length direction of the n-type semiconductor region 29 having a low impurity concentration, which forms an LDD structure with a sidewall spacer 31 of a single layer. The length in the gate length direction of (29) can be shortened, and the p-channel MISFETQp is formed into several sidewall spacers 31 and 33C toward the channel forming region of the p + type semiconductor region 39 having a high impurity concentration. The p + type semiconductor region 39 having a high impurity concentration is formed after the heat treatment is performed to define the amount of return loss of the memory cell and to form the information storage capacitor C of the stacked structure of the memory cell M. Return loss to the channel forming region side of the semiconductor region 39 can be further reduced.

An interlayer insulating film 33 is formed after the step of forming the n + type semiconductor region 32 having a high impurity concentration of the n-channel MISFETQn, and before the step of forming the capacitor C for information storage of the stacked structure of the memory cell M. After the interlayer insulating film 33 is formed, the sidewall spacer 33C is formed using the interlayer insulating film 33. With this structure, a part of the step of forming the sidewall spacer 33C (film deposition step) can be used as a step of forming the interlayer insulating film 33, so that the DRAM 1 can be used as much as this step. The number of manufacturing steps can be reduced.

(Interlayer Insulating Film Formation Step 2)

Next, an interlayer insulating film 40 is laminated on the entire substrate including each element of the DRAM 1. The interlayer insulating film 40 is formed of, for example, a silicon oxide film deposited by a CVD method using inorganic silane gas and nitrogen oxide gas as a source gas. The interlayer insulating film 40 is formed to have a film thickness of, for example, about 250 to 350 nm.

Next, as shown in FIG. 43, a connection hole 40A is formed in the interlayer insulating film 40 at the connection portion between the memory cell M and the complementarity data line 50. Next, as shown in FIG. This connection hole 40A is formed by anisotropic etching, for example.

(Gate Wiring Formation Step 4)

Next, as shown in FIG. 44, a complementary data line is connected to one n-type semiconductor region 29 of the memory cell selection MISFETQs through the connection hole 40A, and extends on the interlayer insulating film 40. DL) 50 is formed. The complementarity data line 50 is formed in the gate wiring forming step of the fourth layer in the manufacturing step. The complementary data line 50 has a two-layer structure in which each of the polycrystalline silicon film 50A and the transition metal film silicide film 50B is sequentially stacked. The lower polycrystalline silicon film 50A is deposited by CVD to form a film thickness of, for example, about 80 to 120 nm. In the polycrystalline silicon film 50A, n-type impurities such as p are introduced by thermal oxidation after deposition. Since the polycrystalline silicon film 50A deposited by the CVD method has high step coverage at the stepped portion of the connection hole 40A, the disconnection failure of the complementary data line 50 can be reduced. In addition, in the connection portion of the memory cell M and the complementary data line 50, the insulating film for isolation between elements is caused by a mask misalignment in the manufacturing process of the connection hole 40A and the isolation insulation film 23 between the elements. When a part of the connection hole 40A is caught on the 23, n-type impurities are diffused from the polycrystalline silicon film 50A to the main surface portion of the p-type well region 22 to complementarity with the n-type semiconductor region 29. Since the data line 50 can be connected, a short circuit between the complementary data line 50 and the p-type well region 22 can be prevented. The upper transition metal silicide film 50B is formed of, for example, a WSi ₂ film deposited by a CVD method, and has a film thickness of about 100 to 200 nm. The upper transition metal silicide film 50B is mainly formed in order to reduce the resistance value of the complementary data line 50 so as to speed up each of the write operation of the information and the read operation of the information. In addition, since the upper transition metal silicide film 50B is deposited by the CVD method, the disconnection failure of the complementary data line 50 can be further reduced.

The complementarity data line 50 is formed by depositing each of the lower polycrystalline silicon film 50A and the upper transition metal silicide film 50B, and then patterning it into a predetermined shape by, for example, anisotropic etching. have.

(Interlayer Insulating Film Formation Process 3)

Next, an interlayer insulating film 51 is formed on the entire surface of the substrate including the complementary data line 50. The interlayer insulating film 51 has a two-layer structure in which each of the silicon oxide film 51A and the BPSG film 51B is sequentially stacked. The lower silicon oxide film 51A is deposited by a CVD method using, for example, inorganic silane gas and nitrogen oxide gas as a source gas, and is formed to a film thickness of about 100 to 200 nm. The lower silicon oxide film 51A is formed to prevent leakage of impurities (each of P and B) of the upper BPSG film 51B. The upper BPSG film 51B is, for example, deposited by CVD to form a film thickness of about 250 to 350 nm. The BPSG film 51 is flowed at a temperature of about 800 ° C. or higher in a nitrogen gas atmosphere, and the surface thereof is flattened.

Next, as shown in FIG. 45, a connection hole 51C is formed in the interlayer insulating film 51. Next, as shown in FIG. The connection hole 51C is disposed on the n + type semiconductor region 32, the p + type semiconductor region 39, the wiring 50 (not shown), the upper electrode layer 37, or the like of each element of the DRAM 1. The interlayer insulating film 51 is removed. The connection hole 51C is formed by anisotropic etching, for example.

Further, in the p-channel MISFETQp formation region, the p + type semiconductor region 39 has a large diffusion coefficient of the p type impurity, so that the surface impurity concentration is thinner than that of the n + type semiconductor region 32. In the n + type semiconductor region 32, a region having a high impurity concentration on the surface is etched by over etching when the connection hole 51C is formed, and the impurity concentration on the surface is further lowered. In the p + type semiconductor region 39, since the wiring 52 connected to the p + type semiconductor region 39 is formed of the transition metal film (W film), the work function difference becomes larger than that of the n + type semiconductor region 32. Thus, the p-channel MISFETQp introduces p-type impurities into the surface of the p + -type semiconductor region 39 within the region defined by the connection hole 51C to increase the p-impurity concentration on the surface of the p + -type semiconductor region 39. You may also This configuration can reduce the connection resistance between the p + type semiconductor region 39 and the wiring 52 of the p-channel MISFETQp.

Wiring Formation Process 1

Next, as shown in FIG. 46, a wiring (column selection signal line diagram) is provided on the interlayer insulating film 51 so as to be connected to the n + type semiconductor region 32, the p + type semiconductor region 39, and the like through the connection hole 51C. 52). The wiring 52 is formed of a transition metal film deposited by a sputtering method, for example, a W film, and formed at a film thickness of about 350 to 450 nm, for example. The wiring 52 can be formed by depositing on the entire surface of the interlayer insulating film 51 and patterning it into a predetermined shape by, for example, anisotropic etching.

(Interlayer Insulating Film Formation Process 4)

Next, as shown in FIG. 47, an interlayer insulating film 53 is formed on the entire surface of the substrate including the wiring 52 above. The interlayer insulating film 53 is a three-layer structure in which a silicon oxide film (deposited insulating film) 53A, a silicon oxide film (coated insulating film) 53B, and a silicon oxide film (deposited insulating film) 53C are sequentially stacked. Consists of The lower silicon oxide film 53A is deposited by a C-CVD method using tetraethoxy silane gas as a source gas to form a film thickness of about 250 to 350 nm. The silicon oxide film 53B of the intermediate layer is formed to planarize the surface of the interlayer insulating film 53. The silicon oxide film 53B is applied several times (2 to 5 times) by SOG method (coating at a film thickness of about 100 to 150 nm in total), and then bake treatment (about 450 DEG C) to retreat the surface by etching. It is formed by making. By the retreat by the above etching, the silicon oxide film 53B is formed only in the concave portion of the stepped shape of the surface of the lower silicon oxide film 53A. The intermediate layer of the interlayer insulating film 53 may be formed of an organic material film, for example, a polyimide resin film instead of the silicon oxide film 53B. The upper silicon oxide film 53C is deposited by the C-CVD method using, for example, tetraethoxy silane gas as a source gas in order to increase the strength of the film as the entire interlayer insulating film 53, and has a film thickness of about 250 to 350 nm. To form.

Next, the predetermined wiring 53 on the interlayer insulating film is removed to form the connection hole 53D. The connection hole 53D is formed by anisotropic etching, for example.

Next, the transition metal film 54 is laminated (embedded) on the surface of the wiring 52 exposed in the connection hole 53D. The transition metal film 54 is formed of, for example, a W film deposited by a selective CVD method to a film thickness of about 600 to 800 nm. The reaction formula of this W film is as follows.

(Wiring forming process 2)

Next, as shown in FIG. 49, wirings (including shunt word lines) 55 are formed on the interlayer insulating film 53 so as to be connected to the transition metal film 54 embedded in the connection hole 53D. . The wiring 55 has a two-layer structure in which each of the transition metal nitride film (or the transition metal film) 55A and the aluminum alloy film 55B is sequentially stacked. The lower transition metal nitride film 55A is formed of, for example, a TiN film deposited by a sputtering method and is formed to a film thickness of about 130 to 180 nm. As described above, the transition metal nitride film 55A is configured to prevent the precipitation phenomenon of Si and the alloying reaction of W and aluminum in the connection hole 53D. The upper aluminum alloy film 55B is, for example, deposited by a sputtering method to form a film thickness of about 600 to 800 nm.

The wiring 55 can be formed by sequentially stacking each of the lower transition metal silicide film 55A and the upper aluminum alloy film 55B, and then patterning the film to a predetermined shape by anisotropic etching, for example. .

Passivation film formation process

Next, as shown in FIG. 1, a passivation film 56 is formed on the entire surface of the substrate including the wiring 55. As shown in FIG. As described above, the passivation film 56 is formed of a composite film in which each of the silicon oxide film 56A and the silicon nitride film 56B is sequentially laminated. As described above, the underlying silicon oxide film 56A is deposited by the C-CVD method using tetraethoxysilane gas as the source gas. The upper silicon nitride film 56B is deposited by plasma CVD.

In addition, although not shown in FIG. 1, the resin film is apply | coated to the upper layer of the passivation film 56. As shown in FIG. This resin film is formed in order to improve the alpha ray soft error internal pressure. This resin film is formed in the film thickness of about 8-12 micrometers using the polyimide-type resin film apply | coated, for example by the potting technique (including the resin dripping coating process, the baking process process, and the patterning process). The resin film basically penetrates the position corresponding to the external terminal and is applied to the entire surface of the DRAM 1 except this region. Moreover, you may arrange | position this resin film in the shape divided into several on the surface of DRAM1. That is, the resin film is disposed in each of the areas where the? Line soft error withstand voltage of the DRAM 1 is to be ensured, for example, the memory cell array 11E, and portions of the direct peripheral circuits 12 and 13, respectively. This area is used as a divided area without being disposed in other parts of the indirect peripheral circuit and the direct peripheral circuit. By dividing the resin film in this manner, stress of the resin film can be reduced to prevent cracking of the passivation film and the like.

(Fuse Opening Process)

In the DRAM 1, a Y-based redundant circuit 1812 for saving each of the defective complementarity data line DL 50, the defective word line WL 27 (or the shunt word line 55), and the X-based redundant Circuits 1806 are disposed respectively. The Y redundant circuit 1812 performs the switching from the defect complementarity data line 50 to the redundant complementarity data line 50 by cutting the fuse element F or not. Similarly, the X-based redundant circuit 1806 performs the switching from the defective word line 27 to the redundant word line 27 by cutting off the fuse element F or not.

As shown in FIG. 50 (main part sectional drawing), the said fuse element F is formed with the same conductive layer as the complementarity data line 50 and the wiring 50. As shown in FIG. Since the DRAM 1 of this embodiment employs a laser cutting method, the fuse element 50 is cut by laser light. Since the cutoff becomes unstable when the passivation film 56 of the thick film thickness exists, the fuse open hole 56C formed in the passivation film 56 is provided on the fuse device 50. Since the etching gas used to pierce the fuse opening hole 56C is also an etching gas for etching the fuse element 50, it is also an etching gas for etching the fuse element 50. 51 and the insulating film of an appropriate film thickness (film thickness of 800 nm or less) of the interlayer insulating film 53 are left. The conductive layer underneath the fuse element 50, for example, the same conductive layer as the upper electrode layer 37 of the capacitor C for stacking structure, has a thin film thickness and thus has a high resistance value, which is not preferable as the fuse element F. not. In addition, since a large number of layers of insulating films exist in the upper conductive layer in the same conductive layer as each of the lower electrode layer 35 and the gate electrode 27, the process of forming a fuse opening hole becomes more complicated. Moreover, since the conductive layer similar to each of the wirings 52 and 55 of the upper layer of the fuse element 50 reflects the laser light, it is not preferable as the fuse element F.

The method of forming the fuse element 50 and the fuse opening hole 56C will be briefly described using FIGS. 51 to 53 (the main part sectional drawing shown for each manufacturing process).

First, as shown in FIG. 51, the fuse element 50 is formed in the same manufacturing process as the complementarity data line 50 on the formation area of the fuse element F of the interlayer insulating film 40. As shown in FIG.

Next, an interlayer insulating film 51 (51A and 51B) is formed, and then as shown in FIG. 52, a wiring 52 is formed. As shown in FIG. 52, the wiring 52 does not exist on the fuse element 50. As shown in FIG.

Next, the interlayer insulating films 53 (53A, 53B, and 53c) are formed, and then the wiring 55 is formed as shown in FIG. The wiring 55 does not exist on the fuse device 50.

Next, a passivation film 56 is formed, and as shown in FIG. 50, a fuse open hole 56C is formed in the passivation film 56 on the fuse element 50. As shown in FIG. Although the fuse opening hole 56C is not described, it can be formed in the same manufacturing process as the process of drilling a portion where the external terminal BP of the passivation film 56 exists (bonding).

Thus, at the intersection of the complementarity data line 50 and the word line 27, the memory cell M composed of the memory cell selection MISFETQs and the series circuit of the information storage capacitor C of the stacked structure is disposed, and the complementary data line ( 50. Alternatively, in the DRAM 1 having the laser cutting redundancy fuse element 50 for repairing the defective complementary data line 50 or the defective word line 27 in the word line 27, the complementary data line 50 ) Is composed of a composite film in which each of the polycrystalline silicon film 50A and the transition metal silicide film 50B deposited by CVD is sequentially stacked, and the redundancy fuse element 50 for laser cutting is used as the complementary data line 50. ) And the same conductive layer. With this arrangement, the complementarity data line 50 is formed above the memory cell selection MISFETQs of the memory cell M and the information storage capacitor C of the stacked structure, so that the redundant fuse element 50 for laser cutting is formed. The number of layers of the insulating film on the upper layer is reduced, and the open hole process of the insulating film on the upper layer of the redundancy fuse element 50 for laser cutting can be simplified, and the polysilicon film 50A and the transition metal silicide film 50B are used. Since the formed composite film has a higher absorption rate than that of each of the wirings 52 and 55 formed on the complementary data line 50, the laser beam can be easily and easily cut. You can certainly run it.

The DRAM 1 of the present embodiment is completed by performing these series processes of forming the passivation film 56 and openings therein.

Next, the manufacturing process of each main part in the manufacturing process of DRAM 1 mentioned above is demonstrated in detail.

Wiring and connection hole formation process

In the method for manufacturing the DRAM 1 described above, each of the complementary data lines DL 50, the wiring 52, the wiring 55, the connection holes 40A, 51C, and 53D is basically a multilayer resist. It is processed by photolithographic technique using a mask. The multilayer resist mask is formed by sequentially laminating a non-photosensitive resin film (holding film such as a polyimide resin film), an intermediate film (an inorganic film such as a silicon oxide film coated by SOG method), and a photosensitive resin film, for example, 3 It is formed into a layer structure.

The multilayer resist mask is mainly used for the purpose of improving the processing precision of the upper photosensitive resin film and the processing accuracy of the etching target material by alleviating the step shape grown by the multilayer structure with the lower layer film and the intermediate film. The multilayer resist mask is formed by the following method.

First, each of the non-photosensitive resin film, the intermediate film, and the photosensitive resin film is sequentially laminated on the surface of the etching target material (for example, the complementary data line 50 or the like) to form a multilayer resist film.

Next, the photosensitive resin film on the upper layer of the multilayer resist film is processed by ordinary exposure treatment and development treatment to form an etching mask.

Next, using the etching mask, each of the intermediate film and the non-photosensitive resin film of the multilayer resist film is sequentially patterned by anisotropic etching to form a multilayer resist mask. During this patterning, the underlying non-photosensitive resin film is patterned by an anisotropic etching technique using oxygen (O ₂ ) gas and halogen (Cl ₂ , Br _2, etc.) gas. As an etching apparatus, a reactive ion etching (RIE) apparatus, a magnetron type RIE apparatus, or a microwave ECR apparatus is used, for example. The etching pressure is, for example, about 1 to 10 mtorr and the high frequency output is about 0.25 to 30 W / cm ² . The halogen gas used in the anisotropic etching is a solid, for example, vinyl chloride, mounted in a vacuum chamber, and the halogen gas (halogen compound is generated simultaneously) as the external gas of vinyl chloride is used instead of the vacuum chamber. Supply from the outside to the inside.

The anisotropic etching gas of the oxygen gas and the halogen gas generates carboxylic acid when the lower layer of the non-photosensitive resin film is etched with oxygen gas, and when the halogen gas is added to the carboxylic acid, acid chloride having a lower vapor pressure is produced, so that the generated gas leaks well. As a result, the amount of side etching of the underlying non-photosensitive resin film can be reduced.

In this way, the multilayer resist film is formed in a three-layer structure, and the lower non-photosensitive resin film is patterned by anisotropic etching using oxygen gas and halogen gas. With this configuration, since halogen gas is used as the anisotropic etching gas, the side etching amount of the lower non-photosensitive resin film can be reduced to improve the processing accuracy and the halogen compound (CF ₄ , CCl ₄ ) as the anisotropic etching gas. Since it is not used, the organic substance can be prevented from adhering to the patterned side surface of the underlying non-photosensitive resin film. The prevention of adhesion of this organic substance can reduce the removal process, and can also reduce the contamination of the inner wall of the vacuum chamber of the etching apparatus. In addition, it is possible to reduce the contamination adhering to the inner wall of the vacuum chamber and to reduce the reattachment of the organic matter separated from the inner wall to the surface of the semiconductor wafer during the manufacturing process, thereby improving manufacturing efficiency in manufacturing.

In addition, since the halogen compound, especially carbon (C), is not used as the anisotropic etching gas, the anisotropic etching rate can be increased.

In addition, since the anisotropic etching uses pure halogen gas outside the vacuum chamber without using halogen gas as a solid external gas, the above-described effects can be obtained.

Wiring Formation Process 1

In the above-described method for manufacturing the DRAM 1, the processing of the wiring 52, that is, the W film, can improve processing accuracy by employing low temperature anisotropic etching.

Anisotropic etching for processing the wiring 52 is performed in a vacuum chamber such as an RIE apparatus. The vacuum chamber is normally maintained at a vacuum degree in the range of about 10 ⁻¹ to 10 ⁻³ torr, and anisotropic etching is performed in this state. As shown in FIG. 54 (a diagram showing the relationship between temperature and vapor pressure of tungsten hexafluoride WF ₆ ), WF ₆ has a vapor pressure of 0 mTorr or a vacuum degree in the vacuum chamber at a low temperature of about −40 ° C. or lower. Come close. In other words, the wiring 52 is not vaporized because ions do not collide with the processed sidewall by anisotropic etching in the low temperature region, so that ions collide with the bottom surface during processing to vaporize, thereby anisotropic etching. Can improve. As a result, the processing precision of the wiring 52 can be improved.

(Connection hole forming process)

In the above-described method for manufacturing the DRAM 1, each of the connection holes 51C (or 53D) can be formed in a tapered shape using a magnetron RIE device or a microwave ECR device.

The connection hole 51C can control the taper angle (step difference angle of the connection hole) by controlling the etching pressure, the etching gas flow rate or the high frequency output during the etching conditions. In order to control the taper angle without impairing the etching performance, it is preferable to control the etching pressure or the etching gas flow rate. The etching rate of the anisotropic etching is determined by the product of the ion current and the average ion energy, and when the ion current is constant, the taper angle is determined as the average ion energy. On the other hand, the ion current is proportional to the high frequency output, and when the high frequency output is constant, it tends to be inversely proportional to the voltage Vdc between the semiconductor wafer (electrode) and the plasma.

As shown in Fig. 55 (a), the relationship between the etching pressure and the energy, the anisotropic etching using the RIE apparatus has a narrow stable discharge region with respect to the etching pressure, a sharp change in the voltage Vdc, and a change in the average ion energy. So steep. That is, the controllability of the taper angle is bad.

On the other hand, as shown in Fig. 55 (b), the relationship between the etching pressure and the energy, the anisotropic etching using the magnetron RIE device (or the µ-wave ECR device) has a large amount of ions in the order of 1 to 2 digits. The stable discharge area against pressure is widened. Therefore, as shown in Fig. 55 (c), the relationship between the ion energy and the etching rate, and Fig. 55 (d), the relationship between the ion energy and the taper angle, the controllability of the taper angle is increased. The etching rate of the stepped portion is the etching rate determined by ion energy corresponding to the cos θ times the ion energy of the flat portion. This indicates that the ion current density of the stepped portion of the taper angle θ corresponds to the cos θ times the ion current density of the flat portion. Further, as the taper angle θ approaches 90 degrees, the stepped portion of the connecting hole becomes steep, and as the taper angle θ approaches 0 degrees, the stepped portions are relaxed.

By forming the connection hole 51C by anisotropic etching using the magnetron RIE device (or μ-wave ECR device) as described above, the stable discharge area with respect to the etching pressure is widened to change the voltage Vdc and the average ion energy, respectively. In this way, the controllability of the taper angle can be improved without impairing the etching performance. That is, as shown in FIG. 55 (d), the taper angle can be easily formed without fluctuating from 60 to 80 degrees. As a result, since the tapered shape can be formed in the connection hole 51C, the disconnection defect of the wiring 52 can be reduced in the stepped portion of the connection hole 51C. In addition, since the connection hole 53D embeds the transition metal film 54 in this embodiment, there is no problem, but in the case of not embedding it, a tapered shape is similarly provided.

(Connection hole forming process)

In the method for manufacturing the DRAM 1 described above, processing of the insulating film such as the connection holes 51C and 53D is performed by low temperature anisotropic etching.

First, the DRAM 1 (semiconductor wafer before the dicing step) is directly adsorbed to the lower electrode in the vacuum chamber of the etching apparatus via the electrostatic adsorption plate. This lower electrode is always cooled, and as a result, the semiconductor wafer is kept at a temperature below room temperature. In this state, each of the interlayer insulating films 51 and 53 is anisotropically etched to form each of the connection holes 51C and 53D.

Since the anisotropic etching gas (halogen compound CHF ₃ ) is deposited on the surface of the semiconductor wafer having a lower temperature than the inner wall of the etching chamber, the use of low temperature anisotropic etching can reduce the flow rate of the anisotropic etching gas, and It is possible to reduce the contaminants attached.

Example 2

In the second embodiment, the second embodiment of the present invention adopts the individual formula in the process of embedding the transition metal film in the connection hole for connecting between different wiring layers in order to improve the manufacturing efficiency of the DRAM 1 of the first embodiment. Example.

56 is a sectional view of the main part, showing a main part of the DRAM 1 as the second embodiment.

As shown in FIG. 56, the DRAM 1 of the second embodiment is a transition metal embedded in the wiring 81 formed on the bottom insulating film 80 and in the connection hole 82A formed in the interlayer insulating film 82. The film 83 is connected. The wiring 81 is formed of an aluminum film or an aluminum alloy film. The interlayer insulating film 82 is formed of a single layer of a silicon oxide film or a composite film mainly composed of it. The transition metal film 83 embedded in the connection hole 82A is formed of a W film deposited by the selective CVD method. Although not shown, a wiring extending over the interlayer insulating film 82 is connected to the transition metal film 83. The structure shown in FIG. 56 can be formed by a manufacturing method employing the following individual formula.

First, a connection hole 82A is formed in the interlayer insulating film 82, and the surface of the wiring 81 is exposed in the connection hole 82A. The surface of the wiring 81 is exposed to be oxidized to produce alumina (Al ₂ O ₃ ).

Next, the alumina produced on the surface of the wiring 81 is removed by the sputtering method. As the sputtering method, a sputtering method in which argon (Ar) gas and fluorine (NF ₃ , XeF, CF ₄ or CHF ₃ ) gas are mixed. The argon gas can remove alumina generated on the surface of the wiring 81 by the argon ions by sputtering. Fluorine-based gas may promote the sputter rate of the alumina. In addition, the fluorine-based gas removes the unbound bond layer formed by the collision of argon ions on the surface of the interlayer insulating film 92 to improve the selectivity of the transition metal film 83 and to corrode the surface of the wiring 81. Don't let that happen. That is, argon gas alone forms unbonded damage on the surface of the interlayer insulating film 82, thereby eliminating the selectivity of the transition metal film 83, and when argon gas is mixed with a halogen compound such as Cl ₂ , The layer can be removed, but since the surface of the wiring 81 is corroded, the sputtering method is formed by mixing fluorine-based gas with argon gas as described above.

Next, a transition metal film 83 is selectively deposited on the surface of the wiring 81 in the connection hole 82A, and the transition metal film 83 is embedded in the connection hole 82A.

As described above, by removing the alumina on the surface of the wiring 81 by the sputtering method using the above-described mixed gas, the connection between the wiring 81 and the transition metal film 83 can be satisfactorily performed and the transition metal film ( 83) selectivity can be secured.

As shown in FIG. 56, fluorine (F) of the fluorine-based gas used in the sputtering method sputters the surface of the wiring 81 to lead aluminum particles to the outside. These aluminum particles adhere to the inner wall of the connection hole 82A to produce cross contamination 81A. This cross-contaminant 81A has a higher deposition rate of the transition metal film 83 than the surface of the interlayer insulating film 82, so that the upper portion of the transition metal film 83 protrudes more than the surface of the interlayer insulating film 82. The protrusion of the transition metal film 83 lowers the processing precision of the upper wiring connected thereto.

The DRAM 1 shown in FIG. 57 (main cross-sectional view) has the cross-contaminant 81A remaining as it is, so as to reduce the protrusion of the transition metal film 83, and the tapered portion 82B above the connection hole 82A. ). The tapered portion 82B can be formed by isotropic etching. The connection hole 82A can be formed by anisotropic etching. That is, the taper portion 82B removes a portion of the upper side of the cross-contaminant 81A to expose the surface of the interlayer insulating film 82, and lowers the deposition rate of the transition metal film 83 in this portion, thereby reducing the transition metal film. Protrusion of 83 can be prevented. On the other hand, by remaining the cross-contaminants 81A, the deposition rate of the transition metal film 83 can be increased, so that the manufacturing time can be shortened.

In addition, the DRAM 1 shown in FIG. 58 (main cross-sectional view) actively creates cross-contaminants 81A on the inner wall of the connection hole 82A to accelerate the deposition speed of the transition metal film 83. .

In addition, although the deposition rate of the transition metal film 83 is slightly delayed, substantially all cross-contaminants 81A may be removed to completely form the connection holes 82A in a tapered shape.

In addition, by adopting a separate formula, the controllability of the film thickness of the transition metal film 83 can be improved as compared with the batch type.

Example 3

The third embodiment is different from the DRAM 1 of the second embodiment described above, but the third embodiment of the present invention employs a transition metal film embedded in a connection hole for connecting the semiconductor substrate and the wiring layer, and employs a separate formula in this step. Example.

59 is a diagram showing a main part (main part cross-sectional view) of the DRAM 1 according to the third embodiment of the present invention.

As shown in FIG. 59, the DRAM 1 of the third embodiment has connection holes formed in the interlayer insulating film 80 in the n + type semiconductor region 32 formed in the main surface portion of the p-type well region 22. As shown in FIG. The transition metal film 84 embedded in 80A is connected. The n + type semiconductor region 32 is silicon (Si) as described in Embodiment 1 described above. The interlayer insulating film 80 is formed of a single layer of a silicon oxide film or a composite film mainly composed of it. The transition metal film 84 embedded in the connection hole 80A is a W film 84A and silane reduction deposited by a selective CVD method using a silicon reduction reaction (reaction of Si and WF _{6 in} the n + type semiconductor region 32). Each of the W films 84B deposited by the selective CVD method using a reaction (reaction of SiH ₄ and WF ₆ ) is formed as a composite film in which layers are sequentially layered. Since the lower W film 84A is a silicon reduction reaction, the adhesion between the n + type semiconductor region 32 and the transition metal film 84 can be improved. Since the upper layer W film 84B is a silane reduction reaction, the amount of reduction of the surface of the n + type semiconductor region 32 can be reduced to form the n + type semiconductor region 32 having a shallow pn junction depth. The upper portion of the transition metal film 84 is connected to a wiring (for example, an aluminum alloy film) 81 extending on the interlayer insulating film 80.

The structure shown in FIG. 59 shows that the upper layer W is formed after some time has elapsed after forming the lower layer W film 84A in the process of forming the transition metal film 84 embedded in the connection hole 80A. When the film 84B is deposited, both interfaces are peeled off (the peeling portion is indicated by reference numeral 84C). This peeling occurs because the stress of the upper W film 84B is larger than that of the lower W film 84A. The exfoliation also occurs when a reaction byproduct, for example, a fluorine gas, is present.

The DRAM 1 shown in FIG. 60 (main part sectional view) forms each of the W film 84A of the lower layer of the said transition metal film 84, and the W film 84B of the upper layer in succession, and peels off the interface of both. Is removing. The continuous formation method of each of the W film 84A of the lower layer and the W film 84B of the upper layer of this transition metal film 84 is as follows.

First, in the selective CVD method employing the individual formula in Fig. 61A, as shown in the relationship between the deposition time of the W film and the source gas flow rate, WF ₆ is supplied as the source gas into the reactor of the CVD apparatus. WF ₆ reacts with Si on the surface of the n + type semiconductor region 32 exposed in the connection hole 80A shown in FIG. 60 to start forming the lower W film 84A. Along with the supply of WF ₆ , the relationship between the deposition time and the amount of generation of the reaction byproducts F ₂ , SiF ₃ and SiF ₄ as shown in FIG. 61 (b) is monitored. The generation amount of the reaction byproduct can be measured by a gas mass analyzer disposed in an exhaust gas supply pipe from the reactor or a plasma light emitting monitor disposed in the reactor (room).

Next, when the lower W film 84A is formed, Si on the surface of the n + type semiconductor region 32 is not exposed, so that deposition of the W film is automatically stopped. As shown in each of (b), silane gas is supplied to the reactor before completion of the silicon reduction reaction from the reduction in the amount of reaction by-products generated, and the W film 84B of the upper layer begins to be deposited. That is, the silicon reduction reaction is switched to the silane reduction reaction to sequentially form each of the lower layer W film 84A and the upper layer W film 84B. The upper W film 84B is deposited at a predetermined film thickness.

Thus, by forming each of the W film 84A of the lower layer and the W film 84B of the upper layer of the said transition metal film 84 in succession, peeling of the interface between them can be prevented.

In addition, by employing a separate formula, the controllability of the film thickness of the transition metal film 84 can be improved as compared with the batch type.

Example 4

In the fourth embodiment, the information storage capacitor C of the stacked structure of the memory cells M of the DRAM 1 of the above-described embodiment 1 is described. The fourth embodiment.

62 is a schematic structural diagram showing a separate CVD apparatus according to Embodiment 4 of the present invention.

As shown in FIG. 62, the individual CVD apparatus mainly includes a load unload chamber 90, a transfer chamber 91, a pretreatment chamber 92, a first reactor chamber 93, and a second reactor. It consists of the yarns 94. Each of the processing chambers 90 to 94 is connected via a gate valve 96.

The load unloading chamber 90 is configured such that a cassette 90A containing a plurality of semiconductor wafers 100 is detachably attached thereto. The load unloading chamber 90 is configured to supply the unprocessed semiconductor wafer 100 to the transfer chamber 91 and to store the processed semiconductor wafer 100 in the transfer chamber 91.

The transfer chamber 91 supplies the unprocessed semiconductor wafer 100 to each of the processing chambers 92 to 93 and supplies the processed semiconductor wafer 100 to each of the processing chambers 92 to 93. It is configured to withdraw from. As shown in FIG. 63 (the schematic view of the main part), the supply and withdrawal of the semiconductor wafer 100 is connected to the rotary drive device 91A and driven to the wafer carrier arm and tray 91B driven therefrom. Is executed by The transfer chamber 91 is isolated from the respective treatment chamber (90), (92) - (93), respectively, like the device of the external atmosphere is maintained high degree is H ₂ O or O ₂ is not present.

As shown in FIG. 62 and FIG. 63, this conveyance chamber 91 is equipped with the ultraviolet irradiation lamp 95. As shown in FIG. The ultraviolet irradiation lamp 95 is configured to irradiate the surface of the semiconductor wafer 100 conveyed to the transfer chamber 91 with ultraviolet rays of energy of at least 5 to 6 KeV or more and to break the bond between Si and F. .

The pretreatment chamber 92 is provided with a pretreatment module 92A. The pretreatment module 92A mainly includes a hot plate 92a, a temperature controller 92b, an exhaust pipe 92c, a vacuum pump 92d, a medical generator tube 92e, a microwave generator 92f, and a microwave power source ( 92g) and a gas control part 92h. That is, the pretreatment chamber 92 is comprised so that an anisotropic etching may remove the natural silicon oxide film formed in the surface of the polycrystalline silicon film on the surface of the semiconductor wafer 100. This polycrystalline silicon film corresponds to the lower electrode layer 35 of the information storage capacitor C of the stacked structure in the DRAM 1 of the first embodiment described above. The anisotropic etching (dry etching) uses an oxygen gas and a halogen compound (CHF ₃ or CF ₄ ).

Each of the first reactor chamber 93 and the second reactor chamber 94 is provided with a common 93A cleaning module. Each of the first reactor chamber 93 and the second reactor chamber 94 is mainly a source gas supply pipe 93a and a source gas ejection plate (shown in FIG. 64 (the main part schematic configuration diagram)). 93b), plate cooling tube 93c, susceptor 93d, wafer heating heater 93e, reactor cooling tube 93f, exhaust pipe 93g, vacuum gate valve 93h, and vacuum pump 93i. It is. Although not limited to this, the first reactor chamber 93 deposits a silicon nitride film (dielectric (silicon nitride film 36A in the lower layer of the film 36)), and the second reactor chamber 94 is a polycrystalline silicon film. The lower electrode layer 35 or the upper electrode layer 37 is configured to be deposited.

When the DRAM 1 has a large capacity of 16 Mbit, for example, the controllability of the film thickness of the lower electrode layer 35 and the dielectric film 36 of the information storage capacitor C of a stacked structure is required. Therefore, a separate CVD apparatus is suitable for manufacturing this DRAM 1. Each of the first reactor chamber 93 and the second reactor chamber 94 has a source gas at a position opposite to the surface of the semiconductor wafer 100 held by the susceptor 93d to become a deposition surface. The jet plate 93b is arranged so that the film can be deposited on the surface of the semiconductor wafer 100 with a uniform film thickness and film quality. Each of the first reactor chamber 93 and the second reactor chamber 94 is maintained at a low temperature as a whole by the reactor cooling tube 93f, and the semiconductor wafer 100 by the wafer heating heater 93e. ) Is heated to the optimum temperature for the reaction.

In addition, the source gas ejection plate 93b is provided with a plate cooling tube 93c in order to reduce the temperature rise due to the radiant heat of the semiconductor wafer 100. Particles immediately reacted in the vicinity of the source gas outlet are grown into coarse particles at the point of reaching the surface of the semiconductor wafer 100 so that the source gas ejection plate 93b is transferred to the plate cooling tube 93c. Need to cool.

As described above, the individual CVD apparatus is a batch continuous process in which a pretreatment chamber 92 is provided at the front end of each of the first reactor chamber 93 and the second reactor chamber 94, and the processing method thereof. Is as follows.

First, as shown in FIG. 62, the semiconductor wafer 100 is conveyed from the load unload chamber 90 to the pretreatment chamber 92 via the transfer chamber 91. As shown in FIG. A polycrystalline silicon film is deposited on the surface of the semiconductor wafer 100.

Next, the pretreatment chamber 92 removes, by anisotropic etching, the natural silicon oxide film formed on the surface of the polycrystalline silicon film on the surface of the semiconductor wafer 100 as shown in FIGS. 62 and 63. This anisotropic etching is performed using an oxidizing gas and a halogen compound as etching gas as mentioned above.

Next, the semiconductor wafer 100 from which the natural silicon oxide film has been removed from the pretreatment chamber 92 is transferred to the transfer chamber 91, and the ultraviolet ray is irradiated to the surface of the polycrystalline silicon film by the ultraviolet irradiation lamp 95 from the transfer chamber 91. Investigate Since the fluorine (F) generated by anisotropic etching adheres to the surface of the said polycrystalline silicon film by this ultraviolet irradiation, this fluorine acts as a radical and scatters on the surface of the polycrystalline silicon film.

Next, the semiconductor wafer 100 is sequentially conveyed to each of the first reactor chamber 93 and the second reactor chamber 94 via the transfer chamber 91, and the first reactor chamber 93 is then transferred. ), A silicon nitride film and the like are deposited on the surface of the polycrystalline silicon film in each of the second reactor chambers 94.

The semiconductor wafer 100 after the processing is stored in the load unloading chamber 90 via the transfer chamber 91.

In the film deposition method of depositing an insulating film or a conductive film on the polycrystalline silicon film (or the surface of the semiconductor wafer 100) deposited on the surface of the semiconductor wafer 100 as described above, the surface of the semiconductor wafer 100 in a vacuum system. Cleaning the surface of the polycrystalline silicon film in the pretreatment chamber 92 and exposing the surface of the polycrystalline silicon film; and the first reactor chamber 93 or the first reaction chamber on the surface of the polycrystalline silicon film in the same vacuum system as the cleaning tablet. And depositing an insulating film or a conductive film in the reactor chamber 94 of FIG. 2. With this configuration, since the natural silicon oxide film formed on the surface of the polycrystalline silicon film is removed by a washing step, an insulating film or a conductive film can be deposited on the surface of the polycrystalline silicon film without being exposed to the atmosphere, so that the surface of the polycrystalline silicon film and the insulating film Alternatively, the natural silicon oxide film is not interposed between the conductive films. As a result, the thickness of the surface of the polycrystalline silicon film and the insulating film deposited on the surface thereof, for example, the silicon nitride film 36A of the dielectric film 36 can be made as thin as that equivalent to that of the natural silicon oxide film. The charge accumulation amount of the capacitor C for the information storage can be increased. Further, conduction between the surface of the polycrystalline silicon film and the conductive film deposited on the surface can be reliably performed.

Further, in the film deposition method for depositing an insulating film on the surface of the polycrystalline silicon film (or semiconductor wafer 100) on the surface of the semiconductor wafer 100, the surface of the polycrystalline silicon film on the surface of the semiconductor wafer 100 in a vacuum system Is washed with anisotropic etching using a halogen compound, exposing the surface of the polycrystalline silicon film, irradiating ultraviolet rays to the exposed surface of the polycrystalline silicon film in the same vacuum system as the cleaning process, and the same vacuum system as the cleaning process. And depositing the insulating film (for example, silicon nitride film) on the surface of the polycrystalline silicon film therein. This structure makes it possible to remove radicals of halogen elements adhering to the surface when the surface of the polycrystalline silicon film is cleaned by the ultraviolet rays, so that the leakage current of the insulating film deposited on the surface of the polycrystalline silicon film, for example, silicon nitride film, is increased. And change in etching rate can be reduced.

Example 5

Embodiment 5 of the present invention has described the most suitable formation method and implementation device of the lower electrode layer 35 in the information storage capacitor C of the stacked structure of the memory cells M of the DRAM 1 of Embodiment 1 described above. The fifth embodiment of.

The individual CVD method according to the fifth embodiment of the present invention is applied to each of Figs. 65 (a timing diagram showing the opening and closing operation of the source gas valve of the CVD apparatus) and 66 degrees (tanging degree indicating the flow rate of the source gas). Illustrated.

The lower electrode layer 35 of the information storage capacitor C of the stacked structure of the memory cells M of the DRAM 1 of the first embodiment is formed with a thick film thickness in order to increase the charge storage amount as described above. When the thickness of the lower electrode layer 35 is thick, it is difficult to introduce n-type impurities that reduce resistance, but this embodiment 5 uses a technique of depositing a polycrystalline silicon film into which the n-type impurities are introduced, a so-called doped polysilicon technique. The lower electrode layer 35 is formed.

The polycrystalline silicon film in which no n-type impurity deposited by the CVD method is usually introduced has a high step coverage at the bottom step portion, but when the film thickness becomes thick, it is difficult to introduce the n-type impurity after deposition. On the other hand, the polycrystalline silicon film into which the n-type impurity deposited by the CVD method is introduced is easy to introduce the n-type impurity, but has poor step coverage at the bottom stepped portion. Therefore, the fifth embodiment improves step coverage at the bottom step portion by alternately stacking each of the polycrystalline silicon film into which the n-type impurity is not introduced and the polycrystalline silicon film into which the n-type impurity is introduced. After each polycrystalline silicon film is deposited, heat treatment is performed to introduce an n-type impurity into the polycrystalline silicon film into which the n-type impurity is not introduced.

FIG. 65 shows the opening and closing operation of the control valve disposed in the source gas supply pipe of the CVD apparatus. The source gas uses inorganic silane (SiH ₄ or Si ₂ H ₆ ) gas and phosphine (PH ₃ ) gas, respectively. The valve for controlling the supply of the inorganic silane gas in the source gas is opened for a predetermined time to reach a predetermined film thickness as shown in FIG. 65 (a). On the other hand, the control valve which supplies phosphine gas repeats opening / closing operation | movement regularly at the time of opening of the control valve of inorganic silane gas, as shown to FIG. 65 (b). FIG. 66 (a) shows the flow rate of the inorganic silane gas controlled by the control valve, and FIG. 66 (b) shows the flow rate of the phosphine gas. The intermittent supply of the phosphine gas can also be controlled by increasing or decreasing the set value of the mass flow controller. The intermittent switching of the phosphine gas by the control valve or the mass flow controller can be performed at a high speed of about 1 to 2 seconds.

In addition, as shown in FIG. 67 (Schematic diagram of the individual CVD apparatus), a stop valve is located near the reactor chamber 93 (or 94) of the source gas PH ₃ supply pipe 93a. 93j may be provided and the source gas may be supplied to each of the reactor chamber 93 and the vacuum pump 93i at a high speed through the stop valve 93j. The CVD apparatus shown in FIG. 67 can switch the intermittent supply of phosphine gas in about 0.1 second.

As described above, in the film deposition method for depositing a polycrystalline silicon film (for example, lower electrode layer 35) on a bottom surface having a stepped shape, polycrystalline silicon containing n-type impurities on the bottom surface is reduced. A process of laminating a plurality of layers of the film and the polycrystalline silicon film not containing the n-type impurity, wherein the stacked polycrystalline silicon film is subjected to heat treatment and contains n-type impurity in the polycrystalline silicon film containing the n-type impurity And diffusing the n-type impurity into a non-crystalline polysilicon film. This configuration makes it possible to supplement the step coverage of the polycrystalline silicon film containing n-type impurities in the stepped region of the bottom surface with the polycrystalline silicon film containing no n-type impurities, thereby making the film thickness of the polycrystalline silicon film uniform. In addition, since the n-type impurity can be diffused from the polycrystalline silicon film containing the n-type impurity to the polycrystalline silicon film containing no n-type impurity, the thick film is made uniform while the impurity concentration of the multiple stacked polycrystalline silicon film is uniform. The thickness can be secured.

In the film deposition method of depositing a polycrystalline silicon film on a bottom surface having a stepped shape, an inorganic silane gas flows at a constant flow rate in a vacuum system in which the polycrystalline silicon film is deposited, and a polycrystalline silicon film containing no impurities is formed by thermal decomposition. At the same time as the deposition, the flow rate is periodically increased and decreased in the vacuum system so that phosphine gas flows, and the n-type impurity p is periodically contained in the deposited polycrystalline silicon film. By this structure, since each of the polycrystalline silicon film containing the n-type impurity and the polycrystalline silicon film not containing the n-type impurity can be continuously deposited in the same vacuum system, the deposition time of the polycrystalline silicon film can be shortened. In other words, the throughput of the DRAM 1 can be improved.

Example 6

This sixth embodiment is the sixth embodiment of the present invention in which the process of setting the threshold voltage of the MISFET is reduced in the method of manufacturing the DRAM 1 described above.

A manufacturing method of the DRAM 1 according to the sixth embodiment of the present invention will be briefly described using Figs. 68 to 71 (the main cross-sectional views shown for each manufacturing step).

The sixth embodiment sets the threshold voltages of six MISFETs used in the DRAM 1 of the first embodiment. That is, the n-channel MISFETs are memory cell selection MISFETQs for memory cell M, n-channel MISFETQn having a standard threshold voltage, and n-channel MISFETQn having a low threshold voltage. Examples of the p-channel MISFETs include p-channel MISFETQp having a standard threshold voltage, p-channel MISFETQp having a low threshold voltage, and p-channel MISFETQp having a high threshold voltage.

The memory cell selection MISFETQs (formed in region I in the manufacturing method described later) are set to the highest threshold voltage as the n-channel MISFET. That is, in the memory cell selection MISFETQs, the p-type semiconductor region 25B is formed in the main surface of the p-type well region 22 in the memory cell array 11E, so that the impurity concentration on the surface becomes high and the threshold voltage is increased. It is set high. Specifically, the memory cell selection MISFETQs have a threshold voltage of 0.8V when the gate length dimension is 0.8 mu m.

The n-channel MISFETQn (formed in the region III) having the above standard threshold voltage is used in most of the peripheral circuits except the sense amplifier circuit SA 13, that is, the region operated at the low power supply voltage Vcc. The n-channel MISFETQn having this standard threshold voltage has a threshold voltage of 0.5V when the gate length dimension is 0.8 mu m.

The n-channel MISFETQn (formed in region II) having the low threshold voltage is mainly used in each of the sense amplifier circuit 13 and the output buffer circuit 1702. The n-channel MISFETQn having this low threshold voltage has a long gate length dimension in order to reduce the variation of the threshold voltage caused by the processing deviation of the gate electrode 27, especially the variation in the gate length dimension. In the sense amplifier circuit 13, when the gate length dimension is longer, the sensitivity at the time of information determination is lowered, so that the threshold voltage of the n-channel MISFETQn is lowered. In addition. The output buffer circuit 1702 sets the threshold voltage of the n-channel MISFETQn low because the drive capability of the rear stage device decreases when the gate length dimension becomes longer. The n-channel MISFETQn having this low threshold voltage has a gate length dimension of 1.4 mu m, and the threshold voltage is set at 0.5V. That is, the n-channel MISFETQn having the low threshold voltage sets the threshold voltage to 0.3V when the gate length dimension is converted to 0.8 mu m again.

On the other hand, the p-channel MISFETQp (formed in the region IV) having the standard threshold voltage is used in most of the peripheral circuits except the sense amplifier circuit 13, that is, in the region operated by the low power supply voltage Vcc. The p-channel MISFETQp having this standard threshold voltage has a threshold voltage of -0.5V when the gate length dimension is formed to 0.8 mu m.

The p-channel MISFETQp (formed in the region V) having the low threshold voltage is used as the sense amplifier circuit 13. In addition, the p-channel MISFETQp having a low threshold voltage is used to form the reference potential of the reference voltage generating circuits of the VCC limiter circuit 1804 and the VDL limiter circuit 1810 (the low power supply voltage Vcc is about 3.3V). It is used as one p-channel MISFETQp forming the reference potential -1.0V). The p-channel MISFETQp having a low threshold voltage used as the sense amplifier circuit 13 has a gate length dimension of 1.4 mu m and a threshold voltage of -0.5 V (threshold voltage is low as an absolute value). . That is, the p-channel MISFETQp having the low threshold voltage sets the threshold voltage to -0.2V when the gate length dimension is converted back to 0.8 mu m. On the other hand, the p-channel MISFETQp having a low threshold voltage used as the reference voltage generating circuit has a gate length dimension of 8 mu m and a threshold voltage of -0.6V. That is, the p-channel MISFETQp having the low threshold voltage sets the threshold voltage to -0.2V when the gate length dimension is converted back to 0.8 mu m.

The p-channel MISFETQp having the high threshold voltage (formed in region VI) is used as the other p-channel MISFETQp forming the reference potential of the reference voltage generating circuit. The p-channel MISFETQp having a high threshold voltage used in this reference voltage generator circuit has a gate length dimension of 8 mu m and a threshold voltage of -1.6 V (threshold voltage is absolute high). That is, the p-channel MISFETQp having a high threshold voltage sets the threshold voltage to -1.2 V when the gate length dimension is converted back to 0.8 mu m.

Next, a method of forming each MISFET of the DRAM 1 will be briefly described.

First of all, the n-type well region 21 and the p-type well region 22 are formed in the main surface of the p-type semiconductor substrate 20 similarly to the method of manufacturing the DRAM 1 of the first embodiment described above. Thereafter, the insulating film 23 for isolation between the elements, the p-type channel stopper region 24, the p-type channel stopper region 25A, and the p-type semiconductor region 25B are sequentially formed. This formed state is shown in FIG. Since the DRAM 1 has a high integration, the isolation dimension between the p-channel MISFETQp is reduced and the separation ability is reduced, so that the impurity concentration of the n-type well region 21 is set slightly higher. Specifically, the n-type well region 21 is set to an impurity concentration of about 1 × 10 ¹³ to 3 × 10 ¹³ atoms / cm ² , for example. The impurity concentration of the n-type well region 21 can set the high threshold voltage (absolute value) of the p-channel MISFETQp formed in the region VI. On the other hand, since the gate length dimension of the n-channel MISFETQn having the standard threshold voltage is reduced by the high integration, the DRAM 1 has a low substrate effect constant and impurity concentration in the p-type well region 22 results in a short channel effect. You can set it slightly higher to suppress it. Specifically, the p-type well region 22 is set to an impurity concentration of, for example, about 7 × 10 ¹² to 2 × 10 ¹² atoms / cm ² . The impurity concentration of the p-type well region 22 can set the low threshold voltage of the n-channel MISFETQn formed in the region II. Further, the high threshold voltage of the memory cell selection MISFETQs in the region I can be set by the impurity concentration in the p-type well region 22 and the boiling of impurities from the p-type semiconductor region 25B.

Next, as shown in FIG. 69, the p-type impurity 22p is introduced into the region III to set the standard threshold voltage of the n-channel MISFETQn. The p-type impurity 22p is introduced by an ion implantation method of energy of about 15 to 25 KeV using, for example, an impurity concentration of B of about 1 × 10 ¹² to 9 × 10 ¹² atoms / cm ² . When the p-type impurity 22p is introduced, an impurity introduction mask (for example, a photoresist film) 110 shown in FIG. 69 is used.

Next, as shown in FIG. 70, the p-type impurity 21p1 is introduced into the region IV to set the standard threshold voltage of the p-channel MISFETQp. p-type impurity (21p1), for example using B of ^{2.0 × 10 12 ~2.2 × 10 12} atoms / cm 2 level of impurity concentration is introduced to the ion implantation method of the degree 15~25KeV energy. When the p-type impurity 21p1 is introduced, an impurity introduction mask (for example, a photoresist film) 111 shown in FIG. 70 is used.

Next, as shown in FIG. 71, the p-type impurity 21p2 is introduced into the region V to set the low threshold voltage of the p-channel MISFETQp. This p-type impurity 21p2 is introduced by an ion implantation method of energy of about 15 to 25 KeV using B having an impurity concentration of about 2.4 x 10 ^{12 to} 2.6 x 10 ¹² atoms / cm ² , for example. In this p-type impurity 21p2, an impurity introduction mask (for example, a photoresist film) 112 shown in FIG. 70 is used for introduction.

In addition, the order of introduction of the threshold voltage adjustment impurities described above is not limited to this and may be introduced either first or later.

As described above, in the DRAM 1 having the complementary MISFET, the high threshold voltage (absolute value) of the p-type well region 22 and the p-channel MISFET Qp is set to an impurity concentration that sets the low threshold voltage of the n-channel MISFETQn. Forming each of the n-type well regions 21 in the main surface portion of the other region of the p-type semiconductor substrate 20 with an impurity concentration to be set, and a threshold value in the main surface portion of the p-type well region 22. A voltage threshold p-type impurity 22p is introduced to set the standard threshold voltage of the n-channel MISFETQn, and at the same time, the threshold voltage-adjustment 21p1 (or (21p2)) is formed on the main surface of the n-type well region 21. ) To set the standard (or low absolute) threshold voltage of the p-channel MISFET. With this configuration, the low threshold voltage of the n-channel MISFET is set to the impurity concentration of the p-type well region 22, and the high threshold voltage of the p-channel MISFET Qp is impurity of the n-type well region 21. Since the density can be set and four kinds of threshold voltages can be set by the introduction of two p-type impurities 22p and 21p1 (or 21p2) for the threshold voltage, the threshold voltage is adjusted. The number of impurity introduction steps can be reduced.

Each of the n-type well region 21 and the p-type well region 22 is formed in self-alignment with respect to each of the main surface portions of the p-type semiconductor substrate 20. This configuration eliminates the need to expose the surface of the p-type semiconductor substrate 20 in addition to the n-type well region 21 and the p-type well region 22, so that the equivalent of this process The number of manufacturing steps of the DRAM 1 can be reduced.

In the DRAM 1 having a p-channel MISFETQp generating a reference voltage and a p-channel MISFETQp having a standard threshold voltage, the high threshold voltage of the p-channel MISFETQp generating the reference voltage (absolutely high) Forming an n-type well region 21 with an impurity concentration to set?, And a threshold voltage adjusting impurity 21p1 (or (21p2)) is introduced into another region of the n-type well region 21 to obtain p. A process of setting the standard threshold voltage (or low threshold voltage) of the channel MISFETQp, and introducing the threshold voltage adjusting impurity 21p1 (or 21p2) into the other region of the n-type well region 21 to supply the p-channel. And setting the low threshold voltage (or standard threshold voltage) of the MISFETQp. This configuration makes it possible to set the low threshold voltage of the p-channel MISFETQp that generates the reference voltage to the impurity concentration in the n-type well region 21, and to set three types of threshold voltages for two threshold voltage adjustments. Since the introduction of the impurities 21p1 and 21p2 can be performed, the number of steps for introducing the impurities for threshold voltage adjustment can be reduced.

Example 7

The seventh embodiment is the seventh embodiment of the present invention in which the amount of charge accumulation of the information storage capacitor C of the stacked structure of the memory cells M is increased in the DRAM 1 of the first embodiment described above.

A main part of the DRAM 1 of Embodiment 7 of the present invention is shown in FIG. 72 (a plan view of the main part of a memory cell array in a predetermined manufacturing process).

As shown in FIG. 72, the memory cell M of the DRAM 1 of the seventh embodiment has grooves 35g formed in the lower electrode layer 35 of the capacitor C for stacking information. That is, since the information storage capacitor C of the stacked structure can increase the surface area in the height direction by the inner wall of the groove 35g of the lower electrode layer 35, the amount of charge storage can be improved. The groove 35g is configured to cross the lower electrode layer 35 in the direction in which the word line WL 27 extends.

Next, a method of forming the information storage capacitor C of the stacked structure of the memory cell M will be briefly described using Figs. 73 to 76 (the main part cross sectional diagram shown for each manufacturing process).

First, the MISFETQs for selecting memory cells of the memory cells M are formed in the same manner as the manufacturing method of the DRAM 1 of the first embodiment described above, and then the interlayer insulating film 33 is formed as shown in FIG.

Next, as shown in FIG. 74, a polysilicon film 35B is formed on the entire surface of the substrate including the interlayer insulating film 33. As shown in FIG. As described above, the polycrystalline silicon film 35B is formed with a thick film thickness and n-type impurities are introduced to reduce the resistance value. In order to introduce the n-type impurity, the polycrystalline silicon film described in Example 1 is divided into several layers, and a method of introducing the n-type impurity by thermal diffusion method is employed every time. In the introduction of the n-type impurity, a method of alternately stacking each of the polycrystalline silicon film into which the n-type impurity described in Example 5 is not introduced and the polycrystalline silicon film into which the n-type impurity is introduced are alternately stacked and then subjected to heat treatment. To be adopted.

Next, as shown in FIG. 75, the polysilicon film 35B and the interlayer insulating film 33 at the connection portion of the memory cell selection MISFETQs and the lower electrode layer 35 of the information storage capacitor C of the stacked structure. Each is sequentially removed to form the groove 35g. The groove 35g is formed by anisotropic etching, for example. By forming the groove 35g, the surface of the other n-type semiconductor region 29 of the memory cell selection MISFETQs is exposed.

Next, a polycrystalline silicon film 35C is formed on the entire surface of the polycrystalline silicon film 35B including the surface of the inner wall of the groove 35g and the surface of the exposed n-type semiconductor region 29. This polycrystalline silicon film 35C is formed with a thin film thickness (film thickness that can secure a stepped shape) in which the groove 35g is not embedded. An n-type impurity is introduced into the polycrystalline silicon film 35C, and the n-type impurity is introduced at a lower impurity concentration than the polycrystalline silicon film 35B in order to reduce the short channel effect of the MISFETQ for memory cell selection.

Next, as shown in FIG. 76, each of the polycrystalline silicon films 35C and 35B is sequentially patterned to form the lower electrode layer 35. As shown in FIG. Since the manufacturing method after this is substantially the same as the manufacturing method of the DRAM 1 of the first embodiment, the description is omitted here.

As described above, in the data storage capacitor C of the stacked structure of the memory cells M of the DRAM 1, by providing the groove 35g in the lower electrode layer 35, the charge is equivalent to the groove 35g. The amount of accumulation can be improved.

The lower electrode layer 35 of the information storage capacitor C of the stacked structure has a complementarity data line DL as shown in FIG. 77 (a plan view of the main part of the memory cell in a predetermined manufacturing process). You may provide the groove | channel 35g which transverses in the extension direction of (). Since the DRAM 1 of the seventh embodiment adopts the folded bit line system, the arrangement interval in the extension direction of the word line 27 of the lower electrode layer 35 is small, and the lower electrode layer 35 has a complementary data line ( 50) is formed in a long rectangular shape in the extending direction. Therefore, the increase in the surface area of the lower electrode layer 35 due to the groove 35g becomes larger than that described above.

The method of forming the information storage capacitor C of the stacked structure shown in FIG. 77 will be briefly described using FIGS. 78 to 80 (the cross sectional view of the main part shown in each manufacturing process).

First, as shown in FIG. 78, a polycrystalline silicon film 35B is formed on the entire surface of the substrate including the interlayer insulating film 33. As shown in FIG.

Next, as shown in FIG. 79, grooves 35g are formed in the polycrystalline silicon film 35B.

Next, a polycrystalline silicon film 35C is formed on the polycrystalline silicon film 35B, and patterning is performed on each of the polycrystalline silicon films 35C and 35B, as shown in FIG. The electrode layer 35 may be formed.

The lower electrode layer 35 of the information storage capacitor C of the stacked structure described with reference to FIGS. 72 through 76 is shown in FIGS. 81 through 84 (cross-sectional view of the main part shown in each manufacturing process). The charge accumulation amount can be further improved.

First, as shown in FIG. 81, the polycrystalline silicon film 35B is formed, and then as shown in FIG. 82, the groove 35g is formed.

Next, as shown in FIG. 83, the polycrystalline silicon film 35B is previously patterned in the shape of the lower electrode layer 35, and the groove 35g is formed at the same time.

Next, a polycrystalline silicon film 35C is formed on the front surface of the substrate including the surface of the inner wall of the groove 35g, the surface of the polycrystalline silicon film 35B, and the exposed surface of the n-type semiconductor region 29. .

Next, the lower electrode layer 35 is formed by patterning the polycrystalline silicon film 35C by anisotropic etching. The lower electrode layer 35 can improve the amount of charge accumulation by the groove 35G as described above, and at the same time, the polycrystalline silicon film 35C is formed on the sidewall of the outer circumference of the polycrystalline silicon film 35B of the lower electrode layer 35. Since it can remain, the amount of charge accumulation can be further improved as much as the film thickness of the remaining polycrystalline silicon film 35C.

Similarly, the lower electrode layer 35 of the information storage capacitor C of the stacked structure described with reference to FIGS. 77 through 80 is shown in FIGS. 85 through 88 (cross-sectional view of the main part shown in each manufacturing process). Similarly, the charge accumulation amount can be further improved.

First, as shown in FIG. 85, the polysilicon film 35B is formed, and then as shown in FIG. 86, the groove 35g is formed.

Next, as shown in FIG. 87, the polycrystalline silicon film 35B is previously patterned in the shape of the lower electrode layer 35. As shown in FIG.

Next, a polycrystalline silicon film 35C is formed on the front surface of the substrate including the surface of the inner wall of the groove 35g, the surface of the polycrystalline silicon film 35B, and the exposed surface of the n-type semiconductor region 29. .

Next, the lower electrode layer 35 is formed by patterning the polycrystalline silicon film 35C by anisotropic etching. The lower electrode layer 35 can leave the polycrystalline silicon film 35C on the sidewalls of the outer circumference of the polycrystalline silicon film 35B, so that the amount of charge accumulation is as large as the film thickness of the remaining polycrystalline silicon film 35C. It can be further improved.

Example 8

This eighth embodiment is the eighth embodiment of the present invention in which the degree of mask alignment (alignment) misalignment is reduced and the degree of integration is improved in the method of manufacturing the DRAM 1 of the first embodiment described above.

An alignment relationship in the manufacturing process of the DRAM 1 according to the eighth embodiment of the present invention is shown in FIG. 89 (alignment tree diagram).

The DRAM 1 of the first embodiment aligns (aligns) the upper layer pattern with respect to the lower layer pattern in the manufacturing process. FIG. 89A shows the alignment relationship in the X direction (for example, the direction in which the word lines are extended). The DRAM 1 of the eighth embodiment executes the alignment reference in the n-type well region 21. The insulating film 23 for element isolation is performing alignment in the X direction with respect to the n-type well region 21. The gate electrode (word line) 27 performs alignment in the X direction with respect to the insulating film 23 for element isolation. This gate electrode 27 serves as a reference for alignment of the upper layer. Each of the lower electrode layer 35, the upper electrode layer 37, and the connection hole 40A of the information storage capacitor C of the laminated structure is aligned in the X direction with respect to the gate electrode 27. As shown in FIG.

On the other hand, Fig. 89 (b) shows the alignment relationship in the Y direction (for example, the extension direction of the complementarity data line). The DRAM 1 of the eighth embodiment performs alignment in two directions, the X direction and the Y direction. Similarly, the n-type well region 21 serves as a reference for alignment, and the insulating film 23 for isolation between the elements performs alignment in the Y direction with respect to the n-type well region 21. The gate electrode 27 performs alignment in the Y direction with respect to the insulating film 23 for element isolation. Unlike the alignment in the X direction, the lower electrode layer 35 performs alignment in the Y direction with respect to the insulating film 23 for isolation between the elements. Each of the upper electrode layer 37 and the connection hole 40A is aligned in the Y direction with respect to the gate electrode 27.

The n-type semiconductor region 29 on the other side of the memory cell selection MISFETQs when the lower electrode layer 35 of the information storage capacitor C having a stacked structure causes large alignment misalignment with respect to the interlayer isolation insulating film 23. A hole is formed in the connection hole 34 connecting the lower electrode layer 35 with the lower electrode layer (see FIG. 1). By this hole, the surface of the n-type semiconductor region 29 exposed in the connection hole 34 during the processing of the lower electrode layer 35 is etched. Therefore, the amount of misalignment of the lower electrode layer 35 with respect to the insulating film 23 for inter-element separation needs to be kept to a minimum.

In the case where the lower electrode layer 35 is simply aligned in the X direction and the Y direction with respect to the gate electrode 27 which is the lower layer, between the insulating film 23 for isolation between the elements and the gate electrode 27, the gate Since the amount of misalignment σ between each of the electrode 27 and the lower electrode layer 35 is generated, the amount of misalignment of the lower electrode layer 35 with respect to the insulating film 23 for isolation between elements is 1.4 sigma.

Thus, in the eighth embodiment, the lower electrode layer 35 aligns the X direction (or the Y direction) with respect to the gate electrode 27 having a pattern below one layer as shown in FIG. 89 (a). As shown in Fig. 2 (b), alignment in the Y direction (or X direction) is performed on the insulating film 23 for element isolation, which is a pattern under two layers. That is, the lower electrode layer 35 of the information storage capacitor C of the stacked structure generates only an alignment misalignment σ with respect to the insulating film 23 for inter-element separation and the gate electrode 27. Since the lower electrode layer 35 is a layer which is not a reference for the alignment of the upper layer, the lower electrode layer 35 can be aligned over the other layers as described above.

Thus, in the alignment method of aligning the pattern of three different layers of the insulating film 23 for isolation | separation, the gate electrode 27, and the lower electrode layer 35 to an X direction and a Y direction, the said gate electrode (2nd layer) Pattern) 27 is aligned in the X direction and the Y direction with respect to the interlayer isolation insulating film (the first layer pattern) 23 in the lower layer, and the lower electrode layer formed on the gate electrode 27 The third layer pattern 35 is aligned in the X direction (or Y direction) with respect to the lower gate electrode 27, and at the same time, in the Y direction (or X direction) with respect to the insulating interlayer 23 for lower element isolation. ). By this structure, the amount of alignment misalignment between the isolation insulating film 23 and the gate electrode 27 between the elements and the amount of misalignment between the insulating film 23 and the lower electrode layer 35 between the elements is substantially reduced. Since it can be similar, the amount of alignment misalignment between the insulating film 23 for isolation | separation between elements and the lower electrode layer 35 can be reduced. As a result, the degree of integration of the DRAM 1 can be improved as much as the mask fitting margin in the manufacturing process. As described above, no holes exist in the connection holes 34 that connect the other n-type semiconductor region 29 and the lower electrode layer 35 of the memory cell selection MISFETQs.

Example 9

This ninth embodiment is the ninth embodiment of the present invention for explaining a method for forming a target mark when the alignment method described in the eighth embodiment is implemented in the DRAM 1 of the above-described first embodiment.

The structure of the target mark portion of the DRAM 1 of the ninth embodiment is shown in FIG. 90 (main part sectional view).

As shown in FIG. 90, the target mark TM is composed of a connection hole 53D formed in the interlayer insulating film 53 of the DRAM 1 and a wiring 55 formed on the interlayer insulating film 53. As shown in FIG. The target mark TM is used as a target mark for alignment in the semiconductor wafer state without using a scribe area between the formation regions of each DRAM 1, inside the formation region of the DRAM 1, or as a dummy DRAM 1 (DRAM). It is arranged in the formation region of the).

The target mark TM can be formed by forming the connection hole 53D in the region where the wiring (transition metal film) 52 is not formed on the interlayer insulating film 51. Since there is no wiring 52 in the lower layer inside the connection hole 53D, the transition metal film 54 for embedding is not deposited by the selective CVD method, and the wiring 55 is an aluminum alloy film having poor step coverage. Since 55B is used, a stepped shape is formed on the surface of the wiring 55 in the stepped shape of the connection hole 53D. This stepped shape is used as the target mark TM.

In this manner, the target mark TM can be used in combination with each of the step of forming the connection hole 53D in the manufacturing process of the DRAM 1 and the process of forming the wiring 55, so that the number of manufacturing steps can be reduced. .

Example 10

This tenth embodiment is the tenth embodiment of the present invention in which the depth of focus and the resolution at the time of exposure of the photolithographic technique are improved in the method of manufacturing the DRAM 1 of the above-described embodiment 1.

Each step of the photolithographic technique used in the manufacturing process of the DRAM 1 of Embodiment 10 of the present invention is shown in FIG. 91 (conceptual diagram) and 92 (process flow diagram), respectively.

The photolithographic technique of Example 10 improves the depth of focus and resolution upon exposure of the photoresist film by using the Focus Latitude Enhancement Exposure (FLEX) method and the Contrast Enhancement Lithography (CEL) method. The procedure of exposure processing of this photolithographic technique is as follows.

91 and 92, a photoresist film 120 is first applied to the semiconductor wafer 100 (1).

Next, a photochemical CEL material 121A is dropped on the surface of the photoresist film 120 coated on the semiconductor wafer 100 to apply the photochemical CEL 121 (2). As the photochemical CEL film 121, for example, nitron is used as shown in FIG. This photochemical CEL film 121 has a property of being transparent (breeching) when irradiated with a predetermined amount or more of light (initiation of irradiation t ₁ ), as shown in FIG. 94 (a diagram showing the transmittance to exposure). The photochemical CEL film 121 has a property of gradually becoming opaque when light irradiation is stopped (irradiation termination t ₂ ), and these properties have a property of repeating.

Next, in the projection exposure apparatus, the pattern of the reticle 125 is applied to the photoresist film 120 coated on the surface of the semiconductor wafer 100 via the projection optical system 124 and the photochemical CED film 121. Transfer (3). This exposure uses the FLEX method to expose the pattern overlaid while changing the depth of focus.

FIG. 95 shows the difference in depth of focus when the FLEX method is applied to the line-and-space pattern with or without the photochemical CEL film 121. FIG. 95A shows the light intensity profile at the time of exposure on the surface (in the photoresist film 120) of the semiconductor wafer 100 in the line and space pattern. As shown in FIG. 95 (a), light is irradiated to a portion corresponding to the position where the chromium pattern 125A of the reticle 125 does not exist so that the light intensity at the focus position (0 μm) is the maximum and the focus position is Light intensity decreases as it shifts up and down.

FIG. 95B shows the relationship between the light intensity profile and the characteristics of the photochemical CEL film 121 when the FLEX method is applied to increase or decrease the surface depth of the semiconductor wafer 100 step by step. When the surface of the semiconductor wafer 100 is increased by 0.5 mu m in FIG. 95 (b), the deep position of the photoresist film 120 is increased in (a) light intensity. When the light intensity reaches a certain amount for making the photochemical CEL film 121 transparent, (b) the photoresist film 120 is irradiated with an amount exceeding the predetermined amount. When the light intensity is less than a certain amount, that is, the shallow position of the photoresist film 120 is blocked by the CEL film 121 in which light irradiation is photochemical. Next, when the surface of the semiconductor wafer 100 is lowered by 0.5 mu m in FIG. 95 (b), the light intensity of the photoresist film 120 is increased in (c) light intensity. When the light intensity reaches a certain amount for making the photochemical CEL film 121 transparent, (d) the photoresist film 120 is irradiated with an amount exceeding the predetermined amount. When the light intensity is equal to or less than a certain amount, that is, the deep position of the photoresist film 120 is blocked by the CEL film 121 in which light irradiation is photochemical.

FIG. 95 (c) shows the light intensity profile of the sum of two light irradiations to which the FLEX method shown in FIG. 95 (b) is applied, and (a + b) indicates that there is no photochemical CEL film 121. (a x b + c x d) is a case where the photochemical CEL film 121 is present. In the absence of the former photochemical CEL film 121, in the line-and-space pattern, applying the FLEX method is preferable as a means for improving the depth of focus by exceeding the dissolution level of the photoresist film 120 in the unexposed areas. Not. On the other hand, when the latter photochemical CEL film 121 is provided, the resolution and the depth of focus can be improved by the breaching effect of the photochemical CEL film 121 and the change of the focus position by the FLEX method. have.

After the exposure process shown in FIGS. 91 and 92, the photochemical CEL film 121 is removed by the cleaning solution 122 (4), and the photoresist film 120 is developed with the developer 123 ( 5).

As shown in FIG. 91, the photochemical CEL film 121B may be used instead of the process of applying the photochemical CEL film 121. FIG. The photochemical CEL film 121B is used by pressing onto the surface of the photoresist film 120 coated on the surface of the semiconductor wafer 100.

In this manner, by using the FLEX method and the CEL method in the photolithographic technique, a high resolution and a high focal depth of the pattern can be obtained.

Example 11

The eleventh embodiment is the eleventh embodiment of the present invention in which the alignment accuracy of each layer is improved in the manufacturing process of the DRAM 1 of the above-described first embodiment.

The structure of the dicing process potential semiconductor wafer 100 of the DRAM 1 of Embodiment 11 of the present invention is shown in FIG. 96 (a schematic plan view).

As shown in FIG. 96, the semiconductor wafer 100 arranges several DRAMs 1 in a row form before the dicing process (before being formed into pellets). A scribe area (not shown) is provided between each DRAM 1. As shown in FIG. 97 (an enlarged plan view of the portion A of FIG. 96) and 98 (an enlarged plan view of the portion B of FIG. 97), the DRAMs (?-?) 1 adjacent to each other of the semiconductor wafer 100 are adjacent to each other. In the scribe area therebetween, target marks TM which are shared between adjacent DRAMs 1 are arranged. This target mark TM serves as a reference for positioning during alignment, for example, in a reduced projection exposure apparatus. As shown in FIG. 97 and FIG. 98, the target marks TM shared between adjacent DRAMs 1, for example, between β and γ, can be detected by one scan of the alignment beam AB in one X-direction. It is arranged to be. 97 and 98 together show the waveform of the alignment signal S when the target mark TM is detected by scanning the alignment beam AB. According to this alignment signal, the center position Xβ in the X direction, the center position Yβ in the Y direction, and the rotation amount Wβ in the DRAM (β) 1 shown in FIG. 97 can be calculated by the following equation.

In the alignment of the eleventh embodiment, the pattern (pellet pattern) of the DRAM 1 of the second layer is arranged with respect to the pattern (pellet pattern) of the DRAM 1 of the first layer arranged on the surface of the semiconductor wafer 100. In this case, the position of the target mark TM of the pattern of the DRAM 1 of the first layer is detected by the alignment beam AB, and the position thereof is calculated, so that the positional shift between the patterns of the adjacent DRAM 1 is small. The calibration is performed by arranging the pattern of the DRAM 1 of the second layer while correcting. That is, the associative alignment method of associating the pattern of the DRAM 1 of the 2nd layer with respect to the pattern of the DRAM 1 of the 1st layer is employ | adopted. This associative alignment method can ensure the regularity of arrangement between patterns of the DRAM 1 as compared with the pellet alignment method. The pellet alignment method is a method of repeating alignment and exposure for each pattern of the DRAMs 1 on the surface of the semiconductor wafer 100.

In addition, the associative alignment method does not directly cause a large alignment error even when the target mark TM is greatly wrongly detected, and thus high alignment accuracy can be obtained.

Further, the associative alignment method can obtain a greater alignment accuracy than the multi-point wafer alignment method even when there is a large distortion in the arrangement of the patterns of the DRAM 1 of the first layer. The multi-point wafer alignment method is a method in which a plurality of target marks TM on the surface of the semiconductor wafer 100 are sampled and aligned, and as a result, the array of the DRAM 1 is extracted by statistical calculation, and then only exposure is performed.

Further, the associative alignment method can calculate and correct the amount of rotation of the pattern of the DRAM 1 of the second layer in accordance with the detection of the target mark TM disposed on the four sides of the pattern of the DRAM 1 of the first layer. The correction accuracy of the higher rotation amount can be obtained as compared with the case of detecting the rotation amount by detecting the target marks TM disposed on two points of the DRAM 1, for example, up, down, left and right. Even in the case of the correction of the rotation amount, the associative alignment method does not directly cause a large rotation amount correction error even when one target mark TM is erroneously detected, and thus high alignment accuracy can be obtained.

In addition, in the case where the above-described pellet alignment method and the multi-point wafer alignment method are mixed, the alignment accuracy is generally lowered. However, even when the associative alignment method is mixed with any method, high alignment accuracy can be obtained.

Further, the associative alignment method can detect the target mark TM of the pattern of two adjacent DRAMs 1 by scanning one alignment beam AB, so that throughput substantially equivalent to the pellet alignment method can be obtained.

FIG. 99 shows a comparison of the alignment accuracy of each of the associative alignment method, pellet alignment method, and multi-point wafer alignment method when there is distortion or rotation in the arrangement of the pattern of the DRAM 1 of the first layer. FIG. 99 (a) shows (a) an ideal arrangement of the pattern 1 of the DRAM 1 of the first layer, (b) the arrangement distortion and rotation of the pattern 1 of the DRAM 1 of the first layer. Each of the arrays of cases is shown. In the latter pattern 1 of the DRAM 1, the X coordinates of?-? Do not coincide, and the pitches in the respective Y coordinate directions between?-? And?-? Are different. Each of, α, and γ has a rotation error. This arrangement distortion and rotation are due to the warpage generated in the semiconductor wafer 100 by repeated heat treatment.

99 (b) shows the case of aligning the pattern 2 of the DRAM 1 of the second layer when the arrangement distortion and the rotation of the pattern 1 of the DRAM 1 of the first layer occur. The comparison of each alignment method is shown. In either case, the pattern 2 of gamma of the DRAM 1 of the second layer represents a case where the target mark TM is largely wrongly detected with respect to the pattern 1 of gamma of the DRAM 1 of the first layer. The associative alignment method is calculated according to the detection of four target marks TM, and the other two alignment methods are calculated according to the detection of two target marks TM. As shown in FIG. 99 (b), when there is no correction of the rotation amount, in each of the cases where the rotation amount is corrected, the associative alignment method is higher than that of the other pellet alignment method and the multi-point wafer alignment method. Alignment precision can be obtained.

Thus, by adopting the associative alignment method, high alignment accuracy can be obtained.

Example 12

In Example 12, in the DRAM 1 of Example 1, the reliability of the transition metal embedded in the connection hole of the interlayer insulating film by the selective CVD method and the connection portion of the wiring extending over the interlayer insulating film is improved. A twelfth embodiment of the invention.

The configuration of the DRAM 1 according to the twelfth embodiment of the present invention is shown in FIG. 100 (main part sectional view).

In the DRAM 1 of the twelfth embodiment, the transition metal film 54 is embedded in each of the connection holes 51D and 51S formed in the interlayer insulating film 51, as shown in FIG. The wiring 53 extending on the interlayer insulating film 51 is connected to the film 54.

In the memory cell array 11E, the memory cell M composed of the memory cell selection MISFETQs and the stacked-layer information storage capacitor C is arranged, so that the stepped shape becomes larger than that of the peripheral circuit. Therefore, the film thickness of the region of the interlayer insulating film 51 is thinner than that of the peripheral circuit. As shown in FIGS. 100 and 101 (main cross-sectional views in a predetermined manufacturing process), the depth of the connection hole 51S formed in the region of the memory cell array 11E of the interlayer insulating film 51 is shallow. The connection hole 51D formed in the area | region of the peripheral circuit is formed deep.

As the transition metal film 54, the W film deposited by the selective CVD method, for example, is used as in the first embodiment. The wiring 52 uses an aluminum alloy film in the twelfth embodiment. In addition, the wiring 52 may be formed of a transition metal film such as a W film deposited by a sputtering method or a composite film mainly containing the same.

As shown in FIGS. 100 and 101, the transition metal film 54 has a film thickness such that the connection hole 51S having a shallow depth of the region of the memory cell array 11E is embedded. In other words, the transition metal film 54 is configured not to protrude from the connection hole 51S on the basis of the connection hole 51S having a shallow depth. In the case where the transition metal film 54 protrudes largely from the connection hole 51S, the surface of the wiring 52 in the upper portion of this portion protrudes, and as a result, the film thickness variation of the photoresist film for processing the wiring 52 The diffraction phenomenon at the time of exposure changes the size of an etching mask from a set value, and the machining precision of the wiring 52 falls. In addition, since the transition metal film 54 protruding largely from the connection hole 51S cannot cover the surface thereof with the wiring 52 in the upper layer, the transition metal film 54 is etched in the etching process for processing the wiring 52. Etched more than necessary. As shown in FIG. 100, the transition metal film 54 embedded in the connection hole 51D having a deep depth of the area of the peripheral circuit is such that the aspect ratio at the portion of the connection hole 51D does not exceed one. It is buried at the film thickness of. If the aspect ratio exceeds 1, the step coverage of the upper wiring 52 is lowered, and disconnection frequently occurs at the connection hole 51D portion of the wiring 52.

In this way, an interlayer insulating film 51 is formed on the bottom surface having the stepped shape, and the connection hole shallow in the high stepped area (the area of the memory cell array 11E) of the bottom surface of the interlayer insulating film 51 is formed. 51S), each of the deep connection holes 51D is formed in the stepped low region (the area of the peripheral circuit), and the transition metal film 54 embedded in each of the connection holes 51S and the connection holes 51D. In the DRAM 1 which extends the wiring 52 onto the interlayer insulating film 51 so as to connect to the interlayer insulating film 51, the transition metal film 54 embedded in each of the shallow connection hole 51S and the deep connection hole 51D. Is deposited by the selective CVD method, and further, the transition metal film 54 is deposited to the same thickness as the depth of the shallow connection hole 51S. With this configuration, the shallow metal connection 54 formed in each of the shallow connection hole 51S and the deep connection hole 51D is formed to have a film thickness that is about the same as the depth of the shallow connection hole 51S, and the shallow connection is achieved. Since the transition metal film 54 does not protrude from each of the hole 51S and the deep connection hole 51D, the processing accuracy of the wiring 52 can be improved and the reliability of the wiring can be improved.

Example 13

The thirteenth embodiment is the thirteenth embodiment of the present invention in which the reliability of the wiring 52 mainly composed of the transition metal film is improved in the DRAM 1 of the above-described first embodiment.

The configuration of the DRAM 1 according to the thirteenth embodiment of the present invention is shown in FIG. 102 (main part sectional view).

As shown in FIG. 102, the DRAM 1 of the thirteenth embodiment extends the wiring 52 on the interlayer insulating film 51. As shown in FIG. The wiring 52 is formed of a composite film in which the transition metal film 52B, which is substantially the same metal material, is laminated on the transition metal film 52A.

The interlayer insulating film 52 under the wiring 52 is formed of, for example, a W film deposited by a sputtering method, and is formed, for example, with a film thickness of about 89 to 120 nm. The adhesion with the interlayer insulating film (silicon oxide-based insulating film) 51 on the bottom of the lower transition metal film 52A is high. If the lower transition metal film 52A is made too thick, the lower transition metal film 52A becomes an overhang shape in the upper part of the stepped shape formed by the connection hole 51C to generate a cavity, and the step coverage of the upper transition metal film 52A. Since it becomes the cause of the lowering of, it is formed in the above-mentioned thin film thickness. In addition, the lower transition metal film 52A causes the film from the surface of the interlayer insulating film 51, as shown in FIG. 103, as the relationship between the target voltage at the time of sputtering and the stress of the film. It is deposited using a target voltage which does not occur (within stress 0 or in the allowable range in the vicinity thereof). The lower transition metal film 52A has substantially the same properties as the etching rate of the upper transition metal film 52B. The lower transition metal film 52A has a higher corrosion resistance than the TiN film or the like and a smaller work function difference with Si, so that the contact resistance value can be reduced.

The transition metal film 52B on the upper layer of the wiring 52 is formed of a W film deposited by the CVD method, and is formed with a film thickness of about 250 to 350 nm, for example. The upper transition metal film 52A is configured as a main body of the wiring 52 by reducing the substantial resistance value of the wiring 52. Since the upper transition metal film 52B is deposited by the CVD method, the step coverage at the stepped portion at the bottom is high, so that disconnection failure can be reduced, so that reliability as wiring can be improved. Since the upper transition metal film 52B is made of the same metal film material, it has high adhesiveness with the lower transition metal film 52A.

Thus, in the DRAM 1 which forms the wiring 52 with the transition metal film 52B deposited by the CVD method on the bottom interlayer insulating film 51, the bottom interlayer insulating film 51 and the wiring 52 A transition metal film 52A of substantially the same type as the transition metal film 52B deposited by the sputtering method is provided between the transition metal films 52B. With this configuration, the lower transition metal film 52A deposited by the sputtering method has high adhesiveness with each of the bottom interlayer insulating film 51 and the transition metal film 52B of the upper layer of the wiring 52, While the adhesion between the bottom interlayer insulating film 51 and the wiring 52 can be improved, the lower transition metal film 52A deposited by the sputtering method is substantially the same as the upper transition metal film 52B. Since it is formed of a kind of transition metal film, it is possible to prevent the formation of concave convexities on the processed sidewall of the wiring 52, thereby improving the processing precision of the wiring 52.

As shown in FIG. 102, when the transition metal film 52A under the wiring 52 is directly connected to the n + type semiconductor region 32 or the p + type semiconductor region 39, the transition of the lower layer is performed. The heat treatment after deposition of the metal film 52A is performed at a temperature at which W and Si do not alloy. Specifically, the heat treatment is carried out at about 600 ° C or less. In this way, by limiting the heat treatment temperature of the transition metal film 52A under the wiring 52, the increase in the resistance value of the connection portion due to the alloying reaction of W and Si described above is suppressed, and the alloy spike The phenomenon can be prevented.

Example 14

The fourteenth embodiment is the fourteenth embodiment of the present invention in which the reliability at the connection portion of each of the memory cells M, each element, and the wiring in the DRAM 1 of the above-described embodiment 1 is improved.

The structure of the DRAM 1 of Embodiment 14 of the present invention is shown in FIG. 104 (main part sectional view).

As shown in FIG. 104, the DRAM 1 of the fourteenth embodiment includes the n-type semiconductor region 29 complementarity data line DL of one n-type semiconductor region 29 of the memory cell selection MISFETQs of the memory cell M in the memory cell array 11E. The intermediate conductive film 130 is interposed between the pads 50. The intermediate conductive film 130 is partially connected to the n-type semiconductor region 29 through the connection hole 131A and the connection hole 34A formed in the interlayer insulating film 131, and the other side side spacer 31. It extends on the phase and the interlayer insulating film 131. The connection hole 34A is formed of a sidewall spacer 31 formed in the sidewall of the gate electrode 27 of the memory cell selection MISFETQs in the connection hole 131A formed in the interlayer insulating film 131. The opening size is defined by Since the connection hole 34A is formed to be self-aligning with respect to the gate electrode 27, as a result, the connection between the intermediate conductive film 130 and the n-type semiconductor region 29 is self-aligning with respect to the gate electrode 27. Is executed as That is, the n-type semiconductor region 29 of the memory cell selection MISFETQs and the complementarity data line 50 are self-aligned to the gate electrode 27 of the memory cell selection MISFETQs via the intermediate conductive film 130. have.

The intermediate conductive layer 130 is formed above the gate electrode 27 (including the word line 27) of the memory cell selection MISFETQs, and the lower electrode layer 35 of the capacitor C for information storage in a stacked structure. It is formed in a lower layer. That is, since the lower electrode layer 35 of the information storage capacitor C of the stacked structure is formed with a thick film thickness in order to increase the amount of charge accumulation, the intermediate conductive film 130 is formed of the lower electrode layer 35 in order to improve processing accuracy. It is formed in the other layer and the lower layer. The intermediate conductive film 130 is formed of, for example, a polycrystalline silicon film deposited by CVD and is formed to a thin film thickness of about 809 to 120 nm. In this polycrystalline silicon film, n type impurity which reduces resistance value is introduce | transduced.

Since the intermediate conductive layer 130 can alleviate the particularly steep step shape of the connection portion between the memory cell M and the complementary data line 50, the disconnection defect of the complementary data line 50 can be reduced.

The intermediate conductive film 130 is also formed in the device of the peripheral circuit in the same manufacturing process. Although not limited to this, in the fourteenth embodiment, an n-channel MISFETQn, especially a layout rule, is provided between the n + type semiconductor region 32 and the wiring 32 in a strict region. In general, peripheral circuits have less stringent layout rules than memory cell arrays 11E. As shown in FIG. 104, even when the wiring 52 is mounted on the insulating film 23 for inter-element isolation in the peripheral circuit region, the n + type semiconductor region 32 and the n + type semiconductor region 32 are interposed therebetween. Since the wiring 52 can be reliably connected, the area of the n + type semiconductor region 32 can be reduced, and consequently, the integration degree of the DRAM 1 can be improved, and the n-channel MISFETQn and p-channel MISFETQp of the peripheral circuit can be improved. Even when each is connected to the wiring 52 formed of a material which is likely to cause mutual diffusion of impurities such as a transition metal film, the intermediate conductive film 130 can prevent the mutual diffusion, so that the resistance value at the connection portion can be reduced. Can be.

Next, the method of forming the DRAM 1 according to the fourteenth embodiment will be briefly described using Figs. 105 and 106 (the cross sectional views of the main parts shown for each manufacturing process).

First, similarly to the method of forming the DRAM 1 of the first embodiment, each of the memory cell selection MISFETQs of the memory cells M and the n-channel MISFETQn of the peripheral circuits are formed.

Next, an interlayer insulating film 131 is deposited on the entire surface of the substrate so as to cover each of the memory cell selection MISFETQs and the n-channel MISFETQn. The interlayer insulating film 131 is deposited by a CVD method using, for example, inorganic silane gas and nitrogen oxide gas as a source gas, and is formed to a film thickness of about 40 to 60 nm using a silicon oxide film.

Next, a connection hole is formed in the interlayer insulating film 131 in each of the n-type semiconductor region 29 of one of the memory cell selection MISFETQs of the memory cell M and the n + -type semiconductor region 32 of the predetermined n-channel MISFETQn. 131A is formed and the connection hole 34A is formed.

Next, as shown in FIG. 105, an intermediate conductive film 130 connected to each of the n-type semiconductor region 29 and the n + -type semiconductor region 32 is formed through the connection holes 131A and 34A. do.

Next, as shown in FIG. 106, an interlayer insulating film 33 is formed over the entire substrate including the intermediate conductive film 130. Next, as shown in FIG. Then, the DRAM 1 of the 14th embodiment is completed by performing the same process as the method for forming the DRAM 1 of the first embodiment, such as the information storage capacitor C and the p-channel MISFETQp of the stacked structure. do.

As described above, the MISFETQs for selecting memory cells, the lower electrode layer 35, the dielectric film 36, and the upper electrode layer 37 are sequentially stacked at the intersection of the complementarity data line 50 and the word line 27. In a DRAM 1 for arranging memory cells M formed of a series circuit of an information storage capacitor C, between the complementary data line 50 and one n-type semiconductor region 29 of the memory cell selection MISFETQs. A portion of the n-type semiconductor region 29 is self-aligned, and another portion is drawn out on the gate electrode 27 of the memory cell selection MISFETQs and at the same time the information storage capacitor of the stacked structure. An interlayer insulating film 130 formed on a layer different from that of the lower electrode layer 35 of C is provided. Since the intermediate conductive film 130 is interposed by this structure, the mask fitting margin in the manufacturing process between the n-type semiconductor region 29 and the complementary data line 50 of one of the memory cell selection MISFETQs is determined. As a result, the area of memory cell M can be reduced to improve the degree of integration, and at the same time, the isolation dimension between the intermediate conductive film 130 and the lower electrode layer 35 of the capacitor C for information storage in a stacked structure is lost. Since the area of the lower electrode layer 35 can be increased independently of the film 130, the charge accumulation amount of the information storage capacitor C of the stacked structure can be increased to reduce the area of the memory cell M to improve the degree of integration.

In addition, the intermediate conductive film 130 has a thinner film thickness than the film thickness of the lower electrode layer 35 of the information storage capacitor C of the stacked structure. With this structure, the information storage capacitor C of the stacked structure can secure the area in the height direction by increasing the film thickness of the lower electrode layer 35, so that the charge accumulation amount is increased to reduce the memory cell M area to improve the integration degree. In addition, since the intermediate conductive film 130 has a thin film thickness, the processing can be simplified.

An intermediate conductive film formed of the same conductive layer as the intermediate conductive film 130 provided in the memory cell M is formed between the n + type semiconductor region 32 of the n-channel MISFETQn constituting the peripheral circuit and the wiring 52 connected thereto. Provide 130. With this configuration, the intermediate conductive film 130 of the peripheral circuit can be formed by forming the intermediate conductive film 130 formed in the memory cell M of the DRAM 1, thus reducing the number of manufacturing steps of the DRAM 1. Can be reduced.

As mentioned above, although the invention made by the present inventors was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

For example, the present invention can be applied to a semiconductor integrated circuit device using a DRAM such as a microcomputer (one chip microcomputer) as a unit.

The present invention is not limited to the DRAM, but can be applied to semiconductor integrated circuit devices having other memory functions such as SRAM and ROM.

Moreover, this invention is applicable to multilayer wiring techniques, such as a printed wiring board.

The effects obtained by the representative of the inventions disclosed herein will be briefly described as follows.

(1) The degree of integration of a semiconductor integrated circuit device having a memory function can be improved.

(2) The electrical reliability of the semiconductor integrated circuit device can be improved.

(3) The soft error withstand voltage of the semiconductor integrated circuit device can be improved.

(4) The number of manufacturing steps of the semiconductor integrated circuit device can be reduced.

(5) The processing accuracy in manufacturing the semiconductor integrated circuit device can be improved.

(6) The driving ability of the semiconductor element of the semiconductor integrated circuit device can be improved.

(7) Manufacturing efficiency in manufacturing the semiconductor integrated circuit device can be improved.

(8) The operation speed of the semiconductor integrated circuit device can be increased.

(9) The disconnection of the wiring of the semiconductor integrated circuit device can be prevented.

(10) The moisture resistance of the semiconductor integrated circuit device can be improved.

(11) In a semiconductor integrated circuit device having a redundancy fuse, the formation process of the redundancy fuse can be simplified.

(12) In the semiconductor integrated circuit device, the film quality of the film used therein can be improved.

(13) The manufacturing apparatus of said (12) can be provided.

Claims (15)

A plurality of wirings regularly arranged on the semiconductor substrate at predetermined intervals and having a predetermined film thickness, the first insulating film formed on the wiring by the CVD method, and the plasma insulating film on the first insulating film. In a semiconductor integrated circuit device having a second insulating film made of a formed silicon nitride film, in a region where the ratio of the wiring film thickness to the wiring interval is one or more, the first insulating film has a film thickness of 1/2 or more of the interval of the wiring. And wherein the wiring is the uppermost wiring on the semiconductor substrate. The semiconductor integrated circuit device according to claim 1, wherein the first insulating film is a film formed of a tetraethoxy silane as a source gas. The memory cell selecting MISFET formed on the semiconductor substrate, the information storage capacitor formed on top of the memory cell selecting MISFET, and the memory cell selecting MISFET. A plurality of first word lines electrically connected to a MISFET, regularly arranged at predetermined intervals on the semiconductor substrate, regularly arranged at predetermined intervals on the first word lines via an insulating film, and And a plurality of second word lines extending in the same direction as the word lines, and electrically connected to the first word lines, wherein the plurality of wirings are the second word lines. The semiconductor integrated circuit device according to claim 1, wherein the wiring includes a first metal layer containing a high melting point metal and a second metal layer made of aluminum. The semiconductor integrated circuit device according to claim 4, wherein the first metal layer is a titanium nitride layer. A plurality of wirings disposed in the first and second portions on the main surface of the semiconductor substrate and having a predetermined thickness; a first insulating film formed between the wirings and the wirings in the first and second portions; A semiconductor integrated circuit device having a second insulating film formed on the first insulating film in first and second portions, wherein the wiring has a first spacing and a first aspect ratio in the first portion. Having a second spacing and a second aspect ratio in the second portion and being arranged in parallel with each other, wherein the second spacing is greater than the first spacing and the first aspect The ratio is larger than 1, the second aspect ratio is smaller than 1, and the thickness of the first insulating film corresponds to 1/2 or more of the first interval in the first portion, and the second portion. It is equivalent to 1/2 or less of the second interval in The semiconductor integrated circuit device. 7. The semiconductor integrated circuit device according to claim 6, wherein the wiring is mainly made of aluminum and is the wiring of the uppermost layer on the semiconductor substrate. 7. The semiconductor integrated circuit device according to claim 6, wherein the wiring includes a first metal layer containing a high melting point metal and a second metal layer made of aluminum. The semiconductor integrated circuit device according to claim 8, wherein the first metal layer is a titanium nitride layer. 7. The semiconductor integrated circuit device according to claim 6, wherein said second insulating film is a silicon nitride film. A plurality of wirings disposed in the first and second portions on the main surface of the semiconductor substrate and having a predetermined thickness; a first insulating film formed between the wirings and the wirings in the first and second portions; A semiconductor integrated circuit device having a second insulating film formed on the first insulating film in first and second portions, wherein the wirings are arranged in parallel with each other at a first interval in the first portion. And a second interval in the second portion and arranged in parallel with each other, wherein the second interval is greater than the first interval, and the film thickness of the first insulating film is defined in the first portion. The semiconductor integrated circuit device which corresponds to 1/2 or more of the interval of 1, and corresponds to 1/2 or less of the 2nd interval in the said 2nd part. 12. The semiconductor integrated circuit device according to claim 11, wherein the wiring is mainly composed of aluminum and is wiring at the uppermost layer on the semiconductor substrate. 12. The semiconductor integrated circuit device according to claim 11, wherein the wiring has a laminated structure including a first metal layer containing a high melting point metal and a second metal layer made of aluminum. The semiconductor integrated circuit device according to claim 13, wherein the first metal layer is a titanium nitride layer. 12. The semiconductor integrated circuit device according to claim 11, wherein said second insulating film is a silicon nitride film.