KR100188099B1 - Fabrication method of thin film transistor panel for lcd - Google Patents
Fabrication method of thin film transistor panel for lcd Download PDFInfo
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- KR100188099B1 KR100188099B1 KR1019950035796A KR19950035796A KR100188099B1 KR 100188099 B1 KR100188099 B1 KR 100188099B1 KR 1019950035796 A KR1019950035796 A KR 1019950035796A KR 19950035796 A KR19950035796 A KR 19950035796A KR 100188099 B1 KR100188099 B1 KR 100188099B1
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- 238000000034 method Methods 0.000 title claims description 21
- 239000010409 thin film Substances 0.000 title abstract description 14
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000002425 crystallisation Methods 0.000 claims description 2
- 230000008025 crystallization Effects 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 230000001678 irradiating effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 36
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 12
- 238000009413 insulation Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
본 발명은 레이저를 이용하여 비정질 실리콘을 다결정 실리콘으로 변화시키면서 동시에 산화막을 형성할 수 있는 액정 표시 장치용 박막 트랜지스터 기판의 제조 방법에 관한 것이다. 기판 위에 비정질 실리콘막을 형성하는 단계, 상기 비정질 실리콘막에 레이저를 쏘아 다결정 실리콘막으로 변화시키는 동시에 상기 다결정 실리콘막 위에 산화막을 형성하는 단계를 포함하는 제조 공정 순서를 갖는다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor substrate for a liquid crystal display device capable of simultaneously forming an oxide film while changing amorphous silicon into polycrystalline silicon using a laser. Forming an amorphous silicon film on the substrate, and forming an oxide film on the polycrystalline silicon film while simultaneously lasering the amorphous silicon film into a polycrystalline silicon film.
Description
제1도는 본 발명의 실시예에 따른 액정 표시 장치용 박막 트랜지스터 기판을 나타낸 단면도이고,1 is a cross-sectional view illustrating a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.
제2a∼d도는 본 발명의 실시예에 따른 액정 표시 장치용 박막 트랜지스터 기판의 제조 공정 순서를 나타낸 단면도이다.2A to 2D are cross-sectional views illustrating a manufacturing process procedure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.
본 발명은 액정 표시 장치용 박막 트랜지스터 기판의 제조 방법에 관한 것으로서, 더욱 상세히 말하자면 레이저를 이용하여 비정질 실리콘을 다결정 실리콘으로 변화시키면서 동시에 산화막을 형성할 수 있는 액정 표시 장치용 박막 트랜지스터 기판의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor substrate for a liquid crystal display device capable of simultaneously forming an oxide film while converting amorphous silicon into polycrystalline silicon using a laser. It is about.
일반적으로 액정 표시 장치는, 박막 트랜지스터 및 화소 전극이 형성되어 있는 다수의 화소 단위가 행렬의 형태로 형성되어 있으며, 게이트 라인 및 데이타 라인이 각각 화소 행과 화소 열을 따라 형성되어 있는 박막 트랜지스터 기판, 공통 전극이 형성되어 있는 컬러 필터 기판, 그리고 그 사이에 봉입되어 있는 액정 물질을 포함하고 있다.In general, a liquid crystal display includes a thin film transistor substrate in which a plurality of pixel units in which a thin film transistor and a pixel electrode are formed are formed in a matrix form, and a gate line and a data line are formed along a pixel row and a pixel column, respectively. It includes a color filter substrate on which a common electrode is formed, and a liquid crystal material enclosed therebetween.
이때, 상기 박막 트랜지스터 기판의 게이트 전극은 상기 게이트 라인을 통해 게이트 구동 드라이브로부터 게이트 구동 신호를 전달받아 반도체층에 채널을 형성시키고, 이에 따라 데이타 구동 드라이브로부터의 데이타 신호가 상기 데이타 라인을 통해 소스 전극에 전달되고, 반도체층과 드레인 전극을 거쳐 화소 전극에 전달된다.In this case, the gate electrode of the thin film transistor substrate receives a gate driving signal from a gate driving drive through the gate line to form a channel in the semiconductor layer, and thus a data signal from the data driving drive is a source electrode through the data line. Is transferred to the pixel electrode via the semiconductor layer and the drain electrode.
이와 같은 액정 표시 장치는 액티브 영역으로 사용하는 채널층을 다결정 실리콘을 사용하여 형성할 수 있는데, 먼저 비정질 실리콘을 적층한 후 다결정 실리콘으로 변화시킬 수 있다.In such a liquid crystal display, a channel layer used as an active region may be formed using polycrystalline silicon. First, amorphous silicon may be laminated and then changed into polycrystalline silicon.
상기 다결정 실리콘막 상부에는 절연막을 형성하는데 이 절연막의 형성 방법은 PECVD 방식과 APCVD방식 그리고 ECRCVD등을 일반적으로 사용한다. 이와 같은 CVD방식은 저온에서 박막 트랜지스터를 형성할 수 있는 장점이 있으나, 액티브층인 다결정 실리콘층과의 계면 상태가 좋지 않다. 즉, 산화막 형성이 산소 원자의 확산에 의해 이루어진 계면 상태가 열산화막에 의한 절연막에 비해 CVD 산화막에 의한 절연막은 원자 결함을 가지기 때문에 계면 상태가 좋지 않은 문제점이 있다.An insulating film is formed on the polycrystalline silicon film, and a method of forming the insulating film generally uses a PECVD method, an APCVD method, and an ECRCVD method. Such a CVD method has the advantage of forming a thin film transistor at a low temperature, but the interface state with the active layer polycrystalline silicon layer is not good. That is, the interface state in which the oxide film is formed by diffusion of oxygen atoms has a problem in that the interface state is not good because the insulating film by the CVD oxide film has atomic defects as compared with the insulating film by the thermal oxide film.
그러므로 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로 저온 공정으로 비정질 실리콘을 다결정 실리콘으로 변화시킬 수 있으며 이 비정질 실리콘막 위에 동시에 절연막을 형성할 수 있는 액정 표시 장치용 박막 트랜지스터 기판의 제조 방법을 제공하기 위한 것이다.Therefore, the present invention is to solve the above-mentioned problems, and to manufacture a thin film transistor substrate for a liquid crystal display device capable of changing amorphous silicon into polycrystalline silicon in a low temperature process and simultaneously forming an insulating film on the amorphous silicon film. It is to provide.
이러한 목적을 달성하기 위한 본 발명의 액정 표시 장치용 박막 트랜지스터 기판의 제조 방법은, 기판 위에 비정질 실리콘막을 형성하는 단계, 상기 비정질 실리콘막에 레이저를 쏘아 다결정 실리콘막으로 변화시키는 동시에 상기 다결정 실리콘막 위에 산화막을 형성하는 단계를 포함한다.A method of manufacturing a thin film transistor substrate for a liquid crystal display device according to the present invention for achieving the above object comprises the steps of forming an amorphous silicon film on a substrate, by firing a laser on the amorphous silicon film to change to a polycrystalline silicon film and on the polycrystalline silicon film Forming an oxide film.
절연 특성을 향상시키기 위해 상기 산화막 위에 CVD 방법으로 보조 산화막을 형성하는 단계를 더 포함할 수 있다.The method may further include forming an auxiliary oxide layer on the oxide layer by a CVD method to improve insulation characteristics.
첨부한 도면을 참고로 하여, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 본 발명의 실시예를 상세하게 설명한다.With reference to the accompanying drawings, it will be described in detail an embodiment of the present invention to be easily carried out by those skilled in the art.
제1도 본 발명의 실시예에 따른 액정 표시 장용 박막 트랜지스터 기판을 나타낸 단면도이고, 제2a∼e도는 본 발명의 실시예에 따른 액정 표시 장치용 박막 트랜지스터 기판의 제조 공정 순서를 나타낸 단면도이다.1 is a cross-sectional view showing a liquid crystal display thin film transistor substrate according to an embodiment of the present invention, Figures 2a to e is a cross-sectional view showing a manufacturing process procedure of a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention.
먼저, 제2a도에 도시한 바와 같이, 기판(1) 위에 비정질 실리콘막(2)을 형성한다.First, as shown in FIG. 2A, an amorphous silicon film 2 is formed on the substrate 1.
이때 PECVD 또는 LPCVD 방법을 사용하고 그 두께는 400Å 내지 600Å 정도로 형성한다.At this time, the PECVD or LPCVD method is used and the thickness is formed to about 400 kPa to 600 kPa.
다음, 제2b도에 도시한 바와 같이, 상기 비정질 실리콘막(2)에 레이저(4)를 쏜다.Next, as shown in FIG. 2B, the laser 4 is directed to the amorphous silicon film 2.
이때 엑시머 레이저를 사용하고, 레이저 에너지는 200mJ/cm2으로 바람직하게는 300mJ/cm2의 크기로 한다.At this time, an excimer laser is used, and the laser energy is 200 mJ / cm 2 and preferably 300 mJ / cm 2 .
레이저에 의해 상기 비정질 실리콘막(2)은 순간적으로 용융되었다가 식으면서 결정화가 시작되면, 150mJ/cm2내지 250mJ/cm2바람직하게로는 200mJ/cm2정도로 레이저의 에너지를 낮추어 조사한다. 이때 분위기는 수증기 또는 02로 한다. 이 과정에서 동시에 제2c도에 도시한 바와 같이, 상기 다결정 실리콘막(3) 표면에는 수백Å의 산화막(6)이 형성된다. 이 과정에서, 다결정 실리콘막(3)의 표면 거칠기가 현저하게 줄어들 뿐 아니라, 외부 불순물의 영향을 받지 않기 때문에 이 산화막(6)은 CVD 방법에 의해 형성된 CVD 산화막에 비해 우수한 계면 특성을 갖는다. 따라서 누설 전류가 억제되고 브레이크 다운 현상을 억제한다.When the amorphous silicon film 2 is instantaneously melted and cooled by a laser and crystallization starts, cooling is performed by lowering the energy of the laser to about 150 mJ / cm 2 to 250 mJ / cm 2, preferably 200 mJ / cm 2 . At this time, the atmosphere is water vapor or 0 2 . In this process, as shown in FIG. 2C at the same time, several hundreds of oxide oxide films 6 are formed on the surface of the polycrystalline silicon film 3. In this process, not only the surface roughness of the polycrystalline silicon film 3 is significantly reduced, but also is not affected by external impurities, the oxide film 6 has superior interfacial properties as compared to the CVD oxide film formed by the CVD method. Therefore, leakage current is suppressed and breakdown phenomenon is suppressed.
다음, 제2d도에 도시한 바와 같이, 상기 산화막(6) 위에 CVD 방법으로 보조산화막(7)을 더 형성하여 절연막의 신뢰도를 높인다. 이때 상기 레이저에 의해 형성된 산화막(6)과 상기 CVD 방법에 의해 형성된 보조 산화막(7)의 두께의 합은 1000Å 이하가 바람직하다.Next, as shown in FIG. 2D, the auxiliary oxide film 7 is further formed on the oxide film 6 by the CVD method to increase the reliability of the insulating film. At this time, the sum of the thicknesses of the oxide film 6 formed by the laser and the auxiliary oxide film 7 formed by the CVD method is preferably 1000 Pa or less.
그러므로 본 발명은 400℃이하의 저온 공정이 가능하여 유리 기판을 사용할 수 있어 제조 비용을 낮출 수 있고, 절연막과 채널층과의 접합 계면 상태를 양호하게 얻을 수 있어 절연 효과를 증대시킬 수 있다.Therefore, in the present invention, a low temperature process of 400 ° C. or lower is possible, and thus, a glass substrate can be used, and thus manufacturing cost can be lowered, and the bonding interface state between the insulating film and the channel layer can be obtained satisfactorily and the insulation effect can be increased.
Claims (7)
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| KR1019950035796A KR100188099B1 (en) | 1995-10-17 | 1995-10-17 | Fabrication method of thin film transistor panel for lcd |
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| KR1019950035796A KR100188099B1 (en) | 1995-10-17 | 1995-10-17 | Fabrication method of thin film transistor panel for lcd |
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| KR970024246A KR970024246A (en) | 1997-05-30 |
| KR100188099B1 true KR100188099B1 (en) | 1999-07-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100623251B1 (en) | 2004-02-19 | 2006-09-18 | 삼성에스디아이 주식회사 | Method of fabricating a polysilicon thin film and thin film transistor using the polysilicon thin film fabricated by the same method |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3658213B2 (en) * | 1998-11-19 | 2005-06-08 | 富士通株式会社 | Manufacturing method of semiconductor device |
| JP4101409B2 (en) * | 1999-08-19 | 2008-06-18 | シャープ株式会社 | Manufacturing method of semiconductor device |
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1995
- 1995-10-17 KR KR1019950035796A patent/KR100188099B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100623251B1 (en) | 2004-02-19 | 2006-09-18 | 삼성에스디아이 주식회사 | Method of fabricating a polysilicon thin film and thin film transistor using the polysilicon thin film fabricated by the same method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970024246A (en) | 1997-05-30 |
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