KR0183176B1 - Logic decoding circuit of ppm communication system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for logic decoding in a PPM communication method, comprising: a first shift register unit for digitally decoding a preparation time and a start time that can be designated in a PPM communication; and a signal output from the first shift register unit. Is a low signal, the ready detection unit for outputting an operation signal, the start detection unit for detecting a data transmission start signal in the PPM communication method, the second shift register unit, and the signals output from the second shift register unit in the PPM communication method. A digital logic converter converts a digital logic high or low signal according to a specified signal length, and a digital logic converter using a shift register.

Description

Logic decoding circuit in PPM communication method

1 is a conceptual diagram of a data input signal in a PPM communication method.

2 is a logic decoding circuit for PPM communication according to the present invention for the data input signal shown in FIG.

(A) and (b) of FIG. 3 are exemplary views of decoding timing of the PPM signal according to FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for decoding logic in a PPM communication scheme, and more particularly, to smoothly convert a PPM communication scheme to digital logic.

In general, PPM (Pulse Position Modulation) communication sends a poll from the system CPU, and the receiver interprets the poll and sends it back to the CPU to send and receive necessary information to facilitate communication between the CPU and the receiver. It is.

The concept of PPM communication in the PPM communication method as described above is illustrated in the attached FIG. 1. Briefly, the PPM communication method is a low section of a signal corresponding to data to be transmitted. By distinguishing the high and low of digital logic according to the long and short of, it is applied to the data bit detection time of FIG.

In the above section, the length of time that the signal is high is the same as any data (actually 200-300 μsec), and the long and short length of the low interval of the signal is present. When the data is high, the length of the low interval is 500-1300 μsec. If the data is low, the length of the row section is set to 100-400 µsec.

Therefore, the procedure of logically decoding the data must be preceded so that this PPM communication can be incorporated into digital logic.

To actually implement this, a preparation time interval and a start detection time interval are required as shown in FIG.

In this case, the preparation time interval corresponds to a case in which the length of the time when the signal is low is 1750 μsec or more, and the start detection time interval is 1300-2000 μsec in length of the time when the signal is high. There was no.

SUMMARY OF THE INVENTION An object of the present invention for meeting the above needs is to provide a logic decoding circuit in a PPM communication method for smoothly converting a signal transmitted in a PPM communication method into digital logic.

A feature of the present invention for achieving the above object is a logic decoding circuit in a PPM communication method, the first shift register unit for digitally decoding the preparation time and start detection time input to the PPM communication method, A preparation detector for outputting a signal to prohibit operation of the entire circuit in the preparation time of the input signal by operating the remaining parts when the signals output from each stage of the one shift register are all low signals; A start detection unit which is operated according to a signal output from the first detection register and detects as a signal for starting data transmission when a high signal is input for more than a predetermined time from the signal output from the first shift register unit, and the first stage of the first shift register unit. The system-synchronized signal and the ready detector and the start of the flip-flop A second shift register part controlled by a signal outputted from the output part to shift and output the signal input by the PPM communication method, and operated by receiving the respective output signals of the preparation detection part and the start detection part, and a signal of the PPM communication method; Digital logic for converting signals output from the second shift register unit 400 to digital logic signals according to the length of the signal specified in the PPM communication method by a signal controlling to decode logic only for input And a parallel data converter configured to receive and output the output signals of the preparation detector and the start detector, and convert the digital logic signals outputted from the digital logic converter by the adst signals in parallel as necessary. do.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a logic decoding circuit diagram for PPM communication according to the present invention for the data input signal shown in FIG.

The configuration is largely parallel to the first shift register unit 100, the preparation detector 200, the start detector 300, the second shift register unit 400, the digital logic converter 500, and parallelism. It consists of a data converter 600.

Referring to the configuration as described above in more detail with reference to FIG. 1 as follows.

The number of D-flip flops is determined by the first shift register section 10 by the length of the preparation time and the start detection time that can be specified in the PPM communication. The first shift register unit 100 performs a function of a register and digitally decodes a preparation time and a start detection time from a data signal Data In that is transmitted and input in a PPM communication method. In the first shift register unit 100, the D-flip flops are serially connected in multiple stages 1F _{1 to} 1F _m , and are respectively connected to the main clock Mclk and operate according to the clock.

Here, the first shift register 400 uses the shift register to be processed even in a time zone corresponding to the preparation time, that is, no event occurs, thereby filtering out noise generated in the system to prevent malfunction. It plays a role. In addition, the time for the start detection time is also a process for discriminating against the noise, which can also refer to the resulting signal after passing through the shift register.

Next, in the preparation detection unit 200, when the signals output from the respective D-flip flops of the first shift register unit 100 are all low signals, all of the flip-flops other than the first shift register unit 100 are removed. By resetting, it acts to prohibit the operation of the whole circuit in the preparation time section. The preparation detector 200 includes an OR gate 210 for ORing the signals output from the respective D-flip flops of the first shift register unit 100, and the signals output from the OR gate 210. And the first AND gate 220 receiving and resetting the reset signal clr.

In addition, the start detector 300 detects a signal for starting data transmission in the PPM communication scheme, and includes a second end gate for ANDing the signals output from the respective D-flip flops of the first shift register unit 100. And a D flip-flop 320 that is reset according to the signal output from the preparation detector 200 and receives a signal output from the second ant gate 310 and outputs a start signal. Here, PPM communication is started if a high signal comes in for more than a predetermined time. That is, it is possible to control that the high signal for less than the specified time is treated as noise so as not to operate normally.

The second shift register unit 400 is controlled by a signal synchronized with the system in the first flip-flop of the first shift register unit 100 and a signal output from the preparation detector 200 and the start detector 300 to control the PPM. It outputs by shifting the input signal by communication method. This includes a first inverter 410 for inverting the main clock Mclk, a third end gate 420 controlled by a result of the start detector 300 to control output of data by a PPM communication method, In the flip-flop (PF) and the flip-flop (PF) for outputting the output of the flip-flop (1F ₁ ) of the first stage of the first shift register unit 100 in accordance with the signal output from the first inverter (410) Composed of D-flip flops 2F ₁ , ..., 2F _n connected in series to the flip-flop PF for outputting the output data according to the control signal output from the third end gate 420. It is.

Next, the digital logic converter 500 converts the signals passed through the second shift register unit 400 into digital logic high or low signals according to the length of a signal specified by the PPM communication method. This is received by the PPM communication method by receiving a signal (hereinafter, 'adst') that distinguishes the input unit from the output unit in the PPM communication method and each output of the start detector 300 and the first stage D-flip flop 1F ₁ . The fourth end gate 510 controls to be converted into digital logic in accordance with the signal itself (data input signal of FIG. 1), and performs a negative logic on the signals output from the second stage of the second shift register unit 400. FIG. A negative logic (NOR) gate 520 and a flip-flop DF for outputting a negative logic result under the control of the fourth ant gate 510. Here, the logic signal is decoded only for the input of the signal of the PPM communication method by the adst signal.

The parallel data converter 600 is a shift register and is a part for parallelizing the digital logic passed through the digital logic converter 500. The second inverter 610 for delaying the output of the first stage D-flip flop 1F ₁ to secure an operation free time, the output of the second inverter, the output of the start detector 300, and the adst. The fifth end gate 620 for multiplying the signal and the number of input signals output from the digital logic converter 500 are parallel-converted as necessary by the adst signal (P0 ₁ , ..., P0 _{y- 2} , P0 _y-1 , P _y ) consists of D-flip flops (3F ₁ , ..., 3F _y ) connected in series in multiple stages.

Referring to the operation of the present invention by such a configuration as follows.

In a second separate decoding circuit, a main clock (Mclk), the speaking period 30.52μsec, the first shift D- flip-flop 56 in the register unit 100, one ₍₁ 1F -1F _56), each flip-flop, even when the shifting hayeoteul When all 56 Q values of are low, the condition corresponding to the preparation time of FIG. 1 is satisfied.

Therefore, the flip-flop SF and the second shift register of the start detection unit 300 when the 56 values of the OR gate 210 of the preparation detection unit 200 become low (the operation result value of ORm) become low. Flip-flops 2F ₁ ,..., 2F _n of unit 400, flip-flops DF of digital logic converter 500, and flip-flops 3F ₁ ,... Of parallel data converter 600. , 3F _y ) to prepare for processing signals after the preparation time in FIG.

In order to cause all of these (2F, 3F, SF, DF flip-flops) to be reset, the operation result of the OR gate 210 and the clear (clr) signal are logically multiplied by the first end gate 220 to perform a second operation. a flip-flop of the shift register unit _{(400) (2F 1 -2F x} ), parallel data flip-flop of the conversion unit _{(600) (3F 1 -3F y} ), the flip-flop (SF), the digital logic of the start detection section 300 is converted The flip-flop DF of the unit 500 is applied to all of them.

When the description with respect to the second-and-operation of the gate 310 of the start detection section 300, a result value of the first shift register 100, the flip-flop 1F ₁ -2F _n n of all of the flip-flop to a high Ramen (actually, the condition satisfying this by applying Mclk 30.52μsec to 1300μsec or more is used when 43 1F flip-flops are used.) This is interpreted as the section corresponding to the start detection time of FIG.

In this case, this condition is satisfied by keeping the result of the flip-flop (SF) 320 in the start detector 300 high until the result of the or gate 210 becomes low and resets the flip-flop 320. only when (a flip-flop (when the result of the SF) to be held high), flip-flop of the flip-flop of the second shift register _{(400) (2F 1 -2F x} ), parallel data conversion unit (600) (3F ₁ -3F _y ), to perform the function of the flip-flop (DF) 530 of the digital logic converter 500.

This prepares the environment for logic decoding of data performed at the data bit detection time of FIG.

Now, a description of the operation of the flip-flop of the second shift register _{(400) (2F 1 -2F x} ).

With the above preparation environment in place, the data input is filtered once through the flip-flop 1F ₁ of the first shift register unit 10 (the setup or hold vibration protection function is performed). Through the flip-flop (PF) of the shift register unit 400 is allowed to reserve the time of 1/2 the main clock by the first inverter 410 (as a result of the PF flip-flop) and the result is the second to pass through the flip-flop (2F ₁ -2F _x) of the shift register 400.

In this way the flip flops (2F _{x 1} -2F) result is negative logical sum (NOR) x it is, all rows in the NOR gate 520 changes the digital logic portion 500 of the line number that will make the result as a high .

In order to process this operation I is followed by the start detecting one degree achieved using a clock of the third AND gate 420, the flip-flop to a rough signal of the second shift register _{(400) (2F 1 -2F x} ) do.

In this case, when the 30.52 μsec main clock is applied, this flip-flop is required to make the low signal length of the data bit detection time interval of the data input of FIG. 1 longer than 457.8 μsec (that is, to logically decode high). is when the number of the (2F ₁ -2F _x) 15 parts.

This way, on the one hand, a time of 100-400μsec can always be decoded into a logic low.

This is the result of the NOR gate 520, and the condition that keeps the rising edge of the signal coming into the data input and the flip-flop (SF) 320 high (this is also the case that the start detection of FIG. And the result of the logical multiplication by the fourth end gate 510 to clock the flip-flop 530 of the digital logic converter 500 to the next column.

The operation of this result is geotinde a decode incoming data bits into data detection time period of the input data, in a place that converts them to the data flip-flop byeolryeol of parallel data conversion unit _{(600) (3F 1 -3F y} ) It is done by

In order to more easily convert the data into parallel data, the signal input through the data input passes through the second inverter 610, and also the result of the flip-flop (SF) 320 of the start detector 300 and the adst signal. the fifth aND gate 620, the flip-flop by using a logical product signal by multiplying logic (3F -3F _{y 1)} the clock by a second-degree y outputs _{(P0 1, ..., P0 y} ) ranging from You will get in turn.

Here, the y data is used as input data to the receiving part of the PPM communication. The signals coming after the y data of the PPM communication are transferred to the CPU as many times as necessary according to their falling edges. Since these y data input signals are no longer data for input of the receiver, no further logic decoding procedure is required for the subsequent signals.

Therefore, for signals coming after y of the bit detection time of the data input of FIG. 1, the adst signal (which is high until y data is input and low after that) Keep until (Poll) comes in.

When the start detection time of the next pole is detected, the adst signal becomes high and then remains high until y data is input.) The fourth end gate 510 and the fifth end gate By 620 multiplying, the logic decoding function is prevented.

That is, referring to FIG. 3 attached to an example in which a signal of the PPM method is changed to digital logic, a circuit in which data input (see (a) in FIG. 3) of the PPM method is shown in FIG. The decoded result should be as shown in (b) of FIG.

Since the section '2' is a low section of the data input signal (PPM type signal), the section should be decoded to digital logic high. The section '3' and '4' should be a section of the data input signal (third section). Since the row section of FIG. (A) is short, it must be decoded into a digital logic row.

As a result, the low intervals of reference numerals '5' and '6' are long and should be decoded to digital logic high. The low intervals of reference numeral '7' are to be decoded to digital logic low. Since the 8 'low section is long, it must be decoded with digital logic high.

In other words, the PPM communication method is a communication method that expresses high and low in accordance with the long and short of the low interval in the expression of one bit in the expression of the data input signal.

Here, the length of the high section of the data input signal is made constant.

However, the section '1' indicates a start bit.

Therefore, the result of the logic decoding of the above case by the present invention is expressed as follows.

This representation shows that on the falling edge of the data input, the result of the digital logic by the decoding procedure according to the present invention appears.

In other words, the values of the digital logic desired to be decoded in the interval '2' to '8' are expressed in order of H (igh), L (ow), L, H, H, L, and H. The values are decoded at the end of the timing chart in the order of (i), (h), (g), (f), (e), (d), and (c) shown in b).

Here is an example of _seven flip-flops, where (i) is the Q signal of the 3F ₇ flip-flop, (h) is the Q signal of the 3F ₆ flip-flop, (g) is the Q signal of the 3F ₅ flip-flop, and (f) Q signal of a 3F ₄ flip-flop, (e) Q signal of a 3F ₃ flip-flop, (d) Q signal of a 3F ₂ flip-flop, and (c) Q signal of a 3F ₁ flip-flop. In addition, (a) is a Q signal of the DF flip-flop 530 of the digital logic converter 500, (b) is a D signal of the DF flip-flop.

The effect of the present invention operating as described above is to enable the grafting with digital logic in the system adopting the PPM communication method, it can be applied when the decoding is required in other systems to adopt the above applications. It is to give.

Claims (1)

Both the first shift register unit 100 for digitally decoding the preparation time and the start detection time input by the PPM communication method, and the signals output from the respective stages of the first shift register unit 100 are all low. When the signal is a signal, by operating the remaining parts of the input signal ready signal output section for prohibiting the operation of the entire circuit in the preparation time zone of the input signal, and is operated according to the signal output from the preparation detection unit 200 When the high signal comes from the signal output from the 1 shift register unit 100 for a predetermined time or more, the start detection unit 300 which detects as a signal for starting data transmission, and the first stage of the first shift register unit 100. It is controlled by the signal synchronized with the system in the flip-flop and the signals output from the ready detector 200 and the start detector 300 in the PPM communication method. A second shift register unit 400 for shifting and outputting the output signal and a signal for controlling the logic decoding only for an input among the signals of the PPM communication method by operating the output signals of the preparation detector and the start detector. A digital logic converter 500 for converting the signals output from the second shift register unit 400 into digital logic signals according to the length of the signal specified in the PPM communication method, and the preparation detector and the start detector. PPM communication comprising a parallel data converter 600 for receiving and outputting each of the output signals and converting the digital logic signals output from the digital logic converter 500 in parallel by the adst signal as necessary. Logic decoding circuit in the scheme.