KR0182132B1 - Fa coder signal detecting method and apparatus - Google Patents

Abstract

The present invention relates to a signal detection method of a FA coder and a signal detector of a FA coder, and forms one code in a frame unit to form a start signal with a predetermined number of bits having a high pulse, and a Manchester code. The data signal is composed of a predetermined number of bits, and has a function of detecting a data signal indicating the state of the servo motor from among the signals of the FA coder for encoding information on the operation state of the servo motor. In the present invention, the start signal is detected among the signals output from the FA coder, and when the start signal is detected, a clock signal synchronized with the frequency of the data signal among the FA signal generated following the start signal is generated. Signal detection method of FA coder which outputs the data signal serially until counting the number of inflow bits of the data signal according to the signal reaches the number of bits of the data signal and FA implementing the same Provide a signal detector.

Description

Signal detection method of FA coder and signal detector of FA coder

1 is an explanatory diagram for each bit constituting a signal of a TS5643N40 FA-coder.

2 is an explanatory diagram of bits in a Manchester code.

3 is a detailed view of the start signal, address signal, and stop bit portion of FIG.

4 is an explanatory diagram of a signal detector of a FA coder according to the present invention.

5 is a view comparing input signals to the signal detector according to the present invention and pulses of respective parts in the signal detector over time.

The present invention relates to a signal detection method of a FA coder and a signal detector of a FA coder.

In order to control the servo motor, accurate information about the electric angle, rotation speed, torque, etc. of the rotor in the operation state of the servo motor is required. In order to obtain this information, the N-pole and the S-pole of the magnet are alternately arranged in the rotor of the servo motor, and the magnetic force that changes according to the rotation of the rotor is sensed and encoded by an encoder.

To code the state of the servomotor, one code is formed in units of frames, and the start signal is composed of a predetermined number of bits having a high pulse, and the data signal is composed of a predetermined number of bits composed of Manchester code, and an error is generated. The method of putting the data on the check and the data on the address at a predetermined position and the stop bit at the last stage is mainly used. This method is most commonly used for FA coders, which are devices that code the state of servomotors.

By the way, the coded signal not only provides information about the operating state of the servomotor, but also information about each frame transmitting the code, information about an error check result, and information indicating the beginning of each frame for information exchange with the outside. And a separate signal analysis device is required to analyze a code having such various information.

Accordingly, an object of the present invention is to detect a signal of a FA coder coded in the above manner, and to detect a data signal indicative of the status of a servomotor, and a signal detector of a FA coder. To provide.

The above object is, according to the present invention, in the method for detecting a signal of an FA-coder having a start signal consisting of a predetermined number of bits having a high pulse and a data signal consisting of a predetermined number of bits of a Manchester code, wherein Detecting a start signal among signals output from the FA coder; Driving a clock pulse generator to generate a clock signal synchronized with a frequency of a data signal consisting of a Manchester code among the signals of the FA coder generated after the start signal when the start signal is detected; Outputting the data signal in series while counting the number of inflow bits of the data signal according to the synchronized clock signal until the number of inflow bits of the counted data signal reaches the number of bits of the data signal; It is achieved by the signal detection method of the FA coder characterized in that.

The detecting of the start signal may include: counting the number of pulses at the frequency while indicating a high pulse among the signals from the FA coder with a counter driven according to a predetermined frequency; And driving the clock pulse generator when the counted value reaches the number of pulses that can be generated by the frequency during the high pulse holding time of the start signal, so that the portion where the high pulse continues for a predetermined time is only the start signal. Can be easily detected.

And sequentially inputting the serially output data signal to a shift register; Shifting the data signal input to the shift register according to a clock pulse synchronized with the data signal and stacking the data signal on the shift register, thereby outputting the data signal more clearly in parallel units. can do.

In this case, the step of stacking the shift register comprises: generating a shift clock delaying a clock pulse synchronized with the data signal by a predetermined time; Using the shift clock as a clock input of the shift register to perform a shift operation in synchronization with each bit of the data signal being sequentially input, thereby eliminating the time difference between the shift operation and the input interval of the data signal bits. Can be detected without loss of data.

In performing such a method, the method may further include determining whether the data signal is a Manchester code signal, and resetting the process to be performed at the beginning if the Manchester code is not a Manchester code. It is desirable to add a function to perform the detection operation again from the code of the next frame to occur.

According to the present invention, there is also provided a signal detector of an FA coder for detecting a signal of the FA coder by the above method.

Hereinafter, the present invention will be described in detail with reference to the drawings.

In the present invention, a signal detector of an FA-coder is constructed for TS5643N40 developed by Tamagawa Seiki Co., Ltd., Japan. Such a signal detector constitutes one code in a frame unit as described above, such as a FA coder developed by Panasonic, forms a start signal with a predetermined number of bits having a high pulse, and a predetermined number of Manchester codes. It is applicable to most FA coders that code the operation state of the servo motor by constructing a data signal with bits.

FIG. 1 is an explanatory diagram of each bit constituting the signal of the TS5643N40 FA coder, and analyzes one frame of the signal generated by the FA coder for each bit. One frame has a total time of 42 ms, of which a coded signal is generated during 25 ms and rest for 17 ms. The code signal section of 25 kHz is divided into 25 bits, of which the first three bits are start signals, the next two bits are address signals representing modem addresses, and the next 15 bits contain data on the operation status of the servomotor. Data signal. Next to the data signal is a frame address of 1 bit, the next 3 bits are a cyclic redundancy check (CRC) signal for error checking of the entire code signal part, and the last 1 bit is a stop bit indicating the end of the code signal part.

The frame address represents a frame of the current code signal unit and has a value of '0' or '1'. Since the data representing the state of the servo motor is substantially composed of 30 bits, the data signal of the code signal section having a frame address of '0' and the data signal of the code signal section having a frame address of '1' are combined to form one data. For this purpose, frame address is used.

Each bit is configured to have a time of 1 ms except for the start signal and the stop bit. The start bit has a time of 3.125 ms and the stop bit has a time of 0.875 ms. Keep it. Each bit is coded using the Manchester code except for the start signal.

2 is an explanatory diagram of bits on a Manchester code. In the Manchester code, the transition from the high state to the low state is used to represent a bit of logic '1', and the transition from the low state to a high state is used to represent a '0'. This approach necessarily involves more than one state change between a high state and a low state within a bit, and is considered an error if not accompanied by a state change.

3 is a detailed view of the start signal, the address signal, and the stop bit portion of FIG. The start signal is a 3-bit signal with a time of 3.125 ms and consists of a high pulse section of 2.625 ms and a low pulse section of 0.5 ms. Both bits of the address signal and one bit of the stop bit always have a value of '0'.

4 is an explanatory diagram of a signal detector of a FA-coder according to the present invention, and FIG. 5 is a diagram comparing input signals to the signal detector according to the present invention and pulses of respective parts in the signal detector according to the time course. The entire signal detector is driven by a clock having a frequency of 16 MHz. RX is the input of the code signal.

The code signal detects the start bit by using the fact that there is no section where the high pulse continues except the start bit. That is, the detector is configured to have a down counter which is driven by a clock of 16 MHz and counts when the input has a high pulse. The start pulse has a high pulse duration of 2.625 ms and during this time a 16 MHz clock generates 41 or 42 pulses, so set the value of the down counter to 41 and only count down if the high pulse continues. If a low pulse comes in, 41 is set again. If the down count value is '0' during continuous down counting, the start signal is detected. The same effect can be obtained by using the up counter to set '0' and determining the start signal detected when 41 is reached.

When the start signal is detected, the two-bit address signal composed of the Manchester code is passed from the detected time point, and the detection of the data signal is started. Detection of the data signal is started while generating an LDK (Load Data Clock) in the detection unit. The LDK is a 16 MHz clock pulse generated by the detector from the time of generation of the data signal. The LDK is input to the latch counter LC and the shift counter SC, and the latch counter LC and the shift counter SC divide the LDK by 16 to generate a clock pulse of 1 MHz. The output pulse of the latch counter LC is used as the driving clock LP of the flip-flop F / F, and the code signal RX connected in series with the input terminal of the flip-flop F / F is the driving clock (L). The data signal inputted in synchronization with the occurrence of LP) is output bit by bit to the shift register. The shift register is driven by the output clock SP of the shift counter SC to perform an operation of shifting each time data is inputted one by one from the flip-flop F / F. The flip-flop (F / F) drive clock LP from the latch counter LC and the output clock SP from the shift counter SC start to occur when the data signal in the code signal is input. The LP is synchronized with the data signal, and the output clock SP is configured to divide the 16 MHz LDK by one or two pulses and then divide the signal 16 to generate a pulse slightly delayed from the driving clock LP. This allows the shift operation to be performed after the input from the flip-flop (F / F) to the shift register is completed to ensure the accuracy of the shift operation.

The data counter DC receives the driving clock LP and counts the number of pulses of the driving clock LP to count 16 corresponding to the number of bits of the data signal and the frame address. When the count reaches 16, a reset signal is output to the reset detector, and the reset detector resets the detector and the data counter DC according to the signal.

In response to the input from the flip-flop F / F and the shift operation of the shift counter SC, the data signals and frame addresses stacked on the shift register are parallel to the latch register after the reset operation by the data counter DC is performed. It is shifted to detect only the data signal.

By adjusting the counting value of the data counter DC and the stacked bits of the shift register, the number of bits of the code signal to be detected can be adjusted. In other words, if you want to output up to CRC signal, if the data counter (DC) counts up to 19 and the number of bits in the shift register is 19 bits, the signal for error checking can be output, and only the data signal except the frame address is detected. If you want to do that, just count up to 15.

The Manchester code inspection unit continuously checks whether the signal input to the flip-flop (F / F) is a Manchester code, and sends a signal to the reset unit if the Manchester code is not, so that the start signal is detected again when an error occurs. Start with.

The signal detection method of the FA coder as described above and the signal detector of the FA coder form one code in units of frames, constitute a start signal with a predetermined number of bits having a high pulse, and comprise a predetermined code made of Manchester code. The data signal is composed of a number of bits, and has a function of detecting a data signal representing the state of the servo motor from among the signals of the FA coder that codes information on the operation state of the servo motor.

Claims (10)

A method of detecting a signal of a FA coder having a start signal composed of a predetermined number of bits having a high pulse and a data signal composed of a predetermined number of bits of a Manchester code, the method comprising: starting among signals output from the FA coder Detecting a signal; Driving a clock pulse generator to generate a clock signal synchronized with a frequency of a data signal consisting of a Manchester code among the signals of the FA coder generated after the start signal when the start signal is detected; Outputting the data signal in series while counting the number of inflow bits of the data signal according to the synchronized clock signal until the number of inflow bits of the counted data signal reaches the number of bits of the data signal. Characterized in that the FA-coder signal detection method. 2. The method of claim 1, wherein the detecting of the start signal comprises: counting the number of pulses by the frequency while indicating a high pulse among the signals from the FA-coder with a counter driven according to a predetermined frequency; And driving the clock pulse generator when the counted value reaches the number of pulses generated by the frequency during the high pulse holding time of the start signal. The method of claim 1 or 2, further comprising: sequentially inputting the serially output data signal into a shift register; And shifting a data signal input to the shift register according to a clock pulse synchronized with the data signal and stacking the data signal on the shift register. The method of claim 3, wherein the stacking of the shift register comprises: generating a shift clock delaying a clock pulse synchronized with the data signal by a predetermined time; And using the shift clock as a clock input of the shift register. The method as claimed in claim 1 or 2, further comprising: determining whether the data signal is a Manchester code signal, and resetting the process to start from the beginning if the Manchester code is not the Manchester code. -Coder signal detection method. A detector for detecting a signal of a FA coder having a start signal consisting of a predetermined number of bits having a high pulse and a data signal consisting of a predetermined number of bits of a Manchester code, comprising: a start among signals output from the FA coder A detection unit detecting a signal; A clock pulse generator for generating a clock signal synchronized with a frequency of a data signal composed of a Manchester code among the FA-coder signals generated following the start signal in response to the start signal detected by the detector; A data signal counter for counting the number of bits introduced into the data signal according to the clock signal from the clock pulse generator; And an output unit for outputting the data signal in series until the number of bits of the data signal counted by the data signal counter reaches the number of the data signals. 7. The signal according to claim 6, wherein the start signal detecting unit is driven according to a predetermined frequency, and counts the number of pulses by the frequency while indicating a high pulse among the signals from the FA coder, and the counted value is And a high pulse counter for driving the clock pulse generator when the number of pulses generated by the frequency is reached during the start time of the start signal. 8. The apparatus of claim 6 or 7, further comprising: a shift register configured to sequentially input, shift, and stack the serially output data signals according to the synchronized clock pulses; And a shifting driving part of the shift register. 9. The apparatus of claim 8, wherein the shifting driver comprises a clock pulse delay unit for generating a shift clock in which the synchronized clock pulse is delayed for a predetermined time; And the shift register uses the output pulse of the clock pulse delay unit as a clock input of the shift register. 8. The signal detector of claim 6 or 7, further comprising a reset unit for resetting the detection unit when the data signal is not a Manchester code.