SU1566354A1 - Device for localization of errors in binary sequence - Google Patents

Abstract

The invention relates to computing and can be used in systems for technical diagnostics of discrete objects. The purpose of the invention is to expand the functionality of the device by localizing error packets. The device contains triggers 1, 13, 16, elements AND 2, 8, 9, 11, shaper 3 signatures, decoder 7. In the device entered the register 4 shift, switching unit 6, counter 5, element NOT 10, element OR 15, triggers 17 , 18, elements And 12, 14. 1 zp ff, 3 ill.

Description

SO JV

The invention relates to computing and can be used in systems for technical diagnostics of discrete objects.

The aim of the invention is to expand the functionality of the device by localizing the error packets in binary sequence.

FIG. 1 shows a diagram of an apparatus for localizing errors; in fig. 2 shows an example of building a signature generator with the characteristic polynomial g (x) x8 + x6-t-x + x3 + x + 1 (x5 + 1) (x3 + x + 1); in fig. 3 - diagram of the switching unit.

The device (Fig. 1) contains the first trigger 1, the first element And 2, the shaper 3 signatures, the register 4 shift counter 5, the switching unit 6, the decoder 7, the second 8 and the third 9, the elements And, the element NOT 10, the fourth 11 and n the second 12 elements And, the second 13 trigger, the sixth element And 14, the element 1UB1 15, the third 1b, the fourth 17 and the fifth 18 trigger, has information input 19, clock input 20, initial start input 21, reset input 22, input 23 modes, input 24 records, group of 25 inputs of the reference signature 4 group of information outputs 26–29.

Shaper signatures (figure 2)

35

Holds D-triggers 30 - 37 and elements EXCLUSIVE IDD1 38 - 42.

The switching unit (Fig. 3) contains the triggers 43 and 44, the single pulse shaper 45, the elements AND 46 - 0 48 and the elements OR 49 and 50.

To determine the location of the error packet in a long sequence, for each checkpoint, the signature is determined by the formula (all operations for module 2)

, h Јв (х) Г (V I - -

GX) g (x)

n-k

fe (x) -an, x - + ... + avnshp- +

., x

+. .. + a

0

a n-, and pk coefficients determined by members of the input sequence; al „k ,, ..., a0 are equal to zero; K - the number of members of the sequence; g (x) (x -1) p (x), with b being the maximum packet length

0 5

five

0

0

five

mistakes; p (x) is an irreducible polynomial of degree cb; (2b-1),

where e is an indicator of an irreducible polynomial p (x), -1. Practically, a reference signature can be obtained if the known polynomial fQ (x) is fed to the input of shaper 3 starting with the coefficients of higher digits until the last factor falls into the low-order bit of shaper 3. For this, all n shifts will be required. As a result, the remainder r (x) (reference signature) of dividing f0 (x) by b (x) will remain in Shaper 3. If you change any member of the sequence f0 (x), this will lead to a change in r (x).

When the device is in operation, a controlled sequence consisting of K elements is supplied to the input of the imaging unit 3. After it is turned off, more (n-K) elements are submitted, being the coefficients r (x). If there were no errors in the sequence, then the remainder in the imaging unit is 3 g (x) 0.

If r (x) / 0, then the input of driver 3 of signatures is disconnected from external circuits (continuously O is applied and the content of driver 3 is shifted.

If in the process of successive shifts in n-K-b, the lower bits of shaper 3 contain zeros, then the remaining b cells will contain an error packet, and the number of shifts performed determines the number of the first erroneous member of the packet.

If in the process of successive shifts, p-2b-I shifts are carried out, and the zeros in the pk-b of the younger cells of the former 3 did not appear, this means that the packet length is greater than b and it is impossible to detect its place.

By varying the size of the signature generator 3, it is possible to locate the errors contained in a packet of any length.

The device works as follows.

Before starting work on the device input 22, it is set to state O triggers 1,13,16,17, 18,43 and 44, driver 3, counter 5. Zeroes are set at the outputs 26,28 and 29 of the device. The unit 6 connects the information input 19 of the device with the information input of the imaging unit 3, and the state O is set at the zero output of the unit 6.

Before operating the device at the entrance

23 in the mode setting, signal 1 is set, and a reference signature code is supplied to a group of 25 inputs, which, according to the signal received at the input

The device's 24 records are written to register 4, with the highest bit of the reference signature being at the output of register 4, Register 4 can be implemented on K155IR1 microcircuits. After that, at the mode setting input 23, a signal O is set, which enables the operation of register 4 in the scaling mode.

According to the Start signal arriving at the device 21 start-up input, trigger 1 switches to state 1 and permits the arrival of clock pulses through the AND 2 element to the counting input of counter 5 and the clock input

thirty

35

40

world maker 3. The division of input-25 is set to signal 1. It is the known sequence, which arrives at the information input of the driver 3, into the characteristic polynomial. The number of shift pulses applied to the input of the imaging unit 3 is fixed by the counter 5. When the information generator arrives at the information generator, the second output of the subscriber 7, corresponding to the K number, receives a signal 1, which enters the input of the unit 6. But this signal unit 6 disconnects the information input 19 of the device from the information input of the imaging unit 3 and connects to it the output of the register 4, in which the reference signature is located, and also enables the arrival of clock pulses from the output of the AND 2 element to the input of the shift of the register 4.

After n shifts in the driver 3, a signal 1 appears at the first output of the depuser 7, which switches the flip-flop 13 to the state 1, and also enters the input of the block 6. By this signal, the block 6 turns off the output of the register 4 from the information input of the shaper 3, gives On the information input of the imaging unit 3, the signal O is permanent, switches the second output to state 1, resets counter 5 on the first output.

If there is no error in the sequence, the remainder in the imaging unit 3 is equal to zero, and the output of the element 11 is

45

50

55

There are errors in the sequence. At the direct output of a single switch 1, the signal O is set, which stops the arrival of the clock pulses through the AND 2 element to the counter 5. The contents of the counter 5 indicate the number of the erroneous clock cycle. It enters the outputs 27 of the device.

If, for n + 2b + 1 clocks, signal 1 does not appear at the output of element I 12, then at output of element II 14 signal 1 appears, which switches to state 1 flip-flop 16 and to state O flip-flop 1. At output 26 device is set a signal This signal means that an error packet is longer than b and its place cannot be detected.

Block 6 (Fig. 3) works as follows.

Before the start of operation, the reset signal arriving at the input of the initial installation of block 6, through the IUDI49 element passes to the first output of block 6, and also sets the status O of the flip-flops 43 and 44. At the same time, the O signal is set at the output of block 6. 47 and 48 are blocked by the signal O from the direct output of the trigger 44. The third output of block 6 passes information from input 19.

When a signal 1 arrives at the second input of the setting of the mode of the block 6, the trigger 44 is set to

6

II 1 II

which trigger is 17 and

ten

15

20

Signal 1 appears in state I1 in state O trigger 1. At the direct output of trigger 1, the signal O, which blocks the passage of clock pulses through AND 2, is outputted. Signal 1 is set at output 28 of the device. It means that no errors.

If there is a balance, the remainder in the imaging unit 3 is different from zero, and the output of the element 11 is the signal O. At the output of the element n1 15, the signal O remains, the clock pulses go to the counting input of the counter 5 and the clock input of the imager 3. In the process of shifting the contents of the imaging device 3 And 12 generates a signal 1 if in the lower p-K-L bits of the imaging unit 3, zeros appear. Signal 1 from element 11-12 switches to state 1 trigger 18 and to state O trigger 1. At the output 29 of the device

0

five

0

5 sets the signal to 1. It will

five

0

five

There are errors in the sequence. At the direct output of a single switch 1, the signal O is set, which stops the arrival of the clock pulses through the AND 2 element to the counter 5. The contents of the counter 5 indicate the number of the erroneous clock cycle. It enters the outputs 27 of the device.

If, for n + 2b + 1 clocks, signal 1 does not appear at the output of element I 12, then at output of element II 14 signal 1 appears, which switches to state 1 flip-flop 16 and to state O flip-flop 1. At output 26, a signal is set. This signal means that the packet of errors is longer than b and its place cannot be detected.

Block 6 (Fig. 3) works as follows.

Before the start of operation, the reset signal arriving at the input of the initial installation of block 6, through the IUDI49 element passes to the first output of block 6, and also sets the status O of the flip-flops 43 and 44. At the same time, the O signal is set at the output of block 6. 47 and 48 are blocked by the signal O from the direct output of the trigger 44. The third output of block 6 passes information from input 19.

When a signal 1 arrives at the second input of the setting of the mode of the block 6, the trigger 44 is set to

1. Element 46 is blocked by signal O from the inverse output of flip-flop 44. Signal 1 from the direct output of flip-flop 44 allows the elements of 47 and 48 to work, and the third output of block 6 passes the information from the register 4 output, and the fourth output of block 6 the clock pulses coming to the clock input of block 6.

On the leading edge of signal 1, arriving at the first input of setting the mode of block 6, the trigger 43 is set to 1m, the driver 45 of a single pulse produces a reset signal, which through the / HJCI element 49 is fed to the first output of block 6. The signal O from the inverse the trigger output 43 blocks the operation of the elements 46 and 47, and on the third output of block 6, a signal O is set. On the second output of block 6 a signal 1 is set.

Thus, the device allows to determine the location and type of the package of the macros in the input sequence being analyzed.

Claims (2)

1. A device for localizing errors in binary sequence, containing the first, second and third triggers, the first, second, third and fourth elements AND, the decoder, the signature generator, the first input of the first element AND being the clock input of the device, the installation input of the first trigger is input of the initial start-up of the device, the output of the first trigger is connected to the second input of the first element AND, the output of which is connected to the clock input of the signature generator, which is of the device’s capabilities due to the localization of error packets, it additionally contains a shift register, a switching unit, a counter, a NOT element, an OR element, the fourth and fifth triggers, the fifth and sixth AND elements, and the reset input of the first trigger is connected to the reset inputs of the signature generator of the second, third, fourth, and fifth triggers, the input of the initial installation of the switching unit and forms the device's reset input, the first information input of the switching unit under Q five 0 d The key is connected to the information input of the device, the inputs of the mode and recording of the shift register are connected respectively to the inputs of the mode and recording of the device, the group of information inputs of the shift register is connected to the input group of the reference device signature definition, the clock input of the switching unit is combined with the clock input of the counter and connected to the output of the first element And, the second information input of the switching unit is connected to the output of the higher bit of the shift register, the first output of the decoder is connected to the clock input of the second trigger and p The first input of the switching unit mode setting, the second input of the mode setting of which is connected to the second output of the decoder, the first, third and fourth outputs of the switching unit are connected respectively to the reset input of the counter, information input of the signature generator and the shift register shift input, the second output of the switching unit is connected to the first the inputs of the fourth and fifth elements And, the second inputs of which are combined and connected to the output of the third And element, the third input of the fifth element And is connected to the output of the element NOT, the input of which connected with the third input of the fourth element I and connected to the output of the second element I, the input group of which is connected to the first group of information outputs of the signature generator, the second group of information outputs of which is connected to the input group of the third element I, the group of the discharge outputs of the counter connected to the group of inputs the decoder, the third output of which is connected to the first input of the sixth element And, the second input of which is connected to the output of the second trigger, the output of the sixth element And is connected to the clock input the second trigger and the first input of the OR element, the second input of which is combined with the clock input of the fourth trigger and connected to the output of the fourth element AND, the output of the fifth element AND is connected to the clock input of the fifth trigger and the third input of the SHP1 element, the output of which is connected to the clock input of the first the trigger, the outputs of the third, fourth, fifth triggers and the group of the bit outputs of the counter form a group of information outputs of the device. 91 2. The device according to claim. 2, the switching unit contains two triggers, a single pulse shaper, three elements And two elements 1001, the first input of the first element ILJDI combined with the reset inputs of the first and second triggers, the counting input of the first trigger is connected to the input of a single pulse shaper and connected to the first input of the block mode setting, the counting input of the second trigger is connected to the second input of the block mode setting, the first input of the first element AND is connected to moat information entry unit, the first input of the second AND element is connected to the second information input unit, the first input of the third AND element is connected to the clock input 66354 block ten ten 15 20 , the output of the first element IL is the first output of the block, the direct output of the first trigger is the B-block output, the output of the second element OR is the third output of the block, the output of the third element AND is the fourth output1 of the block, the output of the single pulse former is connected to the second input of the first element OR, the inverse output of the first trigger is connected to the second inputs of the first and second elements AND, the third input of the first element I is connected to the inverse output of the second trigger, the direct output of which is connected to the third input th second AND gate and a second input of the third AND gate, outputs of first and second AND gates connected to the second OR input. on B on ft, 12 naz on 4 figs